Contents of /alx-src/tags/kernel26-2.6.12-alx-r9/drivers/char/mbcs.c
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Wed Mar 4 11:03:09 2009 UTC (15 years, 3 months ago) by niro
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File size: 20050 byte(s)
Wed Mar 4 11:03:09 2009 UTC (15 years, 3 months ago) by niro
File MIME type: text/plain
File size: 20050 byte(s)
Tag kernel26-2.6.12-alx-r9
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public |
3 | * License. See the file "COPYING" in the main directory of this archive |
4 | * for more details. |
5 | * |
6 | * Copyright (c) 2005 Silicon Graphics, Inc. All rights reserved. |
7 | */ |
8 | |
9 | /* |
10 | * MOATB Core Services driver. |
11 | */ |
12 | |
13 | #include <linux/config.h> |
14 | #include <linux/interrupt.h> |
15 | #include <linux/module.h> |
16 | #include <linux/moduleparam.h> |
17 | #include <linux/types.h> |
18 | #include <linux/ioport.h> |
19 | #include <linux/notifier.h> |
20 | #include <linux/reboot.h> |
21 | #include <linux/init.h> |
22 | #include <linux/fs.h> |
23 | #include <linux/delay.h> |
24 | #include <linux/device.h> |
25 | #include <linux/mm.h> |
26 | #include <linux/uio.h> |
27 | #include <asm/io.h> |
28 | #include <asm/uaccess.h> |
29 | #include <asm/system.h> |
30 | #include <asm/pgtable.h> |
31 | #include <asm/sn/addrs.h> |
32 | #include <asm/sn/intr.h> |
33 | #include <asm/sn/tiocx.h> |
34 | #include "mbcs.h" |
35 | |
36 | #define MBCS_DEBUG 0 |
37 | #if MBCS_DEBUG |
38 | #define DBG(fmt...) printk(KERN_ALERT fmt) |
39 | #else |
40 | #define DBG(fmt...) |
41 | #endif |
42 | int mbcs_major; |
43 | |
44 | LIST_HEAD(soft_list); |
45 | |
46 | /* |
47 | * file operations |
48 | */ |
49 | struct file_operations mbcs_ops = { |
50 | .open = mbcs_open, |
51 | .llseek = mbcs_sram_llseek, |
52 | .read = mbcs_sram_read, |
53 | .write = mbcs_sram_write, |
54 | .mmap = mbcs_gscr_mmap, |
55 | }; |
56 | |
57 | struct mbcs_callback_arg { |
58 | int minor; |
59 | struct cx_dev *cx_dev; |
60 | }; |
61 | |
62 | static inline void mbcs_getdma_init(struct getdma *gdma) |
63 | { |
64 | memset(gdma, 0, sizeof(struct getdma)); |
65 | gdma->DoneIntEnable = 1; |
66 | } |
67 | |
68 | static inline void mbcs_putdma_init(struct putdma *pdma) |
69 | { |
70 | memset(pdma, 0, sizeof(struct putdma)); |
71 | pdma->DoneIntEnable = 1; |
72 | } |
73 | |
74 | static inline void mbcs_algo_init(struct algoblock *algo_soft) |
75 | { |
76 | memset(algo_soft, 0, sizeof(struct algoblock)); |
77 | } |
78 | |
79 | static inline void mbcs_getdma_set(void *mmr, |
80 | uint64_t hostAddr, |
81 | uint64_t localAddr, |
82 | uint64_t localRamSel, |
83 | uint64_t numPkts, |
84 | uint64_t amoEnable, |
85 | uint64_t intrEnable, |
86 | uint64_t peerIO, |
87 | uint64_t amoHostDest, |
88 | uint64_t amoModType, uint64_t intrHostDest, |
89 | uint64_t intrVector) |
90 | { |
91 | union dma_control rdma_control; |
92 | union dma_amo_dest amo_dest; |
93 | union intr_dest intr_dest; |
94 | union dma_localaddr local_addr; |
95 | union dma_hostaddr host_addr; |
96 | |
97 | rdma_control.dma_control_reg = 0; |
98 | amo_dest.dma_amo_dest_reg = 0; |
99 | intr_dest.intr_dest_reg = 0; |
100 | local_addr.dma_localaddr_reg = 0; |
101 | host_addr.dma_hostaddr_reg = 0; |
102 | |
103 | host_addr.dma_sys_addr = hostAddr; |
104 | MBCS_MMR_SET(mmr, MBCS_RD_DMA_SYS_ADDR, host_addr.dma_hostaddr_reg); |
105 | |
106 | local_addr.dma_ram_addr = localAddr; |
107 | local_addr.dma_ram_sel = localRamSel; |
108 | MBCS_MMR_SET(mmr, MBCS_RD_DMA_LOC_ADDR, local_addr.dma_localaddr_reg); |
109 | |
110 | rdma_control.dma_op_length = numPkts; |
111 | rdma_control.done_amo_en = amoEnable; |
112 | rdma_control.done_int_en = intrEnable; |
113 | rdma_control.pio_mem_n = peerIO; |
114 | MBCS_MMR_SET(mmr, MBCS_RD_DMA_CTRL, rdma_control.dma_control_reg); |
115 | |
116 | amo_dest.dma_amo_sys_addr = amoHostDest; |
117 | amo_dest.dma_amo_mod_type = amoModType; |
118 | MBCS_MMR_SET(mmr, MBCS_RD_DMA_AMO_DEST, amo_dest.dma_amo_dest_reg); |
119 | |
120 | intr_dest.address = intrHostDest; |
121 | intr_dest.int_vector = intrVector; |
122 | MBCS_MMR_SET(mmr, MBCS_RD_DMA_INT_DEST, intr_dest.intr_dest_reg); |
123 | |
124 | } |
125 | |
126 | static inline void mbcs_putdma_set(void *mmr, |
127 | uint64_t hostAddr, |
128 | uint64_t localAddr, |
129 | uint64_t localRamSel, |
130 | uint64_t numPkts, |
131 | uint64_t amoEnable, |
132 | uint64_t intrEnable, |
133 | uint64_t peerIO, |
134 | uint64_t amoHostDest, |
135 | uint64_t amoModType, |
136 | uint64_t intrHostDest, uint64_t intrVector) |
137 | { |
138 | union dma_control wdma_control; |
139 | union dma_amo_dest amo_dest; |
140 | union intr_dest intr_dest; |
141 | union dma_localaddr local_addr; |
142 | union dma_hostaddr host_addr; |
143 | |
144 | wdma_control.dma_control_reg = 0; |
145 | amo_dest.dma_amo_dest_reg = 0; |
146 | intr_dest.intr_dest_reg = 0; |
147 | local_addr.dma_localaddr_reg = 0; |
148 | host_addr.dma_hostaddr_reg = 0; |
149 | |
150 | host_addr.dma_sys_addr = hostAddr; |
151 | MBCS_MMR_SET(mmr, MBCS_WR_DMA_SYS_ADDR, host_addr.dma_hostaddr_reg); |
152 | |
153 | local_addr.dma_ram_addr = localAddr; |
154 | local_addr.dma_ram_sel = localRamSel; |
155 | MBCS_MMR_SET(mmr, MBCS_WR_DMA_LOC_ADDR, local_addr.dma_localaddr_reg); |
156 | |
157 | wdma_control.dma_op_length = numPkts; |
158 | wdma_control.done_amo_en = amoEnable; |
159 | wdma_control.done_int_en = intrEnable; |
160 | wdma_control.pio_mem_n = peerIO; |
161 | MBCS_MMR_SET(mmr, MBCS_WR_DMA_CTRL, wdma_control.dma_control_reg); |
162 | |
163 | amo_dest.dma_amo_sys_addr = amoHostDest; |
164 | amo_dest.dma_amo_mod_type = amoModType; |
165 | MBCS_MMR_SET(mmr, MBCS_WR_DMA_AMO_DEST, amo_dest.dma_amo_dest_reg); |
166 | |
167 | intr_dest.address = intrHostDest; |
168 | intr_dest.int_vector = intrVector; |
169 | MBCS_MMR_SET(mmr, MBCS_WR_DMA_INT_DEST, intr_dest.intr_dest_reg); |
170 | |
171 | } |
172 | |
173 | static inline void mbcs_algo_set(void *mmr, |
174 | uint64_t amoHostDest, |
175 | uint64_t amoModType, |
176 | uint64_t intrHostDest, |
177 | uint64_t intrVector, uint64_t algoStepCount) |
178 | { |
179 | union dma_amo_dest amo_dest; |
180 | union intr_dest intr_dest; |
181 | union algo_step step; |
182 | |
183 | step.algo_step_reg = 0; |
184 | intr_dest.intr_dest_reg = 0; |
185 | amo_dest.dma_amo_dest_reg = 0; |
186 | |
187 | amo_dest.dma_amo_sys_addr = amoHostDest; |
188 | amo_dest.dma_amo_mod_type = amoModType; |
189 | MBCS_MMR_SET(mmr, MBCS_ALG_AMO_DEST, amo_dest.dma_amo_dest_reg); |
190 | |
191 | intr_dest.address = intrHostDest; |
192 | intr_dest.int_vector = intrVector; |
193 | MBCS_MMR_SET(mmr, MBCS_ALG_INT_DEST, intr_dest.intr_dest_reg); |
194 | |
195 | step.alg_step_cnt = algoStepCount; |
196 | MBCS_MMR_SET(mmr, MBCS_ALG_STEP, step.algo_step_reg); |
197 | } |
198 | |
199 | static inline int mbcs_getdma_start(struct mbcs_soft *soft) |
200 | { |
201 | void *mmr_base; |
202 | struct getdma *gdma; |
203 | uint64_t numPkts; |
204 | union cm_control cm_control; |
205 | |
206 | mmr_base = soft->mmr_base; |
207 | gdma = &soft->getdma; |
208 | |
209 | /* check that host address got setup */ |
210 | if (!gdma->hostAddr) |
211 | return -1; |
212 | |
213 | numPkts = |
214 | (gdma->bytes + (MBCS_CACHELINE_SIZE - 1)) / MBCS_CACHELINE_SIZE; |
215 | |
216 | /* program engine */ |
217 | mbcs_getdma_set(mmr_base, tiocx_dma_addr(gdma->hostAddr), |
218 | gdma->localAddr, |
219 | (gdma->localAddr < MB2) ? 0 : |
220 | (gdma->localAddr < MB4) ? 1 : |
221 | (gdma->localAddr < MB6) ? 2 : 3, |
222 | numPkts, |
223 | gdma->DoneAmoEnable, |
224 | gdma->DoneIntEnable, |
225 | gdma->peerIO, |
226 | gdma->amoHostDest, |
227 | gdma->amoModType, |
228 | gdma->intrHostDest, gdma->intrVector); |
229 | |
230 | /* start engine */ |
231 | cm_control.cm_control_reg = MBCS_MMR_GET(mmr_base, MBCS_CM_CONTROL); |
232 | cm_control.rd_dma_go = 1; |
233 | MBCS_MMR_SET(mmr_base, MBCS_CM_CONTROL, cm_control.cm_control_reg); |
234 | |
235 | return 0; |
236 | |
237 | } |
238 | |
239 | static inline int mbcs_putdma_start(struct mbcs_soft *soft) |
240 | { |
241 | void *mmr_base; |
242 | struct putdma *pdma; |
243 | uint64_t numPkts; |
244 | union cm_control cm_control; |
245 | |
246 | mmr_base = soft->mmr_base; |
247 | pdma = &soft->putdma; |
248 | |
249 | /* check that host address got setup */ |
250 | if (!pdma->hostAddr) |
251 | return -1; |
252 | |
253 | numPkts = |
254 | (pdma->bytes + (MBCS_CACHELINE_SIZE - 1)) / MBCS_CACHELINE_SIZE; |
255 | |
256 | /* program engine */ |
257 | mbcs_putdma_set(mmr_base, tiocx_dma_addr(pdma->hostAddr), |
258 | pdma->localAddr, |
259 | (pdma->localAddr < MB2) ? 0 : |
260 | (pdma->localAddr < MB4) ? 1 : |
261 | (pdma->localAddr < MB6) ? 2 : 3, |
262 | numPkts, |
263 | pdma->DoneAmoEnable, |
264 | pdma->DoneIntEnable, |
265 | pdma->peerIO, |
266 | pdma->amoHostDest, |
267 | pdma->amoModType, |
268 | pdma->intrHostDest, pdma->intrVector); |
269 | |
270 | /* start engine */ |
271 | cm_control.cm_control_reg = MBCS_MMR_GET(mmr_base, MBCS_CM_CONTROL); |
272 | cm_control.wr_dma_go = 1; |
273 | MBCS_MMR_SET(mmr_base, MBCS_CM_CONTROL, cm_control.cm_control_reg); |
274 | |
275 | return 0; |
276 | |
277 | } |
278 | |
279 | static inline int mbcs_algo_start(struct mbcs_soft *soft) |
280 | { |
281 | struct algoblock *algo_soft = &soft->algo; |
282 | void *mmr_base = soft->mmr_base; |
283 | union cm_control cm_control; |
284 | |
285 | if (down_interruptible(&soft->algolock)) |
286 | return -ERESTARTSYS; |
287 | |
288 | atomic_set(&soft->algo_done, 0); |
289 | |
290 | mbcs_algo_set(mmr_base, |
291 | algo_soft->amoHostDest, |
292 | algo_soft->amoModType, |
293 | algo_soft->intrHostDest, |
294 | algo_soft->intrVector, algo_soft->algoStepCount); |
295 | |
296 | /* start algorithm */ |
297 | cm_control.cm_control_reg = MBCS_MMR_GET(mmr_base, MBCS_CM_CONTROL); |
298 | cm_control.alg_done_int_en = 1; |
299 | cm_control.alg_go = 1; |
300 | MBCS_MMR_SET(mmr_base, MBCS_CM_CONTROL, cm_control.cm_control_reg); |
301 | |
302 | up(&soft->algolock); |
303 | |
304 | return 0; |
305 | } |
306 | |
307 | static inline ssize_t |
308 | do_mbcs_sram_dmawrite(struct mbcs_soft *soft, uint64_t hostAddr, |
309 | size_t len, loff_t * off) |
310 | { |
311 | int rv = 0; |
312 | |
313 | if (down_interruptible(&soft->dmawritelock)) |
314 | return -ERESTARTSYS; |
315 | |
316 | atomic_set(&soft->dmawrite_done, 0); |
317 | |
318 | soft->putdma.hostAddr = hostAddr; |
319 | soft->putdma.localAddr = *off; |
320 | soft->putdma.bytes = len; |
321 | |
322 | if (mbcs_putdma_start(soft) < 0) { |
323 | DBG(KERN_ALERT "do_mbcs_sram_dmawrite: " |
324 | "mbcs_putdma_start failed\n"); |
325 | rv = -EAGAIN; |
326 | goto dmawrite_exit; |
327 | } |
328 | |
329 | if (wait_event_interruptible(soft->dmawrite_queue, |
330 | atomic_read(&soft->dmawrite_done))) { |
331 | rv = -ERESTARTSYS; |
332 | goto dmawrite_exit; |
333 | } |
334 | |
335 | rv = len; |
336 | *off += len; |
337 | |
338 | dmawrite_exit: |
339 | up(&soft->dmawritelock); |
340 | |
341 | return rv; |
342 | } |
343 | |
344 | static inline ssize_t |
345 | do_mbcs_sram_dmaread(struct mbcs_soft *soft, uint64_t hostAddr, |
346 | size_t len, loff_t * off) |
347 | { |
348 | int rv = 0; |
349 | |
350 | if (down_interruptible(&soft->dmareadlock)) |
351 | return -ERESTARTSYS; |
352 | |
353 | atomic_set(&soft->dmawrite_done, 0); |
354 | |
355 | soft->getdma.hostAddr = hostAddr; |
356 | soft->getdma.localAddr = *off; |
357 | soft->getdma.bytes = len; |
358 | |
359 | if (mbcs_getdma_start(soft) < 0) { |
360 | DBG(KERN_ALERT "mbcs_strategy: mbcs_getdma_start failed\n"); |
361 | rv = -EAGAIN; |
362 | goto dmaread_exit; |
363 | } |
364 | |
365 | if (wait_event_interruptible(soft->dmaread_queue, |
366 | atomic_read(&soft->dmaread_done))) { |
367 | rv = -ERESTARTSYS; |
368 | goto dmaread_exit; |
369 | } |
370 | |
371 | rv = len; |
372 | *off += len; |
373 | |
374 | dmaread_exit: |
375 | up(&soft->dmareadlock); |
376 | |
377 | return rv; |
378 | } |
379 | |
380 | int mbcs_open(struct inode *ip, struct file *fp) |
381 | { |
382 | struct mbcs_soft *soft; |
383 | int minor; |
384 | |
385 | minor = iminor(ip); |
386 | |
387 | list_for_each_entry(soft, &soft_list, list) { |
388 | if (soft->nasid == minor) { |
389 | fp->private_data = soft->cxdev; |
390 | return 0; |
391 | } |
392 | } |
393 | |
394 | return -ENODEV; |
395 | } |
396 | |
397 | ssize_t mbcs_sram_read(struct file * fp, char __user *buf, size_t len, loff_t * off) |
398 | { |
399 | struct cx_dev *cx_dev = fp->private_data; |
400 | struct mbcs_soft *soft = cx_dev->soft; |
401 | uint64_t hostAddr; |
402 | int rv = 0; |
403 | |
404 | hostAddr = __get_dma_pages(GFP_KERNEL, get_order(len)); |
405 | if (hostAddr == 0) |
406 | return -ENOMEM; |
407 | |
408 | rv = do_mbcs_sram_dmawrite(soft, hostAddr, len, off); |
409 | if (rv < 0) |
410 | goto exit; |
411 | |
412 | if (copy_to_user(buf, (void *)hostAddr, len)) |
413 | rv = -EFAULT; |
414 | |
415 | exit: |
416 | free_pages(hostAddr, get_order(len)); |
417 | |
418 | return rv; |
419 | } |
420 | |
421 | ssize_t |
422 | mbcs_sram_write(struct file * fp, const char __user *buf, size_t len, loff_t * off) |
423 | { |
424 | struct cx_dev *cx_dev = fp->private_data; |
425 | struct mbcs_soft *soft = cx_dev->soft; |
426 | uint64_t hostAddr; |
427 | int rv = 0; |
428 | |
429 | hostAddr = __get_dma_pages(GFP_KERNEL, get_order(len)); |
430 | if (hostAddr == 0) |
431 | return -ENOMEM; |
432 | |
433 | if (copy_from_user((void *)hostAddr, buf, len)) { |
434 | rv = -EFAULT; |
435 | goto exit; |
436 | } |
437 | |
438 | rv = do_mbcs_sram_dmaread(soft, hostAddr, len, off); |
439 | |
440 | exit: |
441 | free_pages(hostAddr, get_order(len)); |
442 | |
443 | return rv; |
444 | } |
445 | |
446 | loff_t mbcs_sram_llseek(struct file * filp, loff_t off, int whence) |
447 | { |
448 | loff_t newpos; |
449 | |
450 | switch (whence) { |
451 | case 0: /* SEEK_SET */ |
452 | newpos = off; |
453 | break; |
454 | |
455 | case 1: /* SEEK_CUR */ |
456 | newpos = filp->f_pos + off; |
457 | break; |
458 | |
459 | case 2: /* SEEK_END */ |
460 | newpos = MBCS_SRAM_SIZE + off; |
461 | break; |
462 | |
463 | default: /* can't happen */ |
464 | return -EINVAL; |
465 | } |
466 | |
467 | if (newpos < 0) |
468 | return -EINVAL; |
469 | |
470 | filp->f_pos = newpos; |
471 | |
472 | return newpos; |
473 | } |
474 | |
475 | static uint64_t mbcs_pioaddr(struct mbcs_soft *soft, uint64_t offset) |
476 | { |
477 | uint64_t mmr_base; |
478 | |
479 | mmr_base = (uint64_t) (soft->mmr_base + offset); |
480 | |
481 | return mmr_base; |
482 | } |
483 | |
484 | static void mbcs_debug_pioaddr_set(struct mbcs_soft *soft) |
485 | { |
486 | soft->debug_addr = mbcs_pioaddr(soft, MBCS_DEBUG_START); |
487 | } |
488 | |
489 | static void mbcs_gscr_pioaddr_set(struct mbcs_soft *soft) |
490 | { |
491 | soft->gscr_addr = mbcs_pioaddr(soft, MBCS_GSCR_START); |
492 | } |
493 | |
494 | int mbcs_gscr_mmap(struct file *fp, struct vm_area_struct *vma) |
495 | { |
496 | struct cx_dev *cx_dev = fp->private_data; |
497 | struct mbcs_soft *soft = cx_dev->soft; |
498 | |
499 | if (vma->vm_pgoff != 0) |
500 | return -EINVAL; |
501 | |
502 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); |
503 | |
504 | /* Remap-pfn-range will mark the range VM_IO and VM_RESERVED */ |
505 | if (remap_pfn_range(vma, |
506 | vma->vm_start, |
507 | __pa(soft->gscr_addr) >> PAGE_SHIFT, |
508 | PAGE_SIZE, |
509 | vma->vm_page_prot)) |
510 | return -EAGAIN; |
511 | |
512 | return 0; |
513 | } |
514 | |
515 | /** |
516 | * mbcs_completion_intr_handler - Primary completion handler. |
517 | * @irq: irq |
518 | * @arg: soft struct for device |
519 | * @ep: regs |
520 | * |
521 | */ |
522 | static irqreturn_t |
523 | mbcs_completion_intr_handler(int irq, void *arg, struct pt_regs *ep) |
524 | { |
525 | struct mbcs_soft *soft = (struct mbcs_soft *)arg; |
526 | void *mmr_base; |
527 | union cm_status cm_status; |
528 | union cm_control cm_control; |
529 | |
530 | mmr_base = soft->mmr_base; |
531 | cm_status.cm_status_reg = MBCS_MMR_GET(mmr_base, MBCS_CM_STATUS); |
532 | |
533 | if (cm_status.rd_dma_done) { |
534 | /* stop dma-read engine, clear status */ |
535 | cm_control.cm_control_reg = |
536 | MBCS_MMR_GET(mmr_base, MBCS_CM_CONTROL); |
537 | cm_control.rd_dma_clr = 1; |
538 | MBCS_MMR_SET(mmr_base, MBCS_CM_CONTROL, |
539 | cm_control.cm_control_reg); |
540 | atomic_set(&soft->dmaread_done, 1); |
541 | wake_up(&soft->dmaread_queue); |
542 | } |
543 | if (cm_status.wr_dma_done) { |
544 | /* stop dma-write engine, clear status */ |
545 | cm_control.cm_control_reg = |
546 | MBCS_MMR_GET(mmr_base, MBCS_CM_CONTROL); |
547 | cm_control.wr_dma_clr = 1; |
548 | MBCS_MMR_SET(mmr_base, MBCS_CM_CONTROL, |
549 | cm_control.cm_control_reg); |
550 | atomic_set(&soft->dmawrite_done, 1); |
551 | wake_up(&soft->dmawrite_queue); |
552 | } |
553 | if (cm_status.alg_done) { |
554 | /* clear status */ |
555 | cm_control.cm_control_reg = |
556 | MBCS_MMR_GET(mmr_base, MBCS_CM_CONTROL); |
557 | cm_control.alg_done_clr = 1; |
558 | MBCS_MMR_SET(mmr_base, MBCS_CM_CONTROL, |
559 | cm_control.cm_control_reg); |
560 | atomic_set(&soft->algo_done, 1); |
561 | wake_up(&soft->algo_queue); |
562 | } |
563 | |
564 | return IRQ_HANDLED; |
565 | } |
566 | |
567 | /** |
568 | * mbcs_intr_alloc - Allocate interrupts. |
569 | * @dev: device pointer |
570 | * |
571 | */ |
572 | static int mbcs_intr_alloc(struct cx_dev *dev) |
573 | { |
574 | struct sn_irq_info *sn_irq; |
575 | struct mbcs_soft *soft; |
576 | struct getdma *getdma; |
577 | struct putdma *putdma; |
578 | struct algoblock *algo; |
579 | |
580 | soft = dev->soft; |
581 | getdma = &soft->getdma; |
582 | putdma = &soft->putdma; |
583 | algo = &soft->algo; |
584 | |
585 | soft->get_sn_irq = NULL; |
586 | soft->put_sn_irq = NULL; |
587 | soft->algo_sn_irq = NULL; |
588 | |
589 | sn_irq = tiocx_irq_alloc(dev->cx_id.nasid, TIOCX_CORELET, -1, -1, -1); |
590 | if (sn_irq == NULL) |
591 | return -EAGAIN; |
592 | soft->get_sn_irq = sn_irq; |
593 | getdma->intrHostDest = sn_irq->irq_xtalkaddr; |
594 | getdma->intrVector = sn_irq->irq_irq; |
595 | if (request_irq(sn_irq->irq_irq, |
596 | (void *)mbcs_completion_intr_handler, SA_SHIRQ, |
597 | "MBCS get intr", (void *)soft)) { |
598 | tiocx_irq_free(soft->get_sn_irq); |
599 | return -EAGAIN; |
600 | } |
601 | |
602 | sn_irq = tiocx_irq_alloc(dev->cx_id.nasid, TIOCX_CORELET, -1, -1, -1); |
603 | if (sn_irq == NULL) { |
604 | free_irq(soft->get_sn_irq->irq_irq, soft); |
605 | tiocx_irq_free(soft->get_sn_irq); |
606 | return -EAGAIN; |
607 | } |
608 | soft->put_sn_irq = sn_irq; |
609 | putdma->intrHostDest = sn_irq->irq_xtalkaddr; |
610 | putdma->intrVector = sn_irq->irq_irq; |
611 | if (request_irq(sn_irq->irq_irq, |
612 | (void *)mbcs_completion_intr_handler, SA_SHIRQ, |
613 | "MBCS put intr", (void *)soft)) { |
614 | tiocx_irq_free(soft->put_sn_irq); |
615 | free_irq(soft->get_sn_irq->irq_irq, soft); |
616 | tiocx_irq_free(soft->get_sn_irq); |
617 | return -EAGAIN; |
618 | } |
619 | |
620 | sn_irq = tiocx_irq_alloc(dev->cx_id.nasid, TIOCX_CORELET, -1, -1, -1); |
621 | if (sn_irq == NULL) { |
622 | free_irq(soft->put_sn_irq->irq_irq, soft); |
623 | tiocx_irq_free(soft->put_sn_irq); |
624 | free_irq(soft->get_sn_irq->irq_irq, soft); |
625 | tiocx_irq_free(soft->get_sn_irq); |
626 | return -EAGAIN; |
627 | } |
628 | soft->algo_sn_irq = sn_irq; |
629 | algo->intrHostDest = sn_irq->irq_xtalkaddr; |
630 | algo->intrVector = sn_irq->irq_irq; |
631 | if (request_irq(sn_irq->irq_irq, |
632 | (void *)mbcs_completion_intr_handler, SA_SHIRQ, |
633 | "MBCS algo intr", (void *)soft)) { |
634 | tiocx_irq_free(soft->algo_sn_irq); |
635 | free_irq(soft->put_sn_irq->irq_irq, soft); |
636 | tiocx_irq_free(soft->put_sn_irq); |
637 | free_irq(soft->get_sn_irq->irq_irq, soft); |
638 | tiocx_irq_free(soft->get_sn_irq); |
639 | return -EAGAIN; |
640 | } |
641 | |
642 | return 0; |
643 | } |
644 | |
645 | /** |
646 | * mbcs_intr_dealloc - Remove interrupts. |
647 | * @dev: device pointer |
648 | * |
649 | */ |
650 | static void mbcs_intr_dealloc(struct cx_dev *dev) |
651 | { |
652 | struct mbcs_soft *soft; |
653 | |
654 | soft = dev->soft; |
655 | |
656 | free_irq(soft->get_sn_irq->irq_irq, soft); |
657 | tiocx_irq_free(soft->get_sn_irq); |
658 | free_irq(soft->put_sn_irq->irq_irq, soft); |
659 | tiocx_irq_free(soft->put_sn_irq); |
660 | free_irq(soft->algo_sn_irq->irq_irq, soft); |
661 | tiocx_irq_free(soft->algo_sn_irq); |
662 | } |
663 | |
664 | static inline int mbcs_hw_init(struct mbcs_soft *soft) |
665 | { |
666 | void *mmr_base = soft->mmr_base; |
667 | union cm_control cm_control; |
668 | union cm_req_timeout cm_req_timeout; |
669 | uint64_t err_stat; |
670 | |
671 | cm_req_timeout.cm_req_timeout_reg = |
672 | MBCS_MMR_GET(mmr_base, MBCS_CM_REQ_TOUT); |
673 | |
674 | cm_req_timeout.time_out = MBCS_CM_CONTROL_REQ_TOUT_MASK; |
675 | MBCS_MMR_SET(mmr_base, MBCS_CM_REQ_TOUT, |
676 | cm_req_timeout.cm_req_timeout_reg); |
677 | |
678 | mbcs_gscr_pioaddr_set(soft); |
679 | mbcs_debug_pioaddr_set(soft); |
680 | |
681 | /* clear errors */ |
682 | err_stat = MBCS_MMR_GET(mmr_base, MBCS_CM_ERR_STAT); |
683 | MBCS_MMR_SET(mmr_base, MBCS_CM_CLR_ERR_STAT, err_stat); |
684 | MBCS_MMR_ZERO(mmr_base, MBCS_CM_ERROR_DETAIL1); |
685 | |
686 | /* enable interrupts */ |
687 | /* turn off 2^23 (INT_EN_PIO_REQ_ADDR_INV) */ |
688 | MBCS_MMR_SET(mmr_base, MBCS_CM_ERR_INT_EN, 0x3ffffff7e00ffUL); |
689 | |
690 | /* arm status regs and clear engines */ |
691 | cm_control.cm_control_reg = MBCS_MMR_GET(mmr_base, MBCS_CM_CONTROL); |
692 | cm_control.rearm_stat_regs = 1; |
693 | cm_control.alg_clr = 1; |
694 | cm_control.wr_dma_clr = 1; |
695 | cm_control.rd_dma_clr = 1; |
696 | |
697 | MBCS_MMR_SET(mmr_base, MBCS_CM_CONTROL, cm_control.cm_control_reg); |
698 | |
699 | return 0; |
700 | } |
701 | |
702 | static ssize_t show_algo(struct device *dev, char *buf) |
703 | { |
704 | struct cx_dev *cx_dev = to_cx_dev(dev); |
705 | struct mbcs_soft *soft = cx_dev->soft; |
706 | uint64_t debug0; |
707 | |
708 | /* |
709 | * By convention, the first debug register contains the |
710 | * algorithm number and revision. |
711 | */ |
712 | debug0 = *(uint64_t *) soft->debug_addr; |
713 | |
714 | return sprintf(buf, "0x%lx 0x%lx\n", |
715 | (debug0 >> 32), (debug0 & 0xffffffff)); |
716 | } |
717 | |
718 | static ssize_t store_algo(struct device *dev, const char *buf, size_t count) |
719 | { |
720 | int n; |
721 | struct cx_dev *cx_dev = to_cx_dev(dev); |
722 | struct mbcs_soft *soft = cx_dev->soft; |
723 | |
724 | if (count <= 0) |
725 | return 0; |
726 | |
727 | n = simple_strtoul(buf, NULL, 0); |
728 | |
729 | if (n == 1) { |
730 | mbcs_algo_start(soft); |
731 | if (wait_event_interruptible(soft->algo_queue, |
732 | atomic_read(&soft->algo_done))) |
733 | return -ERESTARTSYS; |
734 | } |
735 | |
736 | return count; |
737 | } |
738 | |
739 | DEVICE_ATTR(algo, 0644, show_algo, store_algo); |
740 | |
741 | /** |
742 | * mbcs_probe - Initialize for device |
743 | * @dev: device pointer |
744 | * @device_id: id table pointer |
745 | * |
746 | */ |
747 | static int mbcs_probe(struct cx_dev *dev, const struct cx_device_id *id) |
748 | { |
749 | struct mbcs_soft *soft; |
750 | |
751 | dev->soft = NULL; |
752 | |
753 | soft = kcalloc(1, sizeof(struct mbcs_soft), GFP_KERNEL); |
754 | if (soft == NULL) |
755 | return -ENOMEM; |
756 | |
757 | soft->nasid = dev->cx_id.nasid; |
758 | list_add(&soft->list, &soft_list); |
759 | soft->mmr_base = (void *)tiocx_swin_base(dev->cx_id.nasid); |
760 | dev->soft = soft; |
761 | soft->cxdev = dev; |
762 | |
763 | init_waitqueue_head(&soft->dmawrite_queue); |
764 | init_waitqueue_head(&soft->dmaread_queue); |
765 | init_waitqueue_head(&soft->algo_queue); |
766 | |
767 | init_MUTEX(&soft->dmawritelock); |
768 | init_MUTEX(&soft->dmareadlock); |
769 | init_MUTEX(&soft->algolock); |
770 | |
771 | mbcs_getdma_init(&soft->getdma); |
772 | mbcs_putdma_init(&soft->putdma); |
773 | mbcs_algo_init(&soft->algo); |
774 | |
775 | mbcs_hw_init(soft); |
776 | |
777 | /* Allocate interrupts */ |
778 | mbcs_intr_alloc(dev); |
779 | |
780 | device_create_file(&dev->dev, &dev_attr_algo); |
781 | |
782 | return 0; |
783 | } |
784 | |
785 | static int mbcs_remove(struct cx_dev *dev) |
786 | { |
787 | if (dev->soft) { |
788 | mbcs_intr_dealloc(dev); |
789 | kfree(dev->soft); |
790 | } |
791 | |
792 | device_remove_file(&dev->dev, &dev_attr_algo); |
793 | |
794 | return 0; |
795 | } |
796 | |
797 | const struct cx_device_id __devinitdata mbcs_id_table[] = { |
798 | { |
799 | .part_num = MBCS_PART_NUM, |
800 | .mfg_num = MBCS_MFG_NUM, |
801 | }, |
802 | { |
803 | .part_num = MBCS_PART_NUM_ALG0, |
804 | .mfg_num = MBCS_MFG_NUM, |
805 | }, |
806 | {0, 0} |
807 | }; |
808 | |
809 | MODULE_DEVICE_TABLE(cx, mbcs_id_table); |
810 | |
811 | struct cx_drv mbcs_driver = { |
812 | .name = DEVICE_NAME, |
813 | .id_table = mbcs_id_table, |
814 | .probe = mbcs_probe, |
815 | .remove = mbcs_remove, |
816 | }; |
817 | |
818 | static void __exit mbcs_exit(void) |
819 | { |
820 | int rv; |
821 | |
822 | rv = unregister_chrdev(mbcs_major, DEVICE_NAME); |
823 | if (rv < 0) |
824 | DBG(KERN_ALERT "Error in unregister_chrdev: %d\n", rv); |
825 | |
826 | cx_driver_unregister(&mbcs_driver); |
827 | } |
828 | |
829 | static int __init mbcs_init(void) |
830 | { |
831 | int rv; |
832 | |
833 | // Put driver into chrdevs[]. Get major number. |
834 | rv = register_chrdev(mbcs_major, DEVICE_NAME, &mbcs_ops); |
835 | if (rv < 0) { |
836 | DBG(KERN_ALERT "mbcs_init: can't get major number. %d\n", rv); |
837 | return rv; |
838 | } |
839 | mbcs_major = rv; |
840 | |
841 | return cx_driver_register(&mbcs_driver); |
842 | } |
843 | |
844 | module_init(mbcs_init); |
845 | module_exit(mbcs_exit); |
846 | |
847 | MODULE_AUTHOR("Bruce Losure <blosure@sgi.com>"); |
848 | MODULE_DESCRIPTION("Driver for MOATB Core Services"); |
849 | MODULE_LICENSE("GPL"); |