Contents of /alx-src/tags/kernel26-2.6.12-alx-r9/include/asm-alpha/core_mcpcia.h
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Wed Mar 4 11:03:09 2009 UTC (15 years, 3 months ago) by niro
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Wed Mar 4 11:03:09 2009 UTC (15 years, 3 months ago) by niro
File MIME type: text/plain
File size: 11663 byte(s)
Tag kernel26-2.6.12-alx-r9
1 | #ifndef __ALPHA_MCPCIA__H__ |
2 | #define __ALPHA_MCPCIA__H__ |
3 | |
4 | /* Define to experiment with fitting everything into one 128MB HAE window. |
5 | One window per bus, that is. */ |
6 | #define MCPCIA_ONE_HAE_WINDOW 1 |
7 | |
8 | #include <linux/types.h> |
9 | #include <linux/pci.h> |
10 | #include <asm/compiler.h> |
11 | |
12 | /* |
13 | * MCPCIA is the internal name for a core logic chipset which provides |
14 | * PCI access for the RAWHIDE family of systems. |
15 | * |
16 | * This file is based on: |
17 | * |
18 | * RAWHIDE System Programmer's Manual |
19 | * 16-May-96 |
20 | * Rev. 1.4 |
21 | * |
22 | */ |
23 | |
24 | /*------------------------------------------------------------------------** |
25 | ** ** |
26 | ** I/O procedures ** |
27 | ** ** |
28 | ** inport[b|w|t|l], outport[b|w|t|l] 8:16:24:32 IO xfers ** |
29 | ** inportbxt: 8 bits only ** |
30 | ** inport: alias of inportw ** |
31 | ** outport: alias of outportw ** |
32 | ** ** |
33 | ** inmem[b|w|t|l], outmem[b|w|t|l] 8:16:24:32 ISA memory xfers ** |
34 | ** inmembxt: 8 bits only ** |
35 | ** inmem: alias of inmemw ** |
36 | ** outmem: alias of outmemw ** |
37 | ** ** |
38 | **------------------------------------------------------------------------*/ |
39 | |
40 | |
41 | /* MCPCIA ADDRESS BIT DEFINITIONS |
42 | * |
43 | * 3333 3333 3322 2222 2222 1111 1111 11 |
44 | * 9876 5432 1098 7654 3210 9876 5432 1098 7654 3210 |
45 | * ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- |
46 | * 1 000 |
47 | * ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- |
48 | * | |\| |
49 | * | Byte Enable --+ | |
50 | * | Transfer Length --+ |
51 | * +-- IO space, not cached |
52 | * |
53 | * Byte Transfer |
54 | * Enable Length Transfer Byte Address |
55 | * adr<6:5> adr<4:3> Length Enable Adder |
56 | * --------------------------------------------- |
57 | * 00 00 Byte 1110 0x000 |
58 | * 01 00 Byte 1101 0x020 |
59 | * 10 00 Byte 1011 0x040 |
60 | * 11 00 Byte 0111 0x060 |
61 | * |
62 | * 00 01 Word 1100 0x008 |
63 | * 01 01 Word 1001 0x028 <= Not supported in this code. |
64 | * 10 01 Word 0011 0x048 |
65 | * |
66 | * 00 10 Tribyte 1000 0x010 |
67 | * 01 10 Tribyte 0001 0x030 |
68 | * |
69 | * 10 11 Longword 0000 0x058 |
70 | * |
71 | * Note that byte enables are asserted low. |
72 | * |
73 | */ |
74 | |
75 | #define MCPCIA_MID(m) ((unsigned long)(m) << 33) |
76 | |
77 | /* Dodge has PCI0 and PCI1 at MID 4 and 5 respectively. |
78 | Durango adds PCI2 and PCI3 at MID 6 and 7 respectively. */ |
79 | #define MCPCIA_HOSE2MID(h) ((h) + 4) |
80 | |
81 | #define MCPCIA_MEM_MASK 0x07ffffff /* SPARSE Mem region mask is 27 bits */ |
82 | |
83 | /* |
84 | * Memory spaces: |
85 | */ |
86 | #define MCPCIA_SPARSE(m) (IDENT_ADDR + 0xf000000000UL + MCPCIA_MID(m)) |
87 | #define MCPCIA_DENSE(m) (IDENT_ADDR + 0xf100000000UL + MCPCIA_MID(m)) |
88 | #define MCPCIA_IO(m) (IDENT_ADDR + 0xf180000000UL + MCPCIA_MID(m)) |
89 | #define MCPCIA_CONF(m) (IDENT_ADDR + 0xf1c0000000UL + MCPCIA_MID(m)) |
90 | #define MCPCIA_CSR(m) (IDENT_ADDR + 0xf1e0000000UL + MCPCIA_MID(m)) |
91 | #define MCPCIA_IO_IACK(m) (IDENT_ADDR + 0xf1f0000000UL + MCPCIA_MID(m)) |
92 | #define MCPCIA_DENSE_IO(m) (IDENT_ADDR + 0xe1fc000000UL + MCPCIA_MID(m)) |
93 | #define MCPCIA_DENSE_CONF(m) (IDENT_ADDR + 0xe1fe000000UL + MCPCIA_MID(m)) |
94 | |
95 | /* |
96 | * General Registers |
97 | */ |
98 | #define MCPCIA_REV(m) (MCPCIA_CSR(m) + 0x000) |
99 | #define MCPCIA_WHOAMI(m) (MCPCIA_CSR(m) + 0x040) |
100 | #define MCPCIA_PCI_LAT(m) (MCPCIA_CSR(m) + 0x080) |
101 | #define MCPCIA_CAP_CTRL(m) (MCPCIA_CSR(m) + 0x100) |
102 | #define MCPCIA_HAE_MEM(m) (MCPCIA_CSR(m) + 0x400) |
103 | #define MCPCIA_HAE_IO(m) (MCPCIA_CSR(m) + 0x440) |
104 | #define _MCPCIA_IACK_SC(m) (MCPCIA_CSR(m) + 0x480) |
105 | #define MCPCIA_HAE_DENSE(m) (MCPCIA_CSR(m) + 0x4C0) |
106 | |
107 | /* |
108 | * Interrupt Control registers |
109 | */ |
110 | #define MCPCIA_INT_CTL(m) (MCPCIA_CSR(m) + 0x500) |
111 | #define MCPCIA_INT_REQ(m) (MCPCIA_CSR(m) + 0x540) |
112 | #define MCPCIA_INT_TARG(m) (MCPCIA_CSR(m) + 0x580) |
113 | #define MCPCIA_INT_ADR(m) (MCPCIA_CSR(m) + 0x5C0) |
114 | #define MCPCIA_INT_ADR_EXT(m) (MCPCIA_CSR(m) + 0x600) |
115 | #define MCPCIA_INT_MASK0(m) (MCPCIA_CSR(m) + 0x640) |
116 | #define MCPCIA_INT_MASK1(m) (MCPCIA_CSR(m) + 0x680) |
117 | #define MCPCIA_INT_ACK0(m) (MCPCIA_CSR(m) + 0x10003f00) |
118 | #define MCPCIA_INT_ACK1(m) (MCPCIA_CSR(m) + 0x10003f40) |
119 | |
120 | /* |
121 | * Performance Monitor registers |
122 | */ |
123 | #define MCPCIA_PERF_MON(m) (MCPCIA_CSR(m) + 0x300) |
124 | #define MCPCIA_PERF_CONT(m) (MCPCIA_CSR(m) + 0x340) |
125 | |
126 | /* |
127 | * Diagnostic Registers |
128 | */ |
129 | #define MCPCIA_CAP_DIAG(m) (MCPCIA_CSR(m) + 0x700) |
130 | #define MCPCIA_TOP_OF_MEM(m) (MCPCIA_CSR(m) + 0x7C0) |
131 | |
132 | /* |
133 | * Error registers |
134 | */ |
135 | #define MCPCIA_MC_ERR0(m) (MCPCIA_CSR(m) + 0x800) |
136 | #define MCPCIA_MC_ERR1(m) (MCPCIA_CSR(m) + 0x840) |
137 | #define MCPCIA_CAP_ERR(m) (MCPCIA_CSR(m) + 0x880) |
138 | #define MCPCIA_PCI_ERR1(m) (MCPCIA_CSR(m) + 0x1040) |
139 | #define MCPCIA_MDPA_STAT(m) (MCPCIA_CSR(m) + 0x4000) |
140 | #define MCPCIA_MDPA_SYN(m) (MCPCIA_CSR(m) + 0x4040) |
141 | #define MCPCIA_MDPA_DIAG(m) (MCPCIA_CSR(m) + 0x4080) |
142 | #define MCPCIA_MDPB_STAT(m) (MCPCIA_CSR(m) + 0x8000) |
143 | #define MCPCIA_MDPB_SYN(m) (MCPCIA_CSR(m) + 0x8040) |
144 | #define MCPCIA_MDPB_DIAG(m) (MCPCIA_CSR(m) + 0x8080) |
145 | |
146 | /* |
147 | * PCI Address Translation Registers. |
148 | */ |
149 | #define MCPCIA_SG_TBIA(m) (MCPCIA_CSR(m) + 0x1300) |
150 | #define MCPCIA_HBASE(m) (MCPCIA_CSR(m) + 0x1340) |
151 | |
152 | #define MCPCIA_W0_BASE(m) (MCPCIA_CSR(m) + 0x1400) |
153 | #define MCPCIA_W0_MASK(m) (MCPCIA_CSR(m) + 0x1440) |
154 | #define MCPCIA_T0_BASE(m) (MCPCIA_CSR(m) + 0x1480) |
155 | |
156 | #define MCPCIA_W1_BASE(m) (MCPCIA_CSR(m) + 0x1500) |
157 | #define MCPCIA_W1_MASK(m) (MCPCIA_CSR(m) + 0x1540) |
158 | #define MCPCIA_T1_BASE(m) (MCPCIA_CSR(m) + 0x1580) |
159 | |
160 | #define MCPCIA_W2_BASE(m) (MCPCIA_CSR(m) + 0x1600) |
161 | #define MCPCIA_W2_MASK(m) (MCPCIA_CSR(m) + 0x1640) |
162 | #define MCPCIA_T2_BASE(m) (MCPCIA_CSR(m) + 0x1680) |
163 | |
164 | #define MCPCIA_W3_BASE(m) (MCPCIA_CSR(m) + 0x1700) |
165 | #define MCPCIA_W3_MASK(m) (MCPCIA_CSR(m) + 0x1740) |
166 | #define MCPCIA_T3_BASE(m) (MCPCIA_CSR(m) + 0x1780) |
167 | |
168 | /* Hack! Only words for bus 0. */ |
169 | |
170 | #ifndef MCPCIA_ONE_HAE_WINDOW |
171 | #define MCPCIA_HAE_ADDRESS MCPCIA_HAE_MEM(4) |
172 | #endif |
173 | #define MCPCIA_IACK_SC _MCPCIA_IACK_SC(4) |
174 | |
175 | /* |
176 | * The canonical non-remaped I/O and MEM addresses have these values |
177 | * subtracted out. This is arranged so that folks manipulating ISA |
178 | * devices can use their familiar numbers and have them map to bus 0. |
179 | */ |
180 | |
181 | #define MCPCIA_IO_BIAS MCPCIA_IO(4) |
182 | #define MCPCIA_MEM_BIAS MCPCIA_DENSE(4) |
183 | |
184 | /* Offset between ram physical addresses and pci64 DAC bus addresses. */ |
185 | #define MCPCIA_DAC_OFFSET (1UL << 40) |
186 | |
187 | /* |
188 | * Data structure for handling MCPCIA machine checks: |
189 | */ |
190 | struct el_MCPCIA_uncorrected_frame_mcheck { |
191 | struct el_common header; |
192 | struct el_common_EV5_uncorrectable_mcheck procdata; |
193 | }; |
194 | |
195 | |
196 | #ifdef __KERNEL__ |
197 | |
198 | #ifndef __EXTERN_INLINE |
199 | #define __EXTERN_INLINE extern inline |
200 | #define __IO_EXTERN_INLINE |
201 | #endif |
202 | |
203 | /* |
204 | * I/O functions: |
205 | * |
206 | * MCPCIA, the RAWHIDE family PCI/memory support chipset for the EV5 (21164) |
207 | * and EV56 (21164a) processors, can use either a sparse address mapping |
208 | * scheme, or the so-called byte-word PCI address space, to get at PCI memory |
209 | * and I/O. |
210 | * |
211 | * Unfortunately, we can't use BWIO with EV5, so for now, we always use SPARSE. |
212 | */ |
213 | |
214 | /* |
215 | * Memory functions. 64-bit and 32-bit accesses are done through |
216 | * dense memory space, everything else through sparse space. |
217 | * |
218 | * For reading and writing 8 and 16 bit quantities we need to |
219 | * go through one of the three sparse address mapping regions |
220 | * and use the HAE_MEM CSR to provide some bits of the address. |
221 | * The following few routines use only sparse address region 1 |
222 | * which gives 1Gbyte of accessible space which relates exactly |
223 | * to the amount of PCI memory mapping *into* system address space. |
224 | * See p 6-17 of the specification but it looks something like this: |
225 | * |
226 | * 21164 Address: |
227 | * |
228 | * 3 2 1 |
229 | * 9876543210987654321098765432109876543210 |
230 | * 1ZZZZ0.PCI.QW.Address............BBLL |
231 | * |
232 | * ZZ = SBZ |
233 | * BB = Byte offset |
234 | * LL = Transfer length |
235 | * |
236 | * PCI Address: |
237 | * |
238 | * 3 2 1 |
239 | * 10987654321098765432109876543210 |
240 | * HHH....PCI.QW.Address........ 00 |
241 | * |
242 | * HHH = 31:29 HAE_MEM CSR |
243 | * |
244 | */ |
245 | |
246 | #define vip volatile int __force * |
247 | #define vuip volatile unsigned int __force * |
248 | |
249 | #ifdef MCPCIA_ONE_HAE_WINDOW |
250 | #define MCPCIA_FROB_MMIO \ |
251 | if (__mcpcia_is_mmio(hose)) { \ |
252 | set_hae(hose & 0xffffffff); \ |
253 | hose = hose - MCPCIA_DENSE(4) + MCPCIA_SPARSE(4); \ |
254 | } |
255 | #else |
256 | #define MCPCIA_FROB_MMIO \ |
257 | if (__mcpcia_is_mmio(hose)) { \ |
258 | hose = hose - MCPCIA_DENSE(4) + MCPCIA_SPARSE(4); \ |
259 | } |
260 | #endif |
261 | |
262 | static inline int __mcpcia_is_mmio(unsigned long addr) |
263 | { |
264 | return (addr & 0x80000000UL) == 0; |
265 | } |
266 | |
267 | __EXTERN_INLINE unsigned int mcpcia_ioread8(void __iomem *xaddr) |
268 | { |
269 | unsigned long addr = (unsigned long)xaddr & MCPCIA_MEM_MASK; |
270 | unsigned long hose = (unsigned long)xaddr & ~MCPCIA_MEM_MASK; |
271 | unsigned long result; |
272 | |
273 | MCPCIA_FROB_MMIO; |
274 | |
275 | result = *(vip) ((addr << 5) + hose + 0x00); |
276 | return __kernel_extbl(result, addr & 3); |
277 | } |
278 | |
279 | __EXTERN_INLINE void mcpcia_iowrite8(u8 b, void __iomem *xaddr) |
280 | { |
281 | unsigned long addr = (unsigned long)xaddr & MCPCIA_MEM_MASK; |
282 | unsigned long hose = (unsigned long)xaddr & ~MCPCIA_MEM_MASK; |
283 | unsigned long w; |
284 | |
285 | MCPCIA_FROB_MMIO; |
286 | |
287 | w = __kernel_insbl(b, addr & 3); |
288 | *(vuip) ((addr << 5) + hose + 0x00) = w; |
289 | } |
290 | |
291 | __EXTERN_INLINE unsigned int mcpcia_ioread16(void __iomem *xaddr) |
292 | { |
293 | unsigned long addr = (unsigned long)xaddr & MCPCIA_MEM_MASK; |
294 | unsigned long hose = (unsigned long)xaddr & ~MCPCIA_MEM_MASK; |
295 | unsigned long result; |
296 | |
297 | MCPCIA_FROB_MMIO; |
298 | |
299 | result = *(vip) ((addr << 5) + hose + 0x08); |
300 | return __kernel_extwl(result, addr & 3); |
301 | } |
302 | |
303 | __EXTERN_INLINE void mcpcia_iowrite16(u16 b, void __iomem *xaddr) |
304 | { |
305 | unsigned long addr = (unsigned long)xaddr & MCPCIA_MEM_MASK; |
306 | unsigned long hose = (unsigned long)xaddr & ~MCPCIA_MEM_MASK; |
307 | unsigned long w; |
308 | |
309 | MCPCIA_FROB_MMIO; |
310 | |
311 | w = __kernel_inswl(b, addr & 3); |
312 | *(vuip) ((addr << 5) + hose + 0x08) = w; |
313 | } |
314 | |
315 | __EXTERN_INLINE unsigned int mcpcia_ioread32(void __iomem *xaddr) |
316 | { |
317 | unsigned long addr = (unsigned long)xaddr; |
318 | |
319 | if (!__mcpcia_is_mmio(addr)) |
320 | addr = ((addr & 0xffff) << 5) + (addr & ~0xfffful) + 0x18; |
321 | |
322 | return *(vuip)addr; |
323 | } |
324 | |
325 | __EXTERN_INLINE void mcpcia_iowrite32(u32 b, void __iomem *xaddr) |
326 | { |
327 | unsigned long addr = (unsigned long)xaddr; |
328 | |
329 | if (!__mcpcia_is_mmio(addr)) |
330 | addr = ((addr & 0xffff) << 5) + (addr & ~0xfffful) + 0x18; |
331 | |
332 | *(vuip)addr = b; |
333 | } |
334 | |
335 | |
336 | __EXTERN_INLINE void __iomem *mcpcia_ioportmap(unsigned long addr) |
337 | { |
338 | return (void __iomem *)(addr + MCPCIA_IO_BIAS); |
339 | } |
340 | |
341 | __EXTERN_INLINE void __iomem *mcpcia_ioremap(unsigned long addr, |
342 | unsigned long size) |
343 | { |
344 | return (void __iomem *)(addr + MCPCIA_MEM_BIAS); |
345 | } |
346 | |
347 | __EXTERN_INLINE int mcpcia_is_ioaddr(unsigned long addr) |
348 | { |
349 | return addr >= MCPCIA_SPARSE(0); |
350 | } |
351 | |
352 | __EXTERN_INLINE int mcpcia_is_mmio(const volatile void __iomem *xaddr) |
353 | { |
354 | unsigned long addr = (unsigned long) xaddr; |
355 | return __mcpcia_is_mmio(addr); |
356 | } |
357 | |
358 | #undef MCPCIA_FROB_MMIO |
359 | |
360 | #undef vip |
361 | #undef vuip |
362 | |
363 | #undef __IO_PREFIX |
364 | #define __IO_PREFIX mcpcia |
365 | #define mcpcia_trivial_rw_bw 2 |
366 | #define mcpcia_trivial_rw_lq 1 |
367 | #define mcpcia_trivial_io_bw 0 |
368 | #define mcpcia_trivial_io_lq 0 |
369 | #define mcpcia_trivial_iounmap 1 |
370 | #include <asm/io_trivial.h> |
371 | |
372 | #ifdef __IO_EXTERN_INLINE |
373 | #undef __EXTERN_INLINE |
374 | #undef __IO_EXTERN_INLINE |
375 | #endif |
376 | |
377 | #endif /* __KERNEL__ */ |
378 | |
379 | #endif /* __ALPHA_MCPCIA__H__ */ |