linux-libc-headers/patches/linux-2.6.18.1-mips_headers-1.patch

diff -Naur linux-2.6.18.1/include/asm-mips/cacheflush.h linux-mips-2.6.18.1/include/asm-mips/cacheflush.h
--- linux-2.6.18.1/include/asm-mips/cacheflush.h	2006-10-13 20:34:03.000000000 -0700
+++ linux-mips-2.6.18.1/include/asm-mips/cacheflush.h	2006-10-17 06:23:28.000000000 -0700
@@ -21,7 +21,6 @@
  *  - flush_cache_range(vma, start, end) flushes a range of pages
  *  - flush_icache_range(start, end) flush a range of instructions
  *  - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache
- *  - flush_icache_page(vma, pg) flushes(invalidates) a page for icache
  *
  * MIPS specific flush operations:
  *
@@ -39,7 +38,7 @@
 
 static inline void flush_dcache_page(struct page *page)
 {
-	if (cpu_has_dc_aliases)
+	if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc)
 		__flush_dcache_page(page);
 
 }
@@ -47,30 +46,24 @@
 #define flush_dcache_mmap_lock(mapping)		do { } while (0)
 #define flush_dcache_mmap_unlock(mapping)	do { } while (0)
 
-extern void (*flush_icache_page)(struct vm_area_struct *vma,
+extern void (*__flush_icache_page)(struct vm_area_struct *vma,
 	struct page *page);
+static inline void flush_icache_page(struct vm_area_struct *vma,
+	struct page *page)
+{
+}
+
 extern void (*flush_icache_range)(unsigned long start, unsigned long end);
 #define flush_cache_vmap(start, end)		flush_cache_all()
 #define flush_cache_vunmap(start, end)		flush_cache_all()
 
-static inline void copy_to_user_page(struct vm_area_struct *vma,
+extern void copy_to_user_page(struct vm_area_struct *vma,
 	struct page *page, unsigned long vaddr, void *dst, const void *src,
-	unsigned long len)
-{
-	if (cpu_has_dc_aliases)
-		flush_cache_page(vma, vaddr, page_to_pfn(page));
-	memcpy(dst, src, len);
-	flush_icache_page(vma, page);
-}
+	unsigned long len);
 
-static inline void copy_from_user_page(struct vm_area_struct *vma,
+extern void copy_from_user_page(struct vm_area_struct *vma,
 	struct page *page, unsigned long vaddr, void *dst, const void *src,
-	unsigned long len)
-{
-	if (cpu_has_dc_aliases)
-		flush_cache_page(vma, vaddr, page_to_pfn(page));
-	memcpy(dst, src, len);
-}
+	unsigned long len);
 
 extern void (*flush_cache_sigtramp)(unsigned long addr);
 extern void (*flush_icache_all)(void);
diff -Naur linux-2.6.18.1/include/asm-mips/fixmap.h linux-mips-2.6.18.1/include/asm-mips/fixmap.h
--- linux-2.6.18.1/include/asm-mips/fixmap.h	2006-10-13 20:34:03.000000000 -0700
+++ linux-mips-2.6.18.1/include/asm-mips/fixmap.h	2006-10-17 06:23:28.000000000 -0700
@@ -45,8 +45,16 @@
  * fix-mapped?
  */
 enum fixed_addresses {
+#define FIX_N_COLOURS 8
+	FIX_CMAP_BEGIN,
+#ifdef CONFIG_MIPS_MT_SMTC
+	FIX_CMAP_END = FIX_CMAP_BEGIN + (FIX_N_COLOURS * NR_CPUS),
+#else
+	FIX_CMAP_END = FIX_CMAP_BEGIN + FIX_N_COLOURS,
+#endif
 #ifdef CONFIG_HIGHMEM
-	FIX_KMAP_BEGIN,	/* reserved pte's for temporary kernel mappings */
+	/* reserved pte's for temporary kernel mappings */
+	FIX_KMAP_BEGIN = FIX_CMAP_END + 1,
 	FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1,
 #endif
 	__end_of_fixed_addresses
@@ -70,9 +78,9 @@
  * at the top of mem..
  */
 #if defined(CONFIG_CPU_TX39XX) || defined(CONFIG_CPU_TX49XX)
-#define FIXADDR_TOP	(0xff000000UL - 0x2000)
+#define FIXADDR_TOP	((unsigned long)(long)(int)(0xff000000 - 0x20000))
 #else
-#define FIXADDR_TOP	(0xffffe000UL)
+#define FIXADDR_TOP	((unsigned long)(long)(int)0xfffe0000)
 #endif
 #define FIXADDR_SIZE	(__end_of_fixed_addresses << PAGE_SHIFT)
 #define FIXADDR_START	(FIXADDR_TOP - FIXADDR_SIZE)
diff -Naur linux-2.6.18.1/include/asm-mips/fpu.h linux-mips-2.6.18.1/include/asm-mips/fpu.h
--- linux-2.6.18.1/include/asm-mips/fpu.h	2006-10-13 20:34:03.000000000 -0700
+++ linux-mips-2.6.18.1/include/asm-mips/fpu.h	2006-10-17 06:23:28.000000000 -0700
@@ -134,9 +134,11 @@
 
 static inline fpureg_t *get_fpu_regs(struct task_struct *tsk)
 {
-	if (cpu_has_fpu) {
-		if ((tsk == current) && __is_fpu_owner())
+	if (tsk == current) {
+		preempt_disable();
+		if (is_fpu_owner())
 			_save_fp(current);
+		preempt_enable();
 	}
 
 	return tsk->thread.fpu.fpr;
diff -Naur linux-2.6.18.1/include/asm-mips/irq.h linux-mips-2.6.18.1/include/asm-mips/irq.h
--- linux-2.6.18.1/include/asm-mips/irq.h	2006-10-13 20:34:03.000000000 -0700
+++ linux-mips-2.6.18.1/include/asm-mips/irq.h	2006-10-17 06:23:28.000000000 -0700
@@ -76,8 +76,4 @@
                           unsigned long hwmask);
 #endif /* CONFIG_MIPS_MT_SMTC */
 
-#ifdef CONFIG_SMP
-#define ARCH_HAS_IRQ_PER_CPU
-#endif
-
 #endif /* _ASM_IRQ_H */
diff -Naur linux-2.6.18.1/include/asm-mips/mach-atlas/mc146818rtc.h linux-mips-2.6.18.1/include/asm-mips/mach-atlas/mc146818rtc.h
--- linux-2.6.18.1/include/asm-mips/mach-atlas/mc146818rtc.h	2006-10-13 20:34:03.000000000 -0700
+++ linux-mips-2.6.18.1/include/asm-mips/mach-atlas/mc146818rtc.h	2006-10-17 06:23:28.000000000 -0700
@@ -28,10 +28,12 @@
 #include <asm/mips-boards/atlas.h>
 #include <asm/mips-boards/atlasint.h>
 
+#define ARCH_RTC_LOCATION
+
 #define RTC_PORT(x)	(ATLAS_RTC_ADR_REG + (x) * 8)
 #define RTC_IO_EXTENT	0x100
 #define RTC_IOMAPPED	0
-#define RTC_IRQ		ATLASINT_RTC
+#define RTC_IRQ		ATLAS_INT_RTC
 
 static inline unsigned char CMOS_READ(unsigned long addr)
 {
diff -Naur linux-2.6.18.1/include/asm-mips/mach-au1x00/au1xxx_ide.h linux-mips-2.6.18.1/include/asm-mips/mach-au1x00/au1xxx_ide.h
--- linux-2.6.18.1/include/asm-mips/mach-au1x00/au1xxx_ide.h	2006-10-13 20:34:03.000000000 -0700
+++ linux-mips-2.6.18.1/include/asm-mips/mach-au1x00/au1xxx_ide.h	2006-10-17 06:23:28.000000000 -0700
@@ -83,6 +83,7 @@
 } _auide_hwif;
 
 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
+
 /* HD white list */
 static const struct drive_list_entry dma_white_list [] = {
 /*
diff -Naur linux-2.6.18.1/include/asm-mips/mips-boards/atlasint.h linux-mips-2.6.18.1/include/asm-mips/mips-boards/atlasint.h
--- linux-2.6.18.1/include/asm-mips/mips-boards/atlasint.h	2006-10-13 20:34:03.000000000 -0700
+++ linux-mips-2.6.18.1/include/asm-mips/mips-boards/atlasint.h	2006-10-17 06:23:28.000000000 -0700
@@ -1,6 +1,7 @@
 /*
- * Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 1999 MIPS Technologies, Inc.  All rights reserved.
+ * Copyright (C) 1999, 2006  MIPS Technologies, Inc.  All rights reserved.
+ *	Authors: Carsten Langgaard <carstenl@mips.com>
+ *		 Maciej W. Rozycki <macro@mips.com>
  *
  * ########################################################################
  *
@@ -25,41 +26,88 @@
 #ifndef _MIPS_ATLASINT_H
 #define _MIPS_ATLASINT_H
 
-#define ATLASINT_BASE		1
-#define ATLASINT_UART		(ATLASINT_BASE+0)
-#define ATLASINT_TIM0		(ATLASINT_BASE+1)
-#define ATLASINT_RES2		(ATLASINT_BASE+2)
-#define ATLASINT_RES3		(ATLASINT_BASE+3)
-#define ATLASINT_RTC		(ATLASINT_BASE+4)
-#define ATLASINT_COREHI		(ATLASINT_BASE+5)
-#define ATLASINT_CORELO		(ATLASINT_BASE+6)
-#define ATLASINT_RES7		(ATLASINT_BASE+7)
-#define ATLASINT_PCIA		(ATLASINT_BASE+8)
-#define ATLASINT_PCIB		(ATLASINT_BASE+9)
-#define ATLASINT_PCIC		(ATLASINT_BASE+10)
-#define ATLASINT_PCID		(ATLASINT_BASE+11)
-#define ATLASINT_ENUM		(ATLASINT_BASE+12)
-#define ATLASINT_DEG		(ATLASINT_BASE+13)
-#define ATLASINT_ATXFAIL	(ATLASINT_BASE+14)
-#define ATLASINT_INTA		(ATLASINT_BASE+15)
-#define ATLASINT_INTB		(ATLASINT_BASE+16)
-#define ATLASINT_ETH		ATLASINT_INTB
-#define ATLASINT_INTC		(ATLASINT_BASE+17)
-#define ATLASINT_SCSI		ATLASINT_INTC
-#define ATLASINT_INTD		(ATLASINT_BASE+18)
-#define ATLASINT_SERR		(ATLASINT_BASE+19)
-#define ATLASINT_RES20		(ATLASINT_BASE+20)
-#define ATLASINT_RES21		(ATLASINT_BASE+21)
-#define ATLASINT_RES22		(ATLASINT_BASE+22)
-#define ATLASINT_RES23		(ATLASINT_BASE+23)
-#define ATLASINT_RES24		(ATLASINT_BASE+24)
-#define ATLASINT_RES25		(ATLASINT_BASE+25)
-#define ATLASINT_RES26		(ATLASINT_BASE+26)
-#define ATLASINT_RES27		(ATLASINT_BASE+27)
-#define ATLASINT_RES28		(ATLASINT_BASE+28)
-#define ATLASINT_RES29		(ATLASINT_BASE+29)
-#define ATLASINT_RES30		(ATLASINT_BASE+30)
-#define ATLASINT_RES31		(ATLASINT_BASE+31)
-#define ATLASINT_END		(ATLASINT_BASE+31)
+/*
+ * Interrupts 0..7 are used for Atlas CPU interrupts (nonEIC mode)
+ */
+#define MIPSCPU_INT_BASE	0
+
+/* CPU interrupt offsets */
+#define MIPSCPU_INT_SW0		0
+#define MIPSCPU_INT_SW1		1
+#define MIPSCPU_INT_MB0		2
+#define MIPSCPU_INT_ATLAS	MIPSCPU_INT_MB0
+#define MIPSCPU_INT_MB1		3
+#define MIPSCPU_INT_MB2		4
+#define MIPSCPU_INT_MB3		5
+#define MIPSCPU_INT_MB4		6
+#define MIPSCPU_INT_CPUCTR	7
+
+/*
+ * Interrupts 8..39 are used for Atlas interrupt controller interrupts
+ */
+#define ATLAS_INT_BASE		8
+#define ATLAS_INT_UART		(ATLAS_INT_BASE + 0)
+#define ATLAS_INT_TIM0		(ATLAS_INT_BASE + 1)
+#define ATLAS_INT_RES2		(ATLAS_INT_BASE + 2)
+#define ATLAS_INT_RES3		(ATLAS_INT_BASE + 3)
+#define ATLAS_INT_RTC		(ATLAS_INT_BASE + 4)
+#define ATLAS_INT_COREHI	(ATLAS_INT_BASE + 5)
+#define ATLAS_INT_CORELO	(ATLAS_INT_BASE + 6)
+#define ATLAS_INT_RES7		(ATLAS_INT_BASE + 7)
+#define ATLAS_INT_PCIA		(ATLAS_INT_BASE + 8)
+#define ATLAS_INT_PCIB		(ATLAS_INT_BASE + 9)
+#define ATLAS_INT_PCIC		(ATLAS_INT_BASE + 10)
+#define ATLAS_INT_PCID		(ATLAS_INT_BASE + 11)
+#define ATLAS_INT_ENUM		(ATLAS_INT_BASE + 12)
+#define ATLAS_INT_DEG		(ATLAS_INT_BASE + 13)
+#define ATLAS_INT_ATXFAIL	(ATLAS_INT_BASE + 14)
+#define ATLAS_INT_INTA		(ATLAS_INT_BASE + 15)
+#define ATLAS_INT_INTB		(ATLAS_INT_BASE + 16)
+#define ATLAS_INT_ETH		ATLAS_INT_INTB
+#define ATLAS_INT_INTC		(ATLAS_INT_BASE + 17)
+#define ATLAS_INT_SCSI		ATLAS_INT_INTC
+#define ATLAS_INT_INTD		(ATLAS_INT_BASE + 18)
+#define ATLAS_INT_SERR		(ATLAS_INT_BASE + 19)
+#define ATLAS_INT_RES20		(ATLAS_INT_BASE + 20)
+#define ATLAS_INT_RES21		(ATLAS_INT_BASE + 21)
+#define ATLAS_INT_RES22		(ATLAS_INT_BASE + 22)
+#define ATLAS_INT_RES23		(ATLAS_INT_BASE + 23)
+#define ATLAS_INT_RES24		(ATLAS_INT_BASE + 24)
+#define ATLAS_INT_RES25		(ATLAS_INT_BASE + 25)
+#define ATLAS_INT_RES26		(ATLAS_INT_BASE + 26)
+#define ATLAS_INT_RES27		(ATLAS_INT_BASE + 27)
+#define ATLAS_INT_RES28		(ATLAS_INT_BASE + 28)
+#define ATLAS_INT_RES29		(ATLAS_INT_BASE + 29)
+#define ATLAS_INT_RES30		(ATLAS_INT_BASE + 30)
+#define ATLAS_INT_RES31		(ATLAS_INT_BASE + 31)
+#define ATLAS_INT_END		(ATLAS_INT_BASE + 31)
+
+/*
+ * Interrupts 64..127 are used for Soc-it Classic interrupts
+ */
+#define MSC01C_INT_BASE		64
+
+/* SOC-it Classic interrupt offsets */
+#define MSC01C_INT_TMR		0
+#define MSC01C_INT_PCI		1
+
+/*
+ * Interrupts 64..127 are used for Soc-it EIC interrupts
+ */
+#define MSC01E_INT_BASE		64
+
+/* SOC-it EIC interrupt offsets */
+#define	MSC01E_INT_SW0		1
+#define	MSC01E_INT_SW1		2
+#define	MSC01E_INT_MB0		3
+#define	MSC01E_INT_ATLAS	MSC01E_INT_MB0
+#define	MSC01E_INT_MB1		4
+#define	MSC01E_INT_MB2		5
+#define	MSC01E_INT_MB3		6
+#define	MSC01E_INT_MB4		7
+#define	MSC01E_INT_TMR		8
+#define	MSC01E_INT_PCI		9
+#define	MSC01E_INT_PERFCTR	10
+#define	MSC01E_INT_CPUCTR	11
 
 #endif /* !(_MIPS_ATLASINT_H) */
diff -Naur linux-2.6.18.1/include/asm-mips/page.h linux-mips-2.6.18.1/include/asm-mips/page.h
--- linux-2.6.18.1/include/asm-mips/page.h	2006-10-13 20:34:03.000000000 -0700
+++ linux-mips-2.6.18.1/include/asm-mips/page.h	2006-10-17 06:23:28.000000000 -0700
@@ -53,19 +53,17 @@
 	extern void (*flush_data_cache_page)(unsigned long addr);
 
 	clear_page(addr);
-	if (pages_do_alias((unsigned long) addr, vaddr))
+	if (pages_do_alias((unsigned long) addr, vaddr & PAGE_MASK))
 		flush_data_cache_page((unsigned long)addr);
 }
 
-static inline void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
-	struct page *to)
-{
-	extern void (*flush_data_cache_page)(unsigned long addr);
+extern void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
+	struct page *to);
+struct vm_area_struct;
+extern void copy_user_highpage(struct page *to, struct page *from,
+	unsigned long vaddr, struct vm_area_struct *vma);
 
-	copy_page(vto, vfrom);
-	if (pages_do_alias((unsigned long)vto, vaddr))
-		flush_data_cache_page((unsigned long)vto);
-}
+#define __HAVE_ARCH_COPY_USER_HIGHPAGE
 
 /*
  * These are used to make use of C type-checking..
@@ -74,15 +72,17 @@
   #ifdef CONFIG_CPU_MIPS32
     typedef struct { unsigned long pte_low, pte_high; } pte_t;
     #define pte_val(x)    ((x).pte_low | ((unsigned long long)(x).pte_high << 32))
+    #define __pte(x)      ({ pte_t __pte = {(x), ((unsigned long long)(x)) >> 32}; __pte; })
   #else
      typedef struct { unsigned long long pte; } pte_t;
      #define pte_val(x)	((x).pte)
+     #define __pte(x)	((pte_t) { (x) } )
   #endif
 #else
 typedef struct { unsigned long pte; } pte_t;
 #define pte_val(x)	((x).pte)
-#endif
 #define __pte(x)	((pte_t) { (x) } )
+#endif
 
 /*
  * For 3-level pagetables we defines these ourselves, for 2-level the
diff -Naur linux-2.6.18.1/include/asm-mips/ptrace.h linux-mips-2.6.18.1/include/asm-mips/ptrace.h
--- linux-2.6.18.1/include/asm-mips/ptrace.h	2006-10-13 20:34:03.000000000 -0700
+++ linux-mips-2.6.18.1/include/asm-mips/ptrace.h	2006-10-17 06:23:28.000000000 -0700
@@ -10,8 +10,6 @@
 #define _ASM_PTRACE_H
 
 
-#include <asm/isadep.h>
-
 /* 0 - 31 are integer registers, 32 - 63 are fp registers.  */
 #define FPR_BASE	32
 #define PC		64
@@ -73,6 +71,7 @@
 #ifdef __KERNEL__
 
 #include <linux/linkage.h>
+#include <asm/isadep.h>
 
 /*
  * Does the process account for user or for system time?
diff -Naur linux-2.6.18.1/include/asm-mips/spinlock.h linux-mips-2.6.18.1/include/asm-mips/spinlock.h
--- linux-2.6.18.1/include/asm-mips/spinlock.h	2006-10-13 20:34:03.000000000 -0700
+++ linux-mips-2.6.18.1/include/asm-mips/spinlock.h	2006-10-17 06:23:28.000000000 -0700
@@ -239,7 +239,51 @@
 	: "memory");
 }
 
-#define __raw_read_trylock(lock) generic__raw_read_trylock(lock)
+static inline int __raw_read_trylock(raw_rwlock_t *rw)
+{
+	unsigned int tmp;
+	int ret;
+
+	if (R10000_LLSC_WAR) {
+		__asm__ __volatile__(
+		"	.set	noreorder	# __raw_read_trylock	\n"
+		"	li	%2, 0					\n"
+		"1:	ll	%1, %3					\n"
+		"	bnez	%1, 2f					\n"
+		"	 addu	%1, 1					\n"
+		"	sc	%1, %0					\n"
+		"	beqzl	%1, 1b					\n"
+		"	.set	reorder					\n"
+#ifdef CONFIG_SMP
+		"	 sync						\n"
+#endif
+		"	li	%2, 1					\n"
+		"2:							\n"
+		: "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
+		: "m" (rw->lock)
+		: "memory");
+	} else {
+		__asm__ __volatile__(
+		"	.set	noreorder	# __raw_read_trylock	\n"
+		"	li	%2, 0					\n"
+		"1:	ll	%1, %3					\n"
+		"	bnez	%1, 2f					\n"
+		"	 addu	%1, 1					\n"
+		"	sc	%1, %0					\n"
+		"	beqz	%1, 1b					\n"
+		"	.set	reorder					\n"
+#ifdef CONFIG_SMP
+		"	 sync						\n"
+#endif
+		"	li	%2, 1					\n"
+		"2:							\n"
+		: "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
+		: "m" (rw->lock)
+		: "memory");
+	}
+
+	return ret;
+}
 
 static inline int __raw_write_trylock(raw_rwlock_t *rw)
 {
@@ -283,4 +327,5 @@
 	return ret;
 }
 
+
 #endif /* _ASM_SPINLOCK_H */
diff -Naur linux-2.6.18.1/include/asm-mips/system.h linux-mips-2.6.18.1/include/asm-mips/system.h
--- linux-2.6.18.1/include/asm-mips/system.h	2006-10-13 20:34:03.000000000 -0700
+++ linux-mips-2.6.18.1/include/asm-mips/system.h	2006-10-17 06:23:28.000000000 -0700
@@ -392,7 +392,7 @@
 {
 	__u64 retval;
 
-	if (cpu_has_llsc) {
+	if (cpu_has_llsc && R10000_LLSC_WAR) {
 		__asm__ __volatile__(
 		"	.set	push					\n"
 		"	.set	noat					\n"
diff -Naur linux-2.6.18.1/include/asm-mips/timex.h linux-mips-2.6.18.1/include/asm-mips/timex.h
--- linux-2.6.18.1/include/asm-mips/timex.h	2006-10-13 20:34:03.000000000 -0700
+++ linux-mips-2.6.18.1/include/asm-mips/timex.h	2006-10-17 06:23:28.000000000 -0700
@@ -8,6 +8,8 @@
 #ifndef _ASM_TIMEX_H
 #define _ASM_TIMEX_H
 
+#ifdef __KERNEL__
+
 #include <asm/mipsregs.h>
 
 /*
@@ -51,4 +53,6 @@
 	return read_c0_count();
 }
 
+#endif /* __KERNEL__ */
+
 #endif /*  _ASM_TIMEX_H */
diff -Naur linux-2.6.18.1/include/asm-mips/unistd.h linux-mips-2.6.18.1/include/asm-mips/unistd.h
--- linux-2.6.18.1/include/asm-mips/unistd.h	2006-10-13 20:34:03.000000000 -0700
+++ linux-mips-2.6.18.1/include/asm-mips/unistd.h	2006-10-17 06:23:28.000000000 -0700
@@ -313,7 +313,7 @@
 #define __NR_mknodat			(__NR_Linux + 290)
 #define __NR_fchownat			(__NR_Linux + 291)
 #define __NR_futimesat			(__NR_Linux + 292)
-#define __NR_fstatat			(__NR_Linux + 293)
+#define __NR_fstatat64			(__NR_Linux + 293)
 #define __NR_unlinkat			(__NR_Linux + 294)
 #define __NR_renameat			(__NR_Linux + 295)
 #define __NR_linkat			(__NR_Linux + 296)
@@ -329,16 +329,18 @@
 #define __NR_tee			(__NR_Linux + 306)
 #define __NR_vmsplice			(__NR_Linux + 307)
 #define __NR_move_pages			(__NR_Linux + 308)
+#define __NR_set_robust_list		(__NR_Linux + 309)
+#define __NR_get_robust_list		(__NR_Linux + 310)
 
 /*
  * Offset of the last Linux o32 flavoured syscall
  */
-#define __NR_Linux_syscalls		308
+#define __NR_Linux_syscalls		310
 
 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
 
 #define __NR_O32_Linux			4000
-#define __NR_O32_Linux_syscalls		308
+#define __NR_O32_Linux_syscalls		310
 
 #if _MIPS_SIM == _MIPS_SIM_ABI64
 
@@ -598,7 +600,7 @@
 #define __NR_mknodat			(__NR_Linux + 249)
 #define __NR_fchownat			(__NR_Linux + 250)
 #define __NR_futimesat			(__NR_Linux + 251)
-#define __NR_fstatat			(__NR_Linux + 252)
+#define __NR_newfstatat			(__NR_Linux + 252)
 #define __NR_unlinkat			(__NR_Linux + 253)
 #define __NR_renameat			(__NR_Linux + 254)
 #define __NR_linkat			(__NR_Linux + 255)
@@ -614,16 +616,18 @@
 #define __NR_tee			(__NR_Linux + 265)
 #define __NR_vmsplice			(__NR_Linux + 266)
 #define __NR_move_pages			(__NR_Linux + 267)
+#define __NR_set_robust_list		(__NR_Linux + 268)
+#define __NR_get_robust_list		(__NR_Linux + 269)
 
 /*
  * Offset of the last Linux 64-bit flavoured syscall
  */
-#define __NR_Linux_syscalls		267
+#define __NR_Linux_syscalls		269
 
 #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
 
 #define __NR_64_Linux			5000
-#define __NR_64_Linux_syscalls		267
+#define __NR_64_Linux_syscalls		269
 
 #if _MIPS_SIM == _MIPS_SIM_NABI32
 
@@ -887,7 +891,7 @@
 #define __NR_mknodat			(__NR_Linux + 253)
 #define __NR_fchownat			(__NR_Linux + 254)
 #define __NR_futimesat			(__NR_Linux + 255)
-#define __NR_fstatat			(__NR_Linux + 256)
+#define __NR_newfstatat			(__NR_Linux + 256)
 #define __NR_unlinkat			(__NR_Linux + 257)
 #define __NR_renameat			(__NR_Linux + 258)
 #define __NR_linkat			(__NR_Linux + 259)
@@ -903,16 +907,18 @@
 #define __NR_tee			(__NR_Linux + 269)
 #define __NR_vmsplice			(__NR_Linux + 270)
 #define __NR_move_pages			(__NR_Linux + 271)
+#define __NR_set_robust_list		(__NR_Linux + 272)
+#define __NR_get_robust_list		(__NR_Linux + 273)
 
 /*
  * Offset of the last N32 flavoured syscall
  */
-#define __NR_Linux_syscalls		271
+#define __NR_Linux_syscalls		273
 
 #endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
 
 #define __NR_N32_Linux			6000
-#define __NR_N32_Linux_syscalls		271
+#define __NR_N32_Linux_syscalls		273
 
 #ifdef __KERNEL__
 
diff -Naur linux-2.6.18.1/include/asm-mips/user.h linux-mips-2.6.18.1/include/asm-mips/user.h
--- linux-2.6.18.1/include/asm-mips/user.h	2006-10-13 20:34:03.000000000 -0700
+++ linux-mips-2.6.18.1/include/asm-mips/user.h	2006-10-17 06:23:28.000000000 -0700
@@ -8,6 +8,8 @@
 #ifndef _ASM_USER_H
 #define _ASM_USER_H
 
+#ifdef __KERNEL__
+
 #include <asm/page.h>
 #include <asm/reg.h>
 
@@ -55,4 +57,6 @@
 #define HOST_DATA_START_ADDR	(u.start_data)
 #define HOST_STACK_END_ADDR	(u.start_stack + u.u_ssize * NBPG)
 
+#endif /* __KERNEL__ */
+
 #endif /* _ASM_USER_H */
diff -Naur linux-2.6.18.1/include/linux/pci_ids.h linux-mips-2.6.18.1/include/linux/pci_ids.h
--- linux-2.6.18.1/include/linux/pci_ids.h	2006-10-13 20:34:03.000000000 -0700
+++ linux-mips-2.6.18.1/include/linux/pci_ids.h	2006-10-17 06:23:28.000000000 -0700
@@ -1603,6 +1603,9 @@
 #define PCI_VENDOR_ID_SATSAGEM		0x1267
 #define PCI_DEVICE_ID_SATSAGEM_NICCY	0x1016
 
+#define PCI_VENDOR_ID_SILICON_MOTION		0x126f
+#define PCI_DEVICE_ID_SM501_VOYAGER_GX_REV_AA	0x0501
+#define PCI_DEVICE_ID_SM501_VOYAGER_GX_REV_B	0x0510
 
 #define PCI_VENDOR_ID_ENSONIQ		0x1274
 #define PCI_DEVICE_ID_ENSONIQ_CT5880	0x5880
diff -Naur linux-2.6.18.1/include/linux/serial.h linux-mips-2.6.18.1/include/linux/serial.h
--- linux-2.6.18.1/include/linux/serial.h	2006-10-13 20:34:03.000000000 -0700
+++ linux-mips-2.6.18.1/include/linux/serial.h	2006-10-17 06:23:28.000000000 -0700
@@ -76,7 +76,8 @@
 #define PORT_16654	11
 #define PORT_16850	12
 #define PORT_RSA	13	/* RSA-DV II/S card */
-#define PORT_MAX	13
+#define PORT_SB1250	14
+#define PORT_MAX	14
 
 #define SERIAL_IO_PORT	0
 #define SERIAL_IO_HUB6	1
diff -Naur linux-2.6.18.1/include/linux/serial_ip3106.h linux-mips-2.6.18.1/include/linux/serial_ip3106.h
--- linux-2.6.18.1/include/linux/serial_ip3106.h	2006-10-13 20:34:03.000000000 -0700
+++ linux-mips-2.6.18.1/include/linux/serial_ip3106.h	2006-10-17 06:23:28.000000000 -0700
@@ -78,4 +78,16 @@
 #define IP3106_UART_FIFO_RXFIFO		0x00001F00
 #define IP3106_UART_FIFO_RBRTHR		0x000000FF
 
+#define ip3106_lcr(base,port)    *(volatile u32 *)(base+(port*0x1000) + 0x000)
+#define ip3106_mcr(base, port)   *(volatile u32 *)(base+(port*0x1000) + 0x004)
+#define ip3106_baud(base, port)  *(volatile u32 *)(base+(port*0x1000) + 0x008)
+#define ip3106_cfg(base, port)   *(volatile u32 *)(base+(port*0x1000) + 0x00C)
+#define ip3106_fifo(base, port)	 *(volatile u32 *)(base+(port*0x1000) + 0x028)
+#define ip3106_istat(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFE0)
+#define ip3106_ien(base, port)   *(volatile u32 *)(base+(port*0x1000) + 0xFE4)
+#define ip3106_iclr(base, port)  *(volatile u32 *)(base+(port*0x1000) + 0xFE8)
+#define ip3106_iset(base, port)  *(volatile u32 *)(base+(port*0x1000) + 0xFEC)
+#define ip3106_pd(base, port)    *(volatile u32 *)(base+(port*0x1000) + 0xFF4)
+#define ip3106_mid(base, port)   *(volatile u32 *)(base+(port*0x1000) + 0xFFC)
+
 #endif