Contents of /trunk/linux-libc-headers/patches/linux-2.6.18.2-mips_headers-1.patch
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Revision 435 -
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Fri Mar 16 00:06:55 2007 UTC (17 years, 6 months ago) by niro
File size: 22114 byte(s)
Fri Mar 16 00:06:55 2007 UTC (17 years, 6 months ago) by niro
File size: 22114 byte(s)
updated to upstream svn-149
1 | diff -Naur linux-2.6.18.2.orig/include/asm-mips/asm.h linux-2.6.18.2/include/asm-mips/asm.h |
2 | --- linux-2.6.18.2.orig/include/asm-mips/asm.h 2006-11-03 17:33:58.000000000 -0800 |
3 | +++ linux-2.6.18.2/include/asm-mips/asm.h 2006-11-04 14:51:12.000000000 -0800 |
4 | @@ -344,6 +344,7 @@ |
5 | #define PTR_L lw |
6 | #define PTR_S sw |
7 | #define PTR_LA la |
8 | +#define PTR_LI li |
9 | #define PTR_SLL sll |
10 | #define PTR_SLLV sllv |
11 | #define PTR_SRL srl |
12 | @@ -368,6 +369,7 @@ |
13 | #define PTR_L ld |
14 | #define PTR_S sd |
15 | #define PTR_LA dla |
16 | +#define PTR_LI dli |
17 | #define PTR_SLL dsll |
18 | #define PTR_SLLV dsllv |
19 | #define PTR_SRL dsrl |
20 | diff -Naur linux-2.6.18.2.orig/include/asm-mips/cacheflush.h linux-2.6.18.2/include/asm-mips/cacheflush.h |
21 | --- linux-2.6.18.2.orig/include/asm-mips/cacheflush.h 2006-11-03 17:33:58.000000000 -0800 |
22 | +++ linux-2.6.18.2/include/asm-mips/cacheflush.h 2006-11-04 14:51:12.000000000 -0800 |
23 | @@ -21,7 +21,6 @@ |
24 | * - flush_cache_range(vma, start, end) flushes a range of pages |
25 | * - flush_icache_range(start, end) flush a range of instructions |
26 | * - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache |
27 | - * - flush_icache_page(vma, pg) flushes(invalidates) a page for icache |
28 | * |
29 | * MIPS specific flush operations: |
30 | * |
31 | @@ -39,7 +38,7 @@ |
32 | |
33 | static inline void flush_dcache_page(struct page *page) |
34 | { |
35 | - if (cpu_has_dc_aliases) |
36 | + if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc) |
37 | __flush_dcache_page(page); |
38 | |
39 | } |
40 | @@ -47,30 +46,24 @@ |
41 | #define flush_dcache_mmap_lock(mapping) do { } while (0) |
42 | #define flush_dcache_mmap_unlock(mapping) do { } while (0) |
43 | |
44 | -extern void (*flush_icache_page)(struct vm_area_struct *vma, |
45 | +extern void (*__flush_icache_page)(struct vm_area_struct *vma, |
46 | struct page *page); |
47 | +static inline void flush_icache_page(struct vm_area_struct *vma, |
48 | + struct page *page) |
49 | +{ |
50 | +} |
51 | + |
52 | extern void (*flush_icache_range)(unsigned long start, unsigned long end); |
53 | #define flush_cache_vmap(start, end) flush_cache_all() |
54 | #define flush_cache_vunmap(start, end) flush_cache_all() |
55 | |
56 | -static inline void copy_to_user_page(struct vm_area_struct *vma, |
57 | +extern void copy_to_user_page(struct vm_area_struct *vma, |
58 | struct page *page, unsigned long vaddr, void *dst, const void *src, |
59 | - unsigned long len) |
60 | -{ |
61 | - if (cpu_has_dc_aliases) |
62 | - flush_cache_page(vma, vaddr, page_to_pfn(page)); |
63 | - memcpy(dst, src, len); |
64 | - flush_icache_page(vma, page); |
65 | -} |
66 | + unsigned long len); |
67 | |
68 | -static inline void copy_from_user_page(struct vm_area_struct *vma, |
69 | +extern void copy_from_user_page(struct vm_area_struct *vma, |
70 | struct page *page, unsigned long vaddr, void *dst, const void *src, |
71 | - unsigned long len) |
72 | -{ |
73 | - if (cpu_has_dc_aliases) |
74 | - flush_cache_page(vma, vaddr, page_to_pfn(page)); |
75 | - memcpy(dst, src, len); |
76 | -} |
77 | + unsigned long len); |
78 | |
79 | extern void (*flush_cache_sigtramp)(unsigned long addr); |
80 | extern void (*flush_icache_all)(void); |
81 | diff -Naur linux-2.6.18.2.orig/include/asm-mips/fixmap.h linux-2.6.18.2/include/asm-mips/fixmap.h |
82 | --- linux-2.6.18.2.orig/include/asm-mips/fixmap.h 2006-11-03 17:33:58.000000000 -0800 |
83 | +++ linux-2.6.18.2/include/asm-mips/fixmap.h 2006-11-04 14:51:12.000000000 -0800 |
84 | @@ -45,8 +45,16 @@ |
85 | * fix-mapped? |
86 | */ |
87 | enum fixed_addresses { |
88 | +#define FIX_N_COLOURS 8 |
89 | + FIX_CMAP_BEGIN, |
90 | +#ifdef CONFIG_MIPS_MT_SMTC |
91 | + FIX_CMAP_END = FIX_CMAP_BEGIN + (FIX_N_COLOURS * NR_CPUS), |
92 | +#else |
93 | + FIX_CMAP_END = FIX_CMAP_BEGIN + FIX_N_COLOURS, |
94 | +#endif |
95 | #ifdef CONFIG_HIGHMEM |
96 | - FIX_KMAP_BEGIN, /* reserved pte's for temporary kernel mappings */ |
97 | + /* reserved pte's for temporary kernel mappings */ |
98 | + FIX_KMAP_BEGIN = FIX_CMAP_END + 1, |
99 | FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1, |
100 | #endif |
101 | __end_of_fixed_addresses |
102 | @@ -70,9 +78,9 @@ |
103 | * at the top of mem.. |
104 | */ |
105 | #if defined(CONFIG_CPU_TX39XX) || defined(CONFIG_CPU_TX49XX) |
106 | -#define FIXADDR_TOP (0xff000000UL - 0x2000) |
107 | +#define FIXADDR_TOP ((unsigned long)(long)(int)(0xff000000 - 0x20000)) |
108 | #else |
109 | -#define FIXADDR_TOP (0xffffe000UL) |
110 | +#define FIXADDR_TOP ((unsigned long)(long)(int)0xfffe0000) |
111 | #endif |
112 | #define FIXADDR_SIZE (__end_of_fixed_addresses << PAGE_SHIFT) |
113 | #define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE) |
114 | diff -Naur linux-2.6.18.2.orig/include/asm-mips/fpu.h linux-2.6.18.2/include/asm-mips/fpu.h |
115 | --- linux-2.6.18.2.orig/include/asm-mips/fpu.h 2006-11-03 17:33:58.000000000 -0800 |
116 | +++ linux-2.6.18.2/include/asm-mips/fpu.h 2006-11-04 14:51:12.000000000 -0800 |
117 | @@ -134,9 +134,11 @@ |
118 | |
119 | static inline fpureg_t *get_fpu_regs(struct task_struct *tsk) |
120 | { |
121 | - if (cpu_has_fpu) { |
122 | - if ((tsk == current) && __is_fpu_owner()) |
123 | + if (tsk == current) { |
124 | + preempt_disable(); |
125 | + if (is_fpu_owner()) |
126 | _save_fp(current); |
127 | + preempt_enable(); |
128 | } |
129 | |
130 | return tsk->thread.fpu.fpr; |
131 | diff -Naur linux-2.6.18.2.orig/include/asm-mips/io.h linux-2.6.18.2/include/asm-mips/io.h |
132 | --- linux-2.6.18.2.orig/include/asm-mips/io.h 2006-11-03 17:33:58.000000000 -0800 |
133 | +++ linux-2.6.18.2/include/asm-mips/io.h 2006-11-04 14:51:12.000000000 -0800 |
134 | @@ -172,7 +172,7 @@ |
135 | #define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT) |
136 | |
137 | extern void __iomem * __ioremap(phys_t offset, phys_t size, unsigned long flags); |
138 | -extern void __iounmap(volatile void __iomem *addr); |
139 | +extern void __iounmap(const volatile void __iomem *addr); |
140 | |
141 | static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size, |
142 | unsigned long flags) |
143 | @@ -279,7 +279,7 @@ |
144 | #define ioremap_uncached_accelerated(offset, size) \ |
145 | __ioremap_mode((offset), (size), _CACHE_UNCACHED_ACCELERATED) |
146 | |
147 | -static inline void iounmap(volatile void __iomem *addr) |
148 | +static inline void iounmap(const volatile void __iomem *addr) |
149 | { |
150 | #define __IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1) |
151 | |
152 | diff -Naur linux-2.6.18.2.orig/include/asm-mips/irq.h linux-2.6.18.2/include/asm-mips/irq.h |
153 | --- linux-2.6.18.2.orig/include/asm-mips/irq.h 2006-11-03 17:33:58.000000000 -0800 |
154 | +++ linux-2.6.18.2/include/asm-mips/irq.h 2006-11-04 14:51:12.000000000 -0800 |
155 | @@ -76,8 +76,4 @@ |
156 | unsigned long hwmask); |
157 | #endif /* CONFIG_MIPS_MT_SMTC */ |
158 | |
159 | -#ifdef CONFIG_SMP |
160 | -#define ARCH_HAS_IRQ_PER_CPU |
161 | -#endif |
162 | - |
163 | #endif /* _ASM_IRQ_H */ |
164 | diff -Naur linux-2.6.18.2.orig/include/asm-mips/mach-atlas/mc146818rtc.h linux-2.6.18.2/include/asm-mips/mach-atlas/mc146818rtc.h |
165 | --- linux-2.6.18.2.orig/include/asm-mips/mach-atlas/mc146818rtc.h 2006-11-03 17:33:58.000000000 -0800 |
166 | +++ linux-2.6.18.2/include/asm-mips/mach-atlas/mc146818rtc.h 2006-11-04 14:51:12.000000000 -0800 |
167 | @@ -28,10 +28,12 @@ |
168 | #include <asm/mips-boards/atlas.h> |
169 | #include <asm/mips-boards/atlasint.h> |
170 | |
171 | +#define ARCH_RTC_LOCATION |
172 | + |
173 | #define RTC_PORT(x) (ATLAS_RTC_ADR_REG + (x) * 8) |
174 | #define RTC_IO_EXTENT 0x100 |
175 | #define RTC_IOMAPPED 0 |
176 | -#define RTC_IRQ ATLASINT_RTC |
177 | +#define RTC_IRQ ATLAS_INT_RTC |
178 | |
179 | static inline unsigned char CMOS_READ(unsigned long addr) |
180 | { |
181 | diff -Naur linux-2.6.18.2.orig/include/asm-mips/mach-au1x00/au1xxx_ide.h linux-2.6.18.2/include/asm-mips/mach-au1x00/au1xxx_ide.h |
182 | --- linux-2.6.18.2.orig/include/asm-mips/mach-au1x00/au1xxx_ide.h 2006-11-03 17:33:58.000000000 -0800 |
183 | +++ linux-2.6.18.2/include/asm-mips/mach-au1x00/au1xxx_ide.h 2006-11-04 14:51:12.000000000 -0800 |
184 | @@ -83,6 +83,7 @@ |
185 | } _auide_hwif; |
186 | |
187 | #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA |
188 | + |
189 | /* HD white list */ |
190 | static const struct drive_list_entry dma_white_list [] = { |
191 | /* |
192 | diff -Naur linux-2.6.18.2.orig/include/asm-mips/mips-boards/atlasint.h linux-2.6.18.2/include/asm-mips/mips-boards/atlasint.h |
193 | --- linux-2.6.18.2.orig/include/asm-mips/mips-boards/atlasint.h 2006-11-03 17:33:58.000000000 -0800 |
194 | +++ linux-2.6.18.2/include/asm-mips/mips-boards/atlasint.h 2006-11-04 14:51:12.000000000 -0800 |
195 | @@ -1,6 +1,7 @@ |
196 | /* |
197 | - * Carsten Langgaard, carstenl@mips.com |
198 | - * Copyright (C) 1999 MIPS Technologies, Inc. All rights reserved. |
199 | + * Copyright (C) 1999, 2006 MIPS Technologies, Inc. All rights reserved. |
200 | + * Authors: Carsten Langgaard <carstenl@mips.com> |
201 | + * Maciej W. Rozycki <macro@mips.com> |
202 | * |
203 | * ######################################################################## |
204 | * |
205 | @@ -25,41 +26,88 @@ |
206 | #ifndef _MIPS_ATLASINT_H |
207 | #define _MIPS_ATLASINT_H |
208 | |
209 | -#define ATLASINT_BASE 1 |
210 | -#define ATLASINT_UART (ATLASINT_BASE+0) |
211 | -#define ATLASINT_TIM0 (ATLASINT_BASE+1) |
212 | -#define ATLASINT_RES2 (ATLASINT_BASE+2) |
213 | -#define ATLASINT_RES3 (ATLASINT_BASE+3) |
214 | -#define ATLASINT_RTC (ATLASINT_BASE+4) |
215 | -#define ATLASINT_COREHI (ATLASINT_BASE+5) |
216 | -#define ATLASINT_CORELO (ATLASINT_BASE+6) |
217 | -#define ATLASINT_RES7 (ATLASINT_BASE+7) |
218 | -#define ATLASINT_PCIA (ATLASINT_BASE+8) |
219 | -#define ATLASINT_PCIB (ATLASINT_BASE+9) |
220 | -#define ATLASINT_PCIC (ATLASINT_BASE+10) |
221 | -#define ATLASINT_PCID (ATLASINT_BASE+11) |
222 | -#define ATLASINT_ENUM (ATLASINT_BASE+12) |
223 | -#define ATLASINT_DEG (ATLASINT_BASE+13) |
224 | -#define ATLASINT_ATXFAIL (ATLASINT_BASE+14) |
225 | -#define ATLASINT_INTA (ATLASINT_BASE+15) |
226 | -#define ATLASINT_INTB (ATLASINT_BASE+16) |
227 | -#define ATLASINT_ETH ATLASINT_INTB |
228 | -#define ATLASINT_INTC (ATLASINT_BASE+17) |
229 | -#define ATLASINT_SCSI ATLASINT_INTC |
230 | -#define ATLASINT_INTD (ATLASINT_BASE+18) |
231 | -#define ATLASINT_SERR (ATLASINT_BASE+19) |
232 | -#define ATLASINT_RES20 (ATLASINT_BASE+20) |
233 | -#define ATLASINT_RES21 (ATLASINT_BASE+21) |
234 | -#define ATLASINT_RES22 (ATLASINT_BASE+22) |
235 | -#define ATLASINT_RES23 (ATLASINT_BASE+23) |
236 | -#define ATLASINT_RES24 (ATLASINT_BASE+24) |
237 | -#define ATLASINT_RES25 (ATLASINT_BASE+25) |
238 | -#define ATLASINT_RES26 (ATLASINT_BASE+26) |
239 | -#define ATLASINT_RES27 (ATLASINT_BASE+27) |
240 | -#define ATLASINT_RES28 (ATLASINT_BASE+28) |
241 | -#define ATLASINT_RES29 (ATLASINT_BASE+29) |
242 | -#define ATLASINT_RES30 (ATLASINT_BASE+30) |
243 | -#define ATLASINT_RES31 (ATLASINT_BASE+31) |
244 | -#define ATLASINT_END (ATLASINT_BASE+31) |
245 | +/* |
246 | + * Interrupts 0..7 are used for Atlas CPU interrupts (nonEIC mode) |
247 | + */ |
248 | +#define MIPSCPU_INT_BASE 0 |
249 | + |
250 | +/* CPU interrupt offsets */ |
251 | +#define MIPSCPU_INT_SW0 0 |
252 | +#define MIPSCPU_INT_SW1 1 |
253 | +#define MIPSCPU_INT_MB0 2 |
254 | +#define MIPSCPU_INT_ATLAS MIPSCPU_INT_MB0 |
255 | +#define MIPSCPU_INT_MB1 3 |
256 | +#define MIPSCPU_INT_MB2 4 |
257 | +#define MIPSCPU_INT_MB3 5 |
258 | +#define MIPSCPU_INT_MB4 6 |
259 | +#define MIPSCPU_INT_CPUCTR 7 |
260 | + |
261 | +/* |
262 | + * Interrupts 8..39 are used for Atlas interrupt controller interrupts |
263 | + */ |
264 | +#define ATLAS_INT_BASE 8 |
265 | +#define ATLAS_INT_UART (ATLAS_INT_BASE + 0) |
266 | +#define ATLAS_INT_TIM0 (ATLAS_INT_BASE + 1) |
267 | +#define ATLAS_INT_RES2 (ATLAS_INT_BASE + 2) |
268 | +#define ATLAS_INT_RES3 (ATLAS_INT_BASE + 3) |
269 | +#define ATLAS_INT_RTC (ATLAS_INT_BASE + 4) |
270 | +#define ATLAS_INT_COREHI (ATLAS_INT_BASE + 5) |
271 | +#define ATLAS_INT_CORELO (ATLAS_INT_BASE + 6) |
272 | +#define ATLAS_INT_RES7 (ATLAS_INT_BASE + 7) |
273 | +#define ATLAS_INT_PCIA (ATLAS_INT_BASE + 8) |
274 | +#define ATLAS_INT_PCIB (ATLAS_INT_BASE + 9) |
275 | +#define ATLAS_INT_PCIC (ATLAS_INT_BASE + 10) |
276 | +#define ATLAS_INT_PCID (ATLAS_INT_BASE + 11) |
277 | +#define ATLAS_INT_ENUM (ATLAS_INT_BASE + 12) |
278 | +#define ATLAS_INT_DEG (ATLAS_INT_BASE + 13) |
279 | +#define ATLAS_INT_ATXFAIL (ATLAS_INT_BASE + 14) |
280 | +#define ATLAS_INT_INTA (ATLAS_INT_BASE + 15) |
281 | +#define ATLAS_INT_INTB (ATLAS_INT_BASE + 16) |
282 | +#define ATLAS_INT_ETH ATLAS_INT_INTB |
283 | +#define ATLAS_INT_INTC (ATLAS_INT_BASE + 17) |
284 | +#define ATLAS_INT_SCSI ATLAS_INT_INTC |
285 | +#define ATLAS_INT_INTD (ATLAS_INT_BASE + 18) |
286 | +#define ATLAS_INT_SERR (ATLAS_INT_BASE + 19) |
287 | +#define ATLAS_INT_RES20 (ATLAS_INT_BASE + 20) |
288 | +#define ATLAS_INT_RES21 (ATLAS_INT_BASE + 21) |
289 | +#define ATLAS_INT_RES22 (ATLAS_INT_BASE + 22) |
290 | +#define ATLAS_INT_RES23 (ATLAS_INT_BASE + 23) |
291 | +#define ATLAS_INT_RES24 (ATLAS_INT_BASE + 24) |
292 | +#define ATLAS_INT_RES25 (ATLAS_INT_BASE + 25) |
293 | +#define ATLAS_INT_RES26 (ATLAS_INT_BASE + 26) |
294 | +#define ATLAS_INT_RES27 (ATLAS_INT_BASE + 27) |
295 | +#define ATLAS_INT_RES28 (ATLAS_INT_BASE + 28) |
296 | +#define ATLAS_INT_RES29 (ATLAS_INT_BASE + 29) |
297 | +#define ATLAS_INT_RES30 (ATLAS_INT_BASE + 30) |
298 | +#define ATLAS_INT_RES31 (ATLAS_INT_BASE + 31) |
299 | +#define ATLAS_INT_END (ATLAS_INT_BASE + 31) |
300 | + |
301 | +/* |
302 | + * Interrupts 64..127 are used for Soc-it Classic interrupts |
303 | + */ |
304 | +#define MSC01C_INT_BASE 64 |
305 | + |
306 | +/* SOC-it Classic interrupt offsets */ |
307 | +#define MSC01C_INT_TMR 0 |
308 | +#define MSC01C_INT_PCI 1 |
309 | + |
310 | +/* |
311 | + * Interrupts 64..127 are used for Soc-it EIC interrupts |
312 | + */ |
313 | +#define MSC01E_INT_BASE 64 |
314 | + |
315 | +/* SOC-it EIC interrupt offsets */ |
316 | +#define MSC01E_INT_SW0 1 |
317 | +#define MSC01E_INT_SW1 2 |
318 | +#define MSC01E_INT_MB0 3 |
319 | +#define MSC01E_INT_ATLAS MSC01E_INT_MB0 |
320 | +#define MSC01E_INT_MB1 4 |
321 | +#define MSC01E_INT_MB2 5 |
322 | +#define MSC01E_INT_MB3 6 |
323 | +#define MSC01E_INT_MB4 7 |
324 | +#define MSC01E_INT_TMR 8 |
325 | +#define MSC01E_INT_PCI 9 |
326 | +#define MSC01E_INT_PERFCTR 10 |
327 | +#define MSC01E_INT_CPUCTR 11 |
328 | |
329 | #endif /* !(_MIPS_ATLASINT_H) */ |
330 | diff -Naur linux-2.6.18.2.orig/include/asm-mips/page.h linux-2.6.18.2/include/asm-mips/page.h |
331 | --- linux-2.6.18.2.orig/include/asm-mips/page.h 2006-11-03 17:33:58.000000000 -0800 |
332 | +++ linux-2.6.18.2/include/asm-mips/page.h 2006-11-04 14:51:12.000000000 -0800 |
333 | @@ -53,19 +53,17 @@ |
334 | extern void (*flush_data_cache_page)(unsigned long addr); |
335 | |
336 | clear_page(addr); |
337 | - if (pages_do_alias((unsigned long) addr, vaddr)) |
338 | + if (pages_do_alias((unsigned long) addr, vaddr & PAGE_MASK)) |
339 | flush_data_cache_page((unsigned long)addr); |
340 | } |
341 | |
342 | -static inline void copy_user_page(void *vto, void *vfrom, unsigned long vaddr, |
343 | - struct page *to) |
344 | -{ |
345 | - extern void (*flush_data_cache_page)(unsigned long addr); |
346 | +extern void copy_user_page(void *vto, void *vfrom, unsigned long vaddr, |
347 | + struct page *to); |
348 | +struct vm_area_struct; |
349 | +extern void copy_user_highpage(struct page *to, struct page *from, |
350 | + unsigned long vaddr, struct vm_area_struct *vma); |
351 | |
352 | - copy_page(vto, vfrom); |
353 | - if (pages_do_alias((unsigned long)vto, vaddr)) |
354 | - flush_data_cache_page((unsigned long)vto); |
355 | -} |
356 | +#define __HAVE_ARCH_COPY_USER_HIGHPAGE |
357 | |
358 | /* |
359 | * These are used to make use of C type-checking.. |
360 | @@ -74,15 +72,17 @@ |
361 | #ifdef CONFIG_CPU_MIPS32 |
362 | typedef struct { unsigned long pte_low, pte_high; } pte_t; |
363 | #define pte_val(x) ((x).pte_low | ((unsigned long long)(x).pte_high << 32)) |
364 | + #define __pte(x) ({ pte_t __pte = {(x), ((unsigned long long)(x)) >> 32}; __pte; }) |
365 | #else |
366 | typedef struct { unsigned long long pte; } pte_t; |
367 | #define pte_val(x) ((x).pte) |
368 | + #define __pte(x) ((pte_t) { (x) } ) |
369 | #endif |
370 | #else |
371 | typedef struct { unsigned long pte; } pte_t; |
372 | #define pte_val(x) ((x).pte) |
373 | -#endif |
374 | #define __pte(x) ((pte_t) { (x) } ) |
375 | +#endif |
376 | |
377 | /* |
378 | * For 3-level pagetables we defines these ourselves, for 2-level the |
379 | diff -Naur linux-2.6.18.2.orig/include/asm-mips/pgalloc.h linux-2.6.18.2/include/asm-mips/pgalloc.h |
380 | --- linux-2.6.18.2.orig/include/asm-mips/pgalloc.h 2006-11-03 17:33:58.000000000 -0800 |
381 | +++ linux-2.6.18.2/include/asm-mips/pgalloc.h 2006-11-04 14:51:12.000000000 -0800 |
382 | @@ -48,7 +48,7 @@ |
383 | |
384 | ret = (pgd_t *) __get_free_pages(GFP_KERNEL, PGD_ORDER); |
385 | if (ret) { |
386 | - init = pgd_offset(&init_mm, 0); |
387 | + init = pgd_offset(&init_mm, 0UL); |
388 | pgd_init((unsigned long)ret); |
389 | memcpy(ret + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD, |
390 | (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t)); |
391 | diff -Naur linux-2.6.18.2.orig/include/asm-mips/pgtable-64.h linux-2.6.18.2/include/asm-mips/pgtable-64.h |
392 | --- linux-2.6.18.2.orig/include/asm-mips/pgtable-64.h 2006-11-03 17:33:58.000000000 -0800 |
393 | +++ linux-2.6.18.2/include/asm-mips/pgtable-64.h 2006-11-04 14:51:12.000000000 -0800 |
394 | @@ -170,7 +170,7 @@ |
395 | #define __pmd_offset(address) pmd_index(address) |
396 | |
397 | /* to find an entry in a kernel page-table-directory */ |
398 | -#define pgd_offset_k(address) pgd_offset(&init_mm, 0) |
399 | +#define pgd_offset_k(address) pgd_offset(&init_mm, 0UL) |
400 | |
401 | #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) |
402 | #define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) |
403 | diff -Naur linux-2.6.18.2.orig/include/asm-mips/ptrace.h linux-2.6.18.2/include/asm-mips/ptrace.h |
404 | --- linux-2.6.18.2.orig/include/asm-mips/ptrace.h 2006-11-03 17:33:58.000000000 -0800 |
405 | +++ linux-2.6.18.2/include/asm-mips/ptrace.h 2006-11-04 14:51:12.000000000 -0800 |
406 | @@ -10,8 +10,6 @@ |
407 | #define _ASM_PTRACE_H |
408 | |
409 | |
410 | -#include <asm/isadep.h> |
411 | - |
412 | /* 0 - 31 are integer registers, 32 - 63 are fp registers. */ |
413 | #define FPR_BASE 32 |
414 | #define PC 64 |
415 | @@ -73,6 +71,7 @@ |
416 | #ifdef __KERNEL__ |
417 | |
418 | #include <linux/linkage.h> |
419 | +#include <asm/isadep.h> |
420 | |
421 | /* |
422 | * Does the process account for user or for system time? |
423 | diff -Naur linux-2.6.18.2.orig/include/asm-mips/spinlock.h linux-2.6.18.2/include/asm-mips/spinlock.h |
424 | --- linux-2.6.18.2.orig/include/asm-mips/spinlock.h 2006-11-03 17:33:58.000000000 -0800 |
425 | +++ linux-2.6.18.2/include/asm-mips/spinlock.h 2006-11-04 14:51:12.000000000 -0800 |
426 | @@ -239,7 +239,51 @@ |
427 | : "memory"); |
428 | } |
429 | |
430 | -#define __raw_read_trylock(lock) generic__raw_read_trylock(lock) |
431 | +static inline int __raw_read_trylock(raw_rwlock_t *rw) |
432 | +{ |
433 | + unsigned int tmp; |
434 | + int ret; |
435 | + |
436 | + if (R10000_LLSC_WAR) { |
437 | + __asm__ __volatile__( |
438 | + " .set noreorder # __raw_read_trylock \n" |
439 | + " li %2, 0 \n" |
440 | + "1: ll %1, %3 \n" |
441 | + " bnez %1, 2f \n" |
442 | + " addu %1, 1 \n" |
443 | + " sc %1, %0 \n" |
444 | + " beqzl %1, 1b \n" |
445 | + " .set reorder \n" |
446 | +#ifdef CONFIG_SMP |
447 | + " sync \n" |
448 | +#endif |
449 | + " li %2, 1 \n" |
450 | + "2: \n" |
451 | + : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret) |
452 | + : "m" (rw->lock) |
453 | + : "memory"); |
454 | + } else { |
455 | + __asm__ __volatile__( |
456 | + " .set noreorder # __raw_read_trylock \n" |
457 | + " li %2, 0 \n" |
458 | + "1: ll %1, %3 \n" |
459 | + " bnez %1, 2f \n" |
460 | + " addu %1, 1 \n" |
461 | + " sc %1, %0 \n" |
462 | + " beqz %1, 1b \n" |
463 | + " .set reorder \n" |
464 | +#ifdef CONFIG_SMP |
465 | + " sync \n" |
466 | +#endif |
467 | + " li %2, 1 \n" |
468 | + "2: \n" |
469 | + : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret) |
470 | + : "m" (rw->lock) |
471 | + : "memory"); |
472 | + } |
473 | + |
474 | + return ret; |
475 | +} |
476 | |
477 | static inline int __raw_write_trylock(raw_rwlock_t *rw) |
478 | { |
479 | @@ -283,4 +327,5 @@ |
480 | return ret; |
481 | } |
482 | |
483 | + |
484 | #endif /* _ASM_SPINLOCK_H */ |
485 | diff -Naur linux-2.6.18.2.orig/include/asm-mips/system.h linux-2.6.18.2/include/asm-mips/system.h |
486 | --- linux-2.6.18.2.orig/include/asm-mips/system.h 2006-11-03 17:33:58.000000000 -0800 |
487 | +++ linux-2.6.18.2/include/asm-mips/system.h 2006-11-04 14:51:12.000000000 -0800 |
488 | @@ -392,7 +392,7 @@ |
489 | { |
490 | __u64 retval; |
491 | |
492 | - if (cpu_has_llsc) { |
493 | + if (cpu_has_llsc && R10000_LLSC_WAR) { |
494 | __asm__ __volatile__( |
495 | " .set push \n" |
496 | " .set noat \n" |
497 | diff -Naur linux-2.6.18.2.orig/include/asm-mips/timex.h linux-2.6.18.2/include/asm-mips/timex.h |
498 | --- linux-2.6.18.2.orig/include/asm-mips/timex.h 2006-11-03 17:33:58.000000000 -0800 |
499 | +++ linux-2.6.18.2/include/asm-mips/timex.h 2006-11-04 14:51:12.000000000 -0800 |
500 | @@ -8,6 +8,8 @@ |
501 | #ifndef _ASM_TIMEX_H |
502 | #define _ASM_TIMEX_H |
503 | |
504 | +#ifdef __KERNEL__ |
505 | + |
506 | #include <asm/mipsregs.h> |
507 | |
508 | /* |
509 | @@ -51,4 +53,6 @@ |
510 | return read_c0_count(); |
511 | } |
512 | |
513 | +#endif /* __KERNEL__ */ |
514 | + |
515 | #endif /* _ASM_TIMEX_H */ |
516 | diff -Naur linux-2.6.18.2.orig/include/asm-mips/unistd.h linux-2.6.18.2/include/asm-mips/unistd.h |
517 | --- linux-2.6.18.2.orig/include/asm-mips/unistd.h 2006-11-03 17:33:58.000000000 -0800 |
518 | +++ linux-2.6.18.2/include/asm-mips/unistd.h 2006-11-04 14:51:12.000000000 -0800 |
519 | @@ -313,7 +313,7 @@ |
520 | #define __NR_mknodat (__NR_Linux + 290) |
521 | #define __NR_fchownat (__NR_Linux + 291) |
522 | #define __NR_futimesat (__NR_Linux + 292) |
523 | -#define __NR_fstatat (__NR_Linux + 293) |
524 | +#define __NR_fstatat64 (__NR_Linux + 293) |
525 | #define __NR_unlinkat (__NR_Linux + 294) |
526 | #define __NR_renameat (__NR_Linux + 295) |
527 | #define __NR_linkat (__NR_Linux + 296) |
528 | @@ -329,16 +329,18 @@ |
529 | #define __NR_tee (__NR_Linux + 306) |
530 | #define __NR_vmsplice (__NR_Linux + 307) |
531 | #define __NR_move_pages (__NR_Linux + 308) |
532 | +#define __NR_set_robust_list (__NR_Linux + 309) |
533 | +#define __NR_get_robust_list (__NR_Linux + 310) |
534 | |
535 | /* |
536 | * Offset of the last Linux o32 flavoured syscall |
537 | */ |
538 | -#define __NR_Linux_syscalls 308 |
539 | +#define __NR_Linux_syscalls 310 |
540 | |
541 | #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ |
542 | |
543 | #define __NR_O32_Linux 4000 |
544 | -#define __NR_O32_Linux_syscalls 308 |
545 | +#define __NR_O32_Linux_syscalls 310 |
546 | |
547 | #if _MIPS_SIM == _MIPS_SIM_ABI64 |
548 | |
549 | @@ -598,7 +600,7 @@ |
550 | #define __NR_mknodat (__NR_Linux + 249) |
551 | #define __NR_fchownat (__NR_Linux + 250) |
552 | #define __NR_futimesat (__NR_Linux + 251) |
553 | -#define __NR_fstatat (__NR_Linux + 252) |
554 | +#define __NR_newfstatat (__NR_Linux + 252) |
555 | #define __NR_unlinkat (__NR_Linux + 253) |
556 | #define __NR_renameat (__NR_Linux + 254) |
557 | #define __NR_linkat (__NR_Linux + 255) |
558 | @@ -614,16 +616,18 @@ |
559 | #define __NR_tee (__NR_Linux + 265) |
560 | #define __NR_vmsplice (__NR_Linux + 266) |
561 | #define __NR_move_pages (__NR_Linux + 267) |
562 | +#define __NR_set_robust_list (__NR_Linux + 268) |
563 | +#define __NR_get_robust_list (__NR_Linux + 269) |
564 | |
565 | /* |
566 | * Offset of the last Linux 64-bit flavoured syscall |
567 | */ |
568 | -#define __NR_Linux_syscalls 267 |
569 | +#define __NR_Linux_syscalls 269 |
570 | |
571 | #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */ |
572 | |
573 | #define __NR_64_Linux 5000 |
574 | -#define __NR_64_Linux_syscalls 267 |
575 | +#define __NR_64_Linux_syscalls 269 |
576 | |
577 | #if _MIPS_SIM == _MIPS_SIM_NABI32 |
578 | |
579 | @@ -887,7 +891,7 @@ |
580 | #define __NR_mknodat (__NR_Linux + 253) |
581 | #define __NR_fchownat (__NR_Linux + 254) |
582 | #define __NR_futimesat (__NR_Linux + 255) |
583 | -#define __NR_fstatat (__NR_Linux + 256) |
584 | +#define __NR_newfstatat (__NR_Linux + 256) |
585 | #define __NR_unlinkat (__NR_Linux + 257) |
586 | #define __NR_renameat (__NR_Linux + 258) |
587 | #define __NR_linkat (__NR_Linux + 259) |
588 | @@ -903,16 +907,18 @@ |
589 | #define __NR_tee (__NR_Linux + 269) |
590 | #define __NR_vmsplice (__NR_Linux + 270) |
591 | #define __NR_move_pages (__NR_Linux + 271) |
592 | +#define __NR_set_robust_list (__NR_Linux + 272) |
593 | +#define __NR_get_robust_list (__NR_Linux + 273) |
594 | |
595 | /* |
596 | * Offset of the last N32 flavoured syscall |
597 | */ |
598 | -#define __NR_Linux_syscalls 271 |
599 | +#define __NR_Linux_syscalls 273 |
600 | |
601 | #endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */ |
602 | |
603 | #define __NR_N32_Linux 6000 |
604 | -#define __NR_N32_Linux_syscalls 271 |
605 | +#define __NR_N32_Linux_syscalls 273 |
606 | |
607 | #ifdef __KERNEL__ |
608 | |
609 | diff -Naur linux-2.6.18.2.orig/include/asm-mips/user.h linux-2.6.18.2/include/asm-mips/user.h |
610 | --- linux-2.6.18.2.orig/include/asm-mips/user.h 2006-11-03 17:33:58.000000000 -0800 |
611 | +++ linux-2.6.18.2/include/asm-mips/user.h 2006-11-04 14:51:12.000000000 -0800 |
612 | @@ -8,6 +8,8 @@ |
613 | #ifndef _ASM_USER_H |
614 | #define _ASM_USER_H |
615 | |
616 | +#ifdef __KERNEL__ |
617 | + |
618 | #include <asm/page.h> |
619 | #include <asm/reg.h> |
620 | |
621 | @@ -55,4 +57,6 @@ |
622 | #define HOST_DATA_START_ADDR (u.start_data) |
623 | #define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG) |
624 | |
625 | +#endif /* __KERNEL__ */ |
626 | + |
627 | #endif /* _ASM_USER_H */ |