Annotation of /trunk/linux-libc-headers/patches/linux-2.6.18.3-mips_headers-1.patch
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Revision 435 -
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Fri Mar 16 00:06:55 2007 UTC (17 years, 2 months ago) by niro
File size: 4281 byte(s)
Fri Mar 16 00:06:55 2007 UTC (17 years, 2 months ago) by niro
File size: 4281 byte(s)
updated to upstream svn-149
| 1 | niro | 435 | diff -Naur linux-2.6.18.3/include/asm-mips/io.h linux-mips-2.6.18.3/include/asm-mips/io.h |
| 2 | --- linux-2.6.18.3/include/asm-mips/io.h 2006-11-20 22:14:59.000000000 -0800 | ||
| 3 | +++ linux-mips-2.6.18.3/include/asm-mips/io.h 2006-11-20 10:09:08.000000000 -0800 | ||
| 4 | @@ -518,34 +518,6 @@ | ||
| 5 | } | ||
| 6 | |||
| 7 | /* | ||
| 8 | - * Memory Mapped I/O | ||
| 9 | - */ | ||
| 10 | -#define ioread8(addr) readb(addr) | ||
| 11 | -#define ioread16(addr) readw(addr) | ||
| 12 | -#define ioread32(addr) readl(addr) | ||
| 13 | - | ||
| 14 | -#define iowrite8(b,addr) writeb(b,addr) | ||
| 15 | -#define iowrite16(w,addr) writew(w,addr) | ||
| 16 | -#define iowrite32(l,addr) writel(l,addr) | ||
| 17 | - | ||
| 18 | -#define ioread8_rep(a,b,c) readsb(a,b,c) | ||
| 19 | -#define ioread16_rep(a,b,c) readsw(a,b,c) | ||
| 20 | -#define ioread32_rep(a,b,c) readsl(a,b,c) | ||
| 21 | - | ||
| 22 | -#define iowrite8_rep(a,b,c) writesb(a,b,c) | ||
| 23 | -#define iowrite16_rep(a,b,c) writesw(a,b,c) | ||
| 24 | -#define iowrite32_rep(a,b,c) writesl(a,b,c) | ||
| 25 | - | ||
| 26 | -/* Create a virtual mapping cookie for an IO port range */ | ||
| 27 | -extern void __iomem *ioport_map(unsigned long port, unsigned int nr); | ||
| 28 | -extern void ioport_unmap(void __iomem *); | ||
| 29 | - | ||
| 30 | -/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */ | ||
| 31 | -struct pci_dev; | ||
| 32 | -extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max); | ||
| 33 | -extern void pci_iounmap(struct pci_dev *dev, void __iomem *); | ||
| 34 | - | ||
| 35 | -/* | ||
| 36 | * ISA space is 'always mapped' on currently supported MIPS systems, no need | ||
| 37 | * to explicitly ioremap() it. The fact that the ISA IO space is mapped | ||
| 38 | * to PAGE_OFFSET is pure coincidence - it does not mean ISA values | ||
| 39 | diff -Naur linux-2.6.18.3/include/asm-mips/mach-cobalt/ide.h linux-mips-2.6.18.3/include/asm-mips/mach-cobalt/ide.h | ||
| 40 | --- linux-2.6.18.3/include/asm-mips/mach-cobalt/ide.h 2006-11-20 22:14:59.000000000 -0800 | ||
| 41 | +++ linux-mips-2.6.18.3/include/asm-mips/mach-cobalt/ide.h 1969-12-31 16:00:00.000000000 -0800 | ||
| 42 | @@ -1,83 +0,0 @@ | ||
| 43 | - | ||
| 44 | -/* | ||
| 45 | - * PIO "in" transfers can cause D-cache lines to be allocated | ||
| 46 | - * to the data being read. If the target is the page cache then | ||
| 47 | - * the kernel can create a user space mapping of the same page | ||
| 48 | - * without flushing it from the D-cache. This has large potential | ||
| 49 | - * to create cache aliases. The Cobalts seem to trigger this | ||
| 50 | - * problem easily. | ||
| 51 | - * | ||
| 52 | - * MIPs doesn't have a flush_dcache_range() so we roll | ||
| 53 | - * our own. | ||
| 54 | - * | ||
| 55 | - * -- pdh | ||
| 56 | - */ | ||
| 57 | - | ||
| 58 | -#define MAX_HWIFS 2 | ||
| 59 | - | ||
| 60 | -#include <asm/r4kcache.h> | ||
| 61 | - | ||
| 62 | -static inline void __flush_dcache(void) | ||
| 63 | -{ | ||
| 64 | - unsigned long dc_size, dc_line, addr, end; | ||
| 65 | - | ||
| 66 | - dc_size = current_cpu_data.dcache.ways << current_cpu_data.dcache.waybit; | ||
| 67 | - dc_line = current_cpu_data.dcache.linesz; | ||
| 68 | - | ||
| 69 | - addr = CKSEG0; | ||
| 70 | - end = addr + dc_size; | ||
| 71 | - | ||
| 72 | - for (; addr < end; addr += dc_line) | ||
| 73 | - flush_dcache_line_indexed(addr); | ||
| 74 | -} | ||
| 75 | - | ||
| 76 | -static inline void __flush_dcache_range(unsigned long start, unsigned long end) | ||
| 77 | -{ | ||
| 78 | - unsigned long dc_size, dc_line, addr; | ||
| 79 | - | ||
| 80 | - dc_size = current_cpu_data.dcache.ways << current_cpu_data.dcache.waybit; | ||
| 81 | - dc_line = current_cpu_data.dcache.linesz; | ||
| 82 | - | ||
| 83 | - addr = start & ~(dc_line - 1); | ||
| 84 | - end += dc_line - 1; | ||
| 85 | - | ||
| 86 | - if (end - addr < dc_size) | ||
| 87 | - for (; addr < end; addr += dc_line) | ||
| 88 | - flush_dcache_line(addr); | ||
| 89 | - else | ||
| 90 | - __flush_dcache(); | ||
| 91 | -} | ||
| 92 | - | ||
| 93 | -static inline void __ide_insw(unsigned long port, void *addr, unsigned int count) | ||
| 94 | -{ | ||
| 95 | - insw(port, addr, count); | ||
| 96 | - | ||
| 97 | - __flush_dcache_range((unsigned long) addr, (unsigned long) addr + count * 2); | ||
| 98 | -} | ||
| 99 | - | ||
| 100 | -static inline void __ide_insl(unsigned long port, void *addr, unsigned int count) | ||
| 101 | -{ | ||
| 102 | - insl(port, addr, count); | ||
| 103 | - | ||
| 104 | - __flush_dcache_range((unsigned long) addr, (unsigned long) addr + count * 4); | ||
| 105 | -} | ||
| 106 | - | ||
| 107 | -static inline void __ide_mm_insw(volatile void __iomem *port, void *addr, unsigned int count) | ||
| 108 | -{ | ||
| 109 | - readsw(port, addr, count); | ||
| 110 | - | ||
| 111 | - __flush_dcache_range((unsigned long) addr, (unsigned long) addr + count * 2); | ||
| 112 | -} | ||
| 113 | - | ||
| 114 | -static inline void __ide_mm_insl(volatile void __iomem *port, void *addr, unsigned int count) | ||
| 115 | -{ | ||
| 116 | - readsl(port, addr, count); | ||
| 117 | - | ||
| 118 | - __flush_dcache_range((unsigned long) addr, (unsigned long) addr + count * 4); | ||
| 119 | -} | ||
| 120 | - | ||
| 121 | -#define insw __ide_insw | ||
| 122 | -#define insl __ide_insl | ||
| 123 | - | ||
| 124 | -#define __ide_mm_outsw writesw | ||
| 125 | -#define __ide_mm_outsl writesl |