diff -Naur linux-2.6.18.3/include/asm-mips/io.h linux-mips-2.6.18.3/include/asm-mips/io.h
--- linux-2.6.18.3/include/asm-mips/io.h	2006-11-20 22:14:59.000000000 -0800
+++ linux-mips-2.6.18.3/include/asm-mips/io.h	2006-11-20 10:09:08.000000000 -0800
@@ -518,34 +518,6 @@
 }
 
 /*
- * Memory Mapped I/O
- */
-#define ioread8(addr)          readb(addr)
-#define ioread16(addr)         readw(addr)
-#define ioread32(addr)         readl(addr)
-
-#define iowrite8(b,addr)       writeb(b,addr)
-#define iowrite16(w,addr)      writew(w,addr)
-#define iowrite32(l,addr)      writel(l,addr)
-
-#define ioread8_rep(a,b,c)     readsb(a,b,c)
-#define ioread16_rep(a,b,c)    readsw(a,b,c)
-#define ioread32_rep(a,b,c)    readsl(a,b,c)
-
-#define iowrite8_rep(a,b,c)    writesb(a,b,c)
-#define iowrite16_rep(a,b,c)   writesw(a,b,c)
-#define iowrite32_rep(a,b,c)   writesl(a,b,c)
-
-/* Create a virtual mapping cookie for an IO port range */
-extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
-extern void ioport_unmap(void __iomem *);
-
-/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
-struct pci_dev;
-extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
-extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
-
-/*
  * ISA space is 'always mapped' on currently supported MIPS systems, no need
  * to explicitly ioremap() it. The fact that the ISA IO space is mapped
  * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
diff -Naur linux-2.6.18.3/include/asm-mips/mach-cobalt/ide.h linux-mips-2.6.18.3/include/asm-mips/mach-cobalt/ide.h
--- linux-2.6.18.3/include/asm-mips/mach-cobalt/ide.h	2006-11-20 22:14:59.000000000 -0800
+++ linux-mips-2.6.18.3/include/asm-mips/mach-cobalt/ide.h	1969-12-31 16:00:00.000000000 -0800
@@ -1,83 +0,0 @@
-
-/*
- * PIO "in" transfers can cause D-cache lines to be allocated
- * to the data being read. If the target is the page cache then
- * the kernel can create a user space mapping of the same page
- * without flushing it from the D-cache. This has large potential
- * to create cache aliases. The Cobalts seem to trigger this
- * problem easily.
- *
- * MIPs doesn't have a flush_dcache_range() so we roll
- * our own.
- *
- * -- pdh
- */
-
-#define MAX_HWIFS                      2
-
-#include <asm/r4kcache.h>
-
-static inline void __flush_dcache(void)
-{
-       unsigned long dc_size, dc_line, addr, end;
-
-       dc_size = current_cpu_data.dcache.ways << current_cpu_data.dcache.waybit;
-       dc_line = current_cpu_data.dcache.linesz;
-
-       addr = CKSEG0;
-       end = addr + dc_size;
-
-       for (; addr < end; addr += dc_line)
-               flush_dcache_line_indexed(addr);
-}
-
-static inline void __flush_dcache_range(unsigned long start, unsigned long end)
-{
-       unsigned long dc_size, dc_line, addr;
-
-       dc_size = current_cpu_data.dcache.ways << current_cpu_data.dcache.waybit;
-       dc_line = current_cpu_data.dcache.linesz;
-
-       addr = start & ~(dc_line - 1);
-       end += dc_line - 1;
-
-       if (end - addr < dc_size)
-               for (; addr < end; addr += dc_line)
-                       flush_dcache_line(addr);
-       else
-               __flush_dcache();
-}
-
-static inline void __ide_insw(unsigned long port, void *addr, unsigned int count)
-{
-       insw(port, addr, count);
-
-       __flush_dcache_range((unsigned long) addr, (unsigned long) addr + count * 2);
-}
-
-static inline void __ide_insl(unsigned long port, void *addr, unsigned int count)
-{
-       insl(port, addr, count);
-
-       __flush_dcache_range((unsigned long) addr, (unsigned long) addr + count * 4);
-}
-
-static inline void __ide_mm_insw(volatile void __iomem *port, void *addr, unsigned int count)
-{
-       readsw(port, addr, count);
-
-       __flush_dcache_range((unsigned long) addr, (unsigned long) addr + count * 2);
-}
-
-static inline void __ide_mm_insl(volatile void __iomem *port, void *addr, unsigned int count)
-{
-       readsl(port, addr, count);
-
-       __flush_dcache_range((unsigned long) addr, (unsigned long) addr + count * 4);
-}
-
-#define insw                   __ide_insw
-#define insl                   __ide_insl
-
-#define __ide_mm_outsw         writesw
-#define __ide_mm_outsl         writesl