Annotation of /trunk/linux-libc-headers/patches/linux-2.6.21.1-mips_headers-1.patch
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Revision 642 -
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Tue Dec 18 00:23:39 2007 UTC (16 years, 9 months ago) by niro
File size: 4168 byte(s)
Tue Dec 18 00:23:39 2007 UTC (16 years, 9 months ago) by niro
File size: 4168 byte(s)
-synced with upstream
1 | niro | 642 | diff -Naur linux-2.6.21.1/include/asm-mips/addrspace.h linux-mips-2.6.21.1/include/asm-mips/addrspace.h |
2 | --- linux-2.6.21.1/include/asm-mips/addrspace.h 2007-04-27 14:49:26.000000000 -0700 | ||
3 | +++ linux-mips-2.6.21.1/include/asm-mips/addrspace.h 2007-04-30 08:27:20.000000000 -0700 | ||
4 | @@ -133,6 +133,7 @@ | ||
5 | || defined (CONFIG_CPU_R4X00) \ | ||
6 | || defined (CONFIG_CPU_R5000) \ | ||
7 | || defined (CONFIG_CPU_RM7000) \ | ||
8 | + || defined (CONFIG_CPU_RM9000) \ | ||
9 | || defined (CONFIG_CPU_NEVADA) \ | ||
10 | || defined (CONFIG_CPU_TX49XX) \ | ||
11 | || defined (CONFIG_CPU_MIPS64) | ||
12 | diff -Naur linux-2.6.21.1/include/asm-mips/mach-cobalt/ide.h linux-mips-2.6.21.1/include/asm-mips/mach-cobalt/ide.h | ||
13 | --- linux-2.6.21.1/include/asm-mips/mach-cobalt/ide.h 1969-12-31 16:00:00.000000000 -0800 | ||
14 | +++ linux-mips-2.6.21.1/include/asm-mips/mach-cobalt/ide.h 2007-05-05 22:24:37.000000000 -0700 | ||
15 | @@ -0,0 +1,83 @@ | ||
16 | + | ||
17 | +/* | ||
18 | + * PIO "in" transfers can cause D-cache lines to be allocated | ||
19 | + * to the data being read. If the target is the page cache then | ||
20 | + * the kernel can create a user space mapping of the same page | ||
21 | + * without flushing it from the D-cache. This has large potential | ||
22 | + * to create cache aliases. The Cobalts seem to trigger this | ||
23 | + * problem easily. | ||
24 | + * | ||
25 | + * MIPs doesn't have a flush_dcache_range() so we roll | ||
26 | + * our own. | ||
27 | + * | ||
28 | + * -- pdh | ||
29 | + */ | ||
30 | + | ||
31 | +#define MAX_HWIFS 2 | ||
32 | + | ||
33 | +#include <asm/r4kcache.h> | ||
34 | + | ||
35 | +static inline void __flush_dcache(void) | ||
36 | +{ | ||
37 | + unsigned long dc_size, dc_line, addr, end; | ||
38 | + | ||
39 | + dc_size = current_cpu_data.dcache.ways << current_cpu_data.dcache.waybit; | ||
40 | + dc_line = current_cpu_data.dcache.linesz; | ||
41 | + | ||
42 | + addr = CKSEG0; | ||
43 | + end = addr + dc_size; | ||
44 | + | ||
45 | + for (; addr < end; addr += dc_line) | ||
46 | + flush_dcache_line_indexed(addr); | ||
47 | +} | ||
48 | + | ||
49 | +static inline void __flush_dcache_range(unsigned long start, unsigned long end) | ||
50 | +{ | ||
51 | + unsigned long dc_size, dc_line, addr; | ||
52 | + | ||
53 | + dc_size = current_cpu_data.dcache.ways << current_cpu_data.dcache.waybit; | ||
54 | + dc_line = current_cpu_data.dcache.linesz; | ||
55 | + | ||
56 | + addr = start & ~(dc_line - 1); | ||
57 | + end += dc_line - 1; | ||
58 | + | ||
59 | + if (end - addr < dc_size) | ||
60 | + for (; addr < end; addr += dc_line) | ||
61 | + flush_dcache_line(addr); | ||
62 | + else | ||
63 | + __flush_dcache(); | ||
64 | +} | ||
65 | + | ||
66 | +static inline void __ide_insw(unsigned long port, void *addr, unsigned int count) | ||
67 | +{ | ||
68 | + insw(port, addr, count); | ||
69 | + | ||
70 | + __flush_dcache_range((unsigned long) addr, (unsigned long) addr + count * 2); | ||
71 | +} | ||
72 | + | ||
73 | +static inline void __ide_insl(unsigned long port, void *addr, unsigned int count) | ||
74 | +{ | ||
75 | + insl(port, addr, count); | ||
76 | + | ||
77 | + __flush_dcache_range((unsigned long) addr, (unsigned long) addr + count * 4); | ||
78 | +} | ||
79 | + | ||
80 | +static inline void __ide_mm_insw(volatile void __iomem *port, void *addr, unsigned int count) | ||
81 | +{ | ||
82 | + readsw(port, addr, count); | ||
83 | + | ||
84 | + __flush_dcache_range((unsigned long) addr, (unsigned long) addr + count * 2); | ||
85 | +} | ||
86 | + | ||
87 | +static inline void __ide_mm_insl(volatile void __iomem *port, void *addr, unsigned int count) | ||
88 | +{ | ||
89 | + readsl(port, addr, count); | ||
90 | + | ||
91 | + __flush_dcache_range((unsigned long) addr, (unsigned long) addr + count * 4); | ||
92 | +} | ||
93 | + | ||
94 | +#define insw __ide_insw | ||
95 | +#define insl __ide_insl | ||
96 | + | ||
97 | +#define __ide_mm_outsw writesw | ||
98 | +#define __ide_mm_outsl writesl | ||
99 | diff -Naur linux-2.6.21.1/include/asm-mips/mach-generic/ide.h linux-mips-2.6.21.1/include/asm-mips/mach-generic/ide.h | ||
100 | --- linux-2.6.21.1/include/asm-mips/mach-generic/ide.h 2007-04-27 14:49:26.000000000 -0700 | ||
101 | +++ linux-mips-2.6.21.1/include/asm-mips/mach-generic/ide.h 2007-04-30 08:27:20.000000000 -0700 | ||
102 | @@ -29,17 +29,12 @@ | ||
103 | |||
104 | #define IDE_ARCH_OBSOLETE_DEFAULTS | ||
105 | |||
106 | +extern int mips_system_has_legacy_ide; | ||
107 | + | ||
108 | static __inline__ int ide_probe_legacy(void) | ||
109 | { | ||
110 | #ifdef CONFIG_PCI | ||
111 | - struct pci_dev *dev; | ||
112 | - if ((dev = pci_get_class(PCI_CLASS_BRIDGE_EISA << 8, NULL)) != NULL || | ||
113 | - (dev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL)) != NULL) { | ||
114 | - pci_dev_put(dev); | ||
115 | - | ||
116 | - return 1; | ||
117 | - } | ||
118 | - return 0; | ||
119 | + return mips_system_has_legacy_ide; | ||
120 | #elif defined(CONFIG_EISA) || defined(CONFIG_ISA) | ||
121 | return 1; | ||
122 | #else |