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    Contents of /trunk/gcc/patches/gcc-4.7.2-texinfo5.patch

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    Revision 2112 - (show annotations) (download)
    Tue Mar 12 14:30:43 2013 UTC (11 years, 2 months ago) by niro
    File size: 6775 byte(s) 
    -added fix for texinfo-5
    1 diff -ur gcc-4.7.2.orig/gcc/doc/cppopts.texi gcc-4.7.2/gcc/doc/cppopts.texi
    2 --- gcc-4.7.2.orig/gcc/doc/cppopts.texi 2011-12-20 21:44:13.000000000 +0100
    3 +++ gcc-4.7.2/gcc/doc/cppopts.texi 2013-02-28 20:47:22.345119293 +0100
    4 @@ -803,7 +803,7 @@
    5 Enable special code to work around file systems which only permit very
    6 short file names, such as MS-DOS@.
    7
    8 -@itemx --help
    9 +@item --help
    10 @itemx --target-help
    11 @opindex help
    12 @opindex target-help
    13 diff -ur gcc-4.7.2.orig/gcc/doc/generic.texi gcc-4.7.2/gcc/doc/generic.texi
    14 --- gcc-4.7.2.orig/gcc/doc/generic.texi 2011-12-23 23:07:16.000000000 +0100
    15 +++ gcc-4.7.2/gcc/doc/generic.texi 2013-02-28 20:58:14.832237335 +0100
    16 @@ -1415,13 +1415,13 @@
    17 not matter. The type of the operands and that of the result are
    18 always of @code{BOOLEAN_TYPE} or @code{INTEGER_TYPE}.
    19
    20 -@itemx POINTER_PLUS_EXPR
    21 +@item POINTER_PLUS_EXPR
    22 This node represents pointer arithmetic. The first operand is always
    23 a pointer/reference type. The second operand is always an unsigned
    24 integer type compatible with sizetype. This is the only binary
    25 arithmetic operand that can operate on pointer types.
    26
    27 -@itemx PLUS_EXPR
    28 +@item PLUS_EXPR
    29 @itemx MINUS_EXPR
    30 @itemx MULT_EXPR
    31 These nodes represent various binary arithmetic operations.
    32 diff -ur gcc-4.7.2.orig/gcc/doc/invoke.texi gcc-4.7.2/gcc/doc/invoke.texi
    33 --- gcc-4.7.2.orig/gcc/doc/invoke.texi 2012-09-14 22:45:27.000000000 +0200
    34 +++ gcc-4.7.2/gcc/doc/invoke.texi 2013-02-28 21:09:17.702266972 +0100
    35 @@ -5179,7 +5179,7 @@
    36 e.g. With -fdbg-cnt=dce:10,tail_call:0
    37 dbg_cnt(dce) will return true only for first 10 invocations
    38
    39 -@itemx -fenable-@var{kind}-@var{pass}
    40 +@item -fenable-@var{kind}-@var{pass}
    41 @itemx -fdisable-@var{kind}-@var{pass}=@var{range-list}
    42 @opindex fdisable-
    43 @opindex fenable-
    44 @@ -5327,11 +5327,11 @@
    45 @option{-fdump-rtl-ce3} enable dumping after the three
    46 if conversion passes.
    47
    48 -@itemx -fdump-rtl-cprop_hardreg
    49 +@item -fdump-rtl-cprop_hardreg
    50 @opindex fdump-rtl-cprop_hardreg
    51 Dump after hard register copy propagation.
    52
    53 -@itemx -fdump-rtl-csa
    54 +@item -fdump-rtl-csa
    55 @opindex fdump-rtl-csa
    56 Dump after combining stack adjustments.
    57
    58 @@ -5342,11 +5342,11 @@
    59 @option{-fdump-rtl-cse1} and @option{-fdump-rtl-cse2} enable dumping after
    60 the two common sub-expression elimination passes.
    61
    62 -@itemx -fdump-rtl-dce
    63 +@item -fdump-rtl-dce
    64 @opindex fdump-rtl-dce
    65 Dump after the standalone dead code elimination passes.
    66
    67 -@itemx -fdump-rtl-dbr
    68 +@item -fdump-rtl-dbr
    69 @opindex fdump-rtl-dbr
    70 Dump after delayed branch scheduling.
    71
    72 @@ -5391,7 +5391,7 @@
    73 @opindex fdump-rtl-initvals
    74 Dump after the computation of the initial value sets.
    75
    76 -@itemx -fdump-rtl-into_cfglayout
    77 +@item -fdump-rtl-into_cfglayout
    78 @opindex fdump-rtl-into_cfglayout
    79 Dump after converting to cfglayout mode.
    80
    81 @@ -5421,7 +5421,7 @@
    82 @opindex fdump-rtl-rnreg
    83 Dump after register renumbering.
    84
    85 -@itemx -fdump-rtl-outof_cfglayout
    86 +@item -fdump-rtl-outof_cfglayout
    87 @opindex fdump-rtl-outof_cfglayout
    88 Dump after converting from cfglayout mode.
    89
    90 @@ -5433,7 +5433,7 @@
    91 @opindex fdump-rtl-postreload
    92 Dump after post-reload optimizations.
    93
    94 -@itemx -fdump-rtl-pro_and_epilogue
    95 +@item -fdump-rtl-pro_and_epilogue
    96 @opindex fdump-rtl-pro_and_epilogue
    97 Dump after generating the function prologues and epilogues.
    98
    99 @@ -10494,10 +10494,10 @@
    100 The default is @option{-mfp-mode=caller}
    101
    102 @item -mnosplit-lohi
    103 +@itemx -mno-postinc
    104 +@itemx -mno-postmodify
    105 @opindex mnosplit-lohi
    106 -@item -mno-postinc
    107 @opindex mno-postinc
    108 -@item -mno-postmodify
    109 @opindex mno-postmodify
    110 Code generation tweaks that disable, respectively, splitting of 32-bit
    111 loads, generation of post-increment addresses, and generation of
    112 @@ -11409,7 +11409,7 @@
    113 memory and if @code{-mshort-calls} is not set.
    114
    115 @item __AVR_HAVE_EIJMP_EICALL__
    116 -@item __AVR_3_BYTE_PC__
    117 +@itemx __AVR_3_BYTE_PC__
    118 The device has the @code{EIJMP} and @code{EICALL} instructions.
    119 This is the case for devices with more than 128@tie{}KiB of program memory.
    120 This also means that the program counter
    121 @@ -11420,13 +11420,13 @@
    122 with up to 128@tie{}KiB of program memory.
    123
    124 @item __AVR_HAVE_8BIT_SP__
    125 -@item __AVR_HAVE_16BIT_SP__
    126 +@itemx __AVR_HAVE_16BIT_SP__
    127 The stack pointer (SP) register is treated as 8-bit respectively
    128 16-bit register by the compiler.
    129 The definition of these macros is affected by @code{-mtiny-stack}.
    130
    131 @item __AVR_HAVE_SPH__
    132 -@item __AVR_SP8__
    133 +@itemx __AVR_SP8__
    134 The device has the SPH (high part of stack pointer) special function
    135 register or has an 8-bit stack pointer, respectively.
    136 The definition of these macros is affected by @code{-mmcu=} and
    137 @@ -11434,9 +11434,9 @@
    138 by @code{-msp8}.
    139
    140 @item __AVR_HAVE_RAMPD__
    141 -@item __AVR_HAVE_RAMPX__
    142 -@item __AVR_HAVE_RAMPY__
    143 -@item __AVR_HAVE_RAMPZ__
    144 +@itemx __AVR_HAVE_RAMPX__
    145 +@itemx __AVR_HAVE_RAMPY__
    146 +@itemx __AVR_HAVE_RAMPZ__
    147 The device has the @code{RAMPD}, @code{RAMPX}, @code{RAMPY},
    148 @code{RAMPZ} special function register, respectively.
    149
    150 @@ -11444,7 +11444,7 @@
    151 This macro reflects the @code{-mno-interrupts} command line option.
    152
    153 @item __AVR_ERRATA_SKIP__
    154 -@item __AVR_ERRATA_SKIP_JMP_CALL__
    155 +@itemx __AVR_ERRATA_SKIP_JMP_CALL__
    156 Some AVR devices (AT90S8515, ATmega103) must not skip 32-bit
    157 instructions because of a hardware erratum. Skip instructions are
    158 @code{SBRS}, @code{SBRC}, @code{SBIS}, @code{SBIC} and @code{CPSE}.
    159 @@ -17971,7 +17971,7 @@
    160 @option{-mhitachi} is given.
    161
    162 @item -mieee
    163 -@item -mno-ieee
    164 +@itemx -mno-ieee
    165 @opindex mieee
    166 @opindex mnoieee
    167 Control the IEEE compliance of floating-point comparisons, which affects the
    168 diff -ur gcc-4.7.2.orig/gcc/doc/md.texi gcc-4.7.2/gcc/doc/md.texi
    169 --- gcc-4.7.2.orig/gcc/doc/md.texi 2012-08-27 20:51:44.000000000 +0200
    170 +++ gcc-4.7.2/gcc/doc/md.texi 2013-02-28 21:10:21.882266695 +0100
    171 @@ -4405,8 +4405,8 @@
    172 @cindex @code{ior@var{m}3} instruction pattern
    173 @cindex @code{xor@var{m}3} instruction pattern
    174 @item @samp{ssadd@var{m}3}, @samp{usadd@var{m}3}
    175 -@item @samp{sub@var{m}3}, @samp{sssub@var{m}3}, @samp{ussub@var{m}3}
    176 -@item @samp{mul@var{m}3}, @samp{ssmul@var{m}3}, @samp{usmul@var{m}3}
    177 +@itemx @samp{sub@var{m}3}, @samp{sssub@var{m}3}, @samp{ussub@var{m}3}
    178 +@itemx @samp{mul@var{m}3}, @samp{ssmul@var{m}3}, @samp{usmul@var{m}3}
    179 @itemx @samp{div@var{m}3}, @samp{ssdiv@var{m}3}
    180 @itemx @samp{udiv@var{m}3}, @samp{usdiv@var{m}3}
    181 @itemx @samp{mod@var{m}3}, @samp{umod@var{m}3}
    182 diff -ur gcc-4.7.2.orig/gcc/doc/sourcebuild.texi gcc-4.7.2/gcc/doc/sourcebuild.texi
    183 --- gcc-4.7.2.orig/gcc/doc/sourcebuild.texi 2011-07-25 18:44:22.000000000 +0200
    184 +++ gcc-4.7.2/gcc/doc/sourcebuild.texi 2013-02-28 21:10:44.042264211 +0100
    185 @@ -676,7 +676,7 @@
    186 @code{lang_checks}.
    187
    188 @table @code
    189 -@itemx all.cross
    190 +@item all.cross
    191 @itemx start.encap
    192 @itemx rest.encap
    193 FIXME: exactly what goes in each of these targets?