Annotation of /trunk/kernel-alx/patches-4.14/0145-4.14.46-all-fixes.patch
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Revision 3238 -
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Fri Nov 9 12:14:58 2018 UTC (5 years, 10 months ago) by niro
File size: 49971 byte(s)
Fri Nov 9 12:14:58 2018 UTC (5 years, 10 months ago) by niro
File size: 49971 byte(s)
-added up to patches-4.14.79
1 | niro | 3238 | diff --git a/Makefile b/Makefile |
2 | index f3ea74e7a516..3b1845f2b8f8 100644 | ||
3 | --- a/Makefile | ||
4 | +++ b/Makefile | ||
5 | @@ -1,7 +1,7 @@ | ||
6 | # SPDX-License-Identifier: GPL-2.0 | ||
7 | VERSION = 4 | ||
8 | PATCHLEVEL = 14 | ||
9 | -SUBLEVEL = 45 | ||
10 | +SUBLEVEL = 46 | ||
11 | EXTRAVERSION = | ||
12 | NAME = Petit Gorille | ||
13 | |||
14 | diff --git a/tools/arch/arm/include/uapi/asm/kvm.h b/tools/arch/arm/include/uapi/asm/kvm.h | ||
15 | index 1f57bbe82b6f..df24fc8da1bc 100644 | ||
16 | --- a/tools/arch/arm/include/uapi/asm/kvm.h | ||
17 | +++ b/tools/arch/arm/include/uapi/asm/kvm.h | ||
18 | @@ -180,6 +180,12 @@ struct kvm_arch_memory_slot { | ||
19 | #define KVM_REG_ARM_VFP_FPINST 0x1009 | ||
20 | #define KVM_REG_ARM_VFP_FPINST2 0x100A | ||
21 | |||
22 | +/* KVM-as-firmware specific pseudo-registers */ | ||
23 | +#define KVM_REG_ARM_FW (0x0014 << KVM_REG_ARM_COPROC_SHIFT) | ||
24 | +#define KVM_REG_ARM_FW_REG(r) (KVM_REG_ARM | KVM_REG_SIZE_U64 | \ | ||
25 | + KVM_REG_ARM_FW | ((r) & 0xffff)) | ||
26 | +#define KVM_REG_ARM_PSCI_VERSION KVM_REG_ARM_FW_REG(0) | ||
27 | + | ||
28 | /* Device Control API: ARM VGIC */ | ||
29 | #define KVM_DEV_ARM_VGIC_GRP_ADDR 0 | ||
30 | #define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1 | ||
31 | diff --git a/tools/arch/arm64/include/uapi/asm/kvm.h b/tools/arch/arm64/include/uapi/asm/kvm.h | ||
32 | index 51149ec75fe4..9f74ce5899f0 100644 | ||
33 | --- a/tools/arch/arm64/include/uapi/asm/kvm.h | ||
34 | +++ b/tools/arch/arm64/include/uapi/asm/kvm.h | ||
35 | @@ -200,6 +200,12 @@ struct kvm_arch_memory_slot { | ||
36 | #define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2) | ||
37 | #define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2) | ||
38 | |||
39 | +/* KVM-as-firmware specific pseudo-registers */ | ||
40 | +#define KVM_REG_ARM_FW (0x0014 << KVM_REG_ARM_COPROC_SHIFT) | ||
41 | +#define KVM_REG_ARM_FW_REG(r) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \ | ||
42 | + KVM_REG_ARM_FW | ((r) & 0xffff)) | ||
43 | +#define KVM_REG_ARM_PSCI_VERSION KVM_REG_ARM_FW_REG(0) | ||
44 | + | ||
45 | /* Device Control API: ARM VGIC */ | ||
46 | #define KVM_DEV_ARM_VGIC_GRP_ADDR 0 | ||
47 | #define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1 | ||
48 | diff --git a/tools/arch/powerpc/include/uapi/asm/kvm.h b/tools/arch/powerpc/include/uapi/asm/kvm.h | ||
49 | index 61d6049f4c1e..8aaec831053a 100644 | ||
50 | --- a/tools/arch/powerpc/include/uapi/asm/kvm.h | ||
51 | +++ b/tools/arch/powerpc/include/uapi/asm/kvm.h | ||
52 | @@ -607,6 +607,8 @@ struct kvm_ppc_rmmu_info { | ||
53 | #define KVM_REG_PPC_TIDR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xbc) | ||
54 | #define KVM_REG_PPC_PSSCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xbd) | ||
55 | |||
56 | +#define KVM_REG_PPC_DEC_EXPIRY (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xbe) | ||
57 | + | ||
58 | /* Transactional Memory checkpointed state: | ||
59 | * This is all GPRs, all VSX regs and a subset of SPRs | ||
60 | */ | ||
61 | diff --git a/tools/arch/s390/include/uapi/asm/kvm.h b/tools/arch/s390/include/uapi/asm/kvm.h | ||
62 | index 9ad172dcd912..a3938db010f7 100644 | ||
63 | --- a/tools/arch/s390/include/uapi/asm/kvm.h | ||
64 | +++ b/tools/arch/s390/include/uapi/asm/kvm.h | ||
65 | @@ -228,6 +228,7 @@ struct kvm_guest_debug_arch { | ||
66 | #define KVM_SYNC_RICCB (1UL << 7) | ||
67 | #define KVM_SYNC_FPRS (1UL << 8) | ||
68 | #define KVM_SYNC_GSCB (1UL << 9) | ||
69 | +#define KVM_SYNC_BPBC (1UL << 10) | ||
70 | /* length and alignment of the sdnx as a power of two */ | ||
71 | #define SDNXC 8 | ||
72 | #define SDNXL (1UL << SDNXC) | ||
73 | @@ -251,7 +252,9 @@ struct kvm_sync_regs { | ||
74 | }; | ||
75 | __u8 reserved[512]; /* for future vector expansion */ | ||
76 | __u32 fpc; /* valid on KVM_SYNC_VRS or KVM_SYNC_FPRS */ | ||
77 | - __u8 padding1[52]; /* riccb needs to be 64byte aligned */ | ||
78 | + __u8 bpbc : 1; /* bp mode */ | ||
79 | + __u8 reserved2 : 7; | ||
80 | + __u8 padding1[51]; /* riccb needs to be 64byte aligned */ | ||
81 | __u8 riccb[64]; /* runtime instrumentation controls block */ | ||
82 | __u8 padding2[192]; /* sdnx needs to be 256byte aligned */ | ||
83 | union { | ||
84 | diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h | ||
85 | index 793690fbda36..403e97d5e243 100644 | ||
86 | --- a/tools/arch/x86/include/asm/cpufeatures.h | ||
87 | +++ b/tools/arch/x86/include/asm/cpufeatures.h | ||
88 | @@ -13,173 +13,176 @@ | ||
89 | /* | ||
90 | * Defines x86 CPU feature bits | ||
91 | */ | ||
92 | -#define NCAPINTS 18 /* N 32-bit words worth of info */ | ||
93 | -#define NBUGINTS 1 /* N 32-bit bug flags */ | ||
94 | +#define NCAPINTS 19 /* N 32-bit words worth of info */ | ||
95 | +#define NBUGINTS 1 /* N 32-bit bug flags */ | ||
96 | |||
97 | /* | ||
98 | * Note: If the comment begins with a quoted string, that string is used | ||
99 | * in /proc/cpuinfo instead of the macro name. If the string is "", | ||
100 | * this feature bit is not displayed in /proc/cpuinfo at all. | ||
101 | + * | ||
102 | + * When adding new features here that depend on other features, | ||
103 | + * please update the table in kernel/cpu/cpuid-deps.c as well. | ||
104 | */ | ||
105 | |||
106 | -/* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */ | ||
107 | -#define X86_FEATURE_FPU ( 0*32+ 0) /* Onboard FPU */ | ||
108 | -#define X86_FEATURE_VME ( 0*32+ 1) /* Virtual Mode Extensions */ | ||
109 | -#define X86_FEATURE_DE ( 0*32+ 2) /* Debugging Extensions */ | ||
110 | -#define X86_FEATURE_PSE ( 0*32+ 3) /* Page Size Extensions */ | ||
111 | -#define X86_FEATURE_TSC ( 0*32+ 4) /* Time Stamp Counter */ | ||
112 | -#define X86_FEATURE_MSR ( 0*32+ 5) /* Model-Specific Registers */ | ||
113 | -#define X86_FEATURE_PAE ( 0*32+ 6) /* Physical Address Extensions */ | ||
114 | -#define X86_FEATURE_MCE ( 0*32+ 7) /* Machine Check Exception */ | ||
115 | -#define X86_FEATURE_CX8 ( 0*32+ 8) /* CMPXCHG8 instruction */ | ||
116 | -#define X86_FEATURE_APIC ( 0*32+ 9) /* Onboard APIC */ | ||
117 | -#define X86_FEATURE_SEP ( 0*32+11) /* SYSENTER/SYSEXIT */ | ||
118 | -#define X86_FEATURE_MTRR ( 0*32+12) /* Memory Type Range Registers */ | ||
119 | -#define X86_FEATURE_PGE ( 0*32+13) /* Page Global Enable */ | ||
120 | -#define X86_FEATURE_MCA ( 0*32+14) /* Machine Check Architecture */ | ||
121 | -#define X86_FEATURE_CMOV ( 0*32+15) /* CMOV instructions */ | ||
122 | - /* (plus FCMOVcc, FCOMI with FPU) */ | ||
123 | -#define X86_FEATURE_PAT ( 0*32+16) /* Page Attribute Table */ | ||
124 | -#define X86_FEATURE_PSE36 ( 0*32+17) /* 36-bit PSEs */ | ||
125 | -#define X86_FEATURE_PN ( 0*32+18) /* Processor serial number */ | ||
126 | -#define X86_FEATURE_CLFLUSH ( 0*32+19) /* CLFLUSH instruction */ | ||
127 | -#define X86_FEATURE_DS ( 0*32+21) /* "dts" Debug Store */ | ||
128 | -#define X86_FEATURE_ACPI ( 0*32+22) /* ACPI via MSR */ | ||
129 | -#define X86_FEATURE_MMX ( 0*32+23) /* Multimedia Extensions */ | ||
130 | -#define X86_FEATURE_FXSR ( 0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */ | ||
131 | -#define X86_FEATURE_XMM ( 0*32+25) /* "sse" */ | ||
132 | -#define X86_FEATURE_XMM2 ( 0*32+26) /* "sse2" */ | ||
133 | -#define X86_FEATURE_SELFSNOOP ( 0*32+27) /* "ss" CPU self snoop */ | ||
134 | -#define X86_FEATURE_HT ( 0*32+28) /* Hyper-Threading */ | ||
135 | -#define X86_FEATURE_ACC ( 0*32+29) /* "tm" Automatic clock control */ | ||
136 | -#define X86_FEATURE_IA64 ( 0*32+30) /* IA-64 processor */ | ||
137 | -#define X86_FEATURE_PBE ( 0*32+31) /* Pending Break Enable */ | ||
138 | +/* Intel-defined CPU features, CPUID level 0x00000001 (EDX), word 0 */ | ||
139 | +#define X86_FEATURE_FPU ( 0*32+ 0) /* Onboard FPU */ | ||
140 | +#define X86_FEATURE_VME ( 0*32+ 1) /* Virtual Mode Extensions */ | ||
141 | +#define X86_FEATURE_DE ( 0*32+ 2) /* Debugging Extensions */ | ||
142 | +#define X86_FEATURE_PSE ( 0*32+ 3) /* Page Size Extensions */ | ||
143 | +#define X86_FEATURE_TSC ( 0*32+ 4) /* Time Stamp Counter */ | ||
144 | +#define X86_FEATURE_MSR ( 0*32+ 5) /* Model-Specific Registers */ | ||
145 | +#define X86_FEATURE_PAE ( 0*32+ 6) /* Physical Address Extensions */ | ||
146 | +#define X86_FEATURE_MCE ( 0*32+ 7) /* Machine Check Exception */ | ||
147 | +#define X86_FEATURE_CX8 ( 0*32+ 8) /* CMPXCHG8 instruction */ | ||
148 | +#define X86_FEATURE_APIC ( 0*32+ 9) /* Onboard APIC */ | ||
149 | +#define X86_FEATURE_SEP ( 0*32+11) /* SYSENTER/SYSEXIT */ | ||
150 | +#define X86_FEATURE_MTRR ( 0*32+12) /* Memory Type Range Registers */ | ||
151 | +#define X86_FEATURE_PGE ( 0*32+13) /* Page Global Enable */ | ||
152 | +#define X86_FEATURE_MCA ( 0*32+14) /* Machine Check Architecture */ | ||
153 | +#define X86_FEATURE_CMOV ( 0*32+15) /* CMOV instructions (plus FCMOVcc, FCOMI with FPU) */ | ||
154 | +#define X86_FEATURE_PAT ( 0*32+16) /* Page Attribute Table */ | ||
155 | +#define X86_FEATURE_PSE36 ( 0*32+17) /* 36-bit PSEs */ | ||
156 | +#define X86_FEATURE_PN ( 0*32+18) /* Processor serial number */ | ||
157 | +#define X86_FEATURE_CLFLUSH ( 0*32+19) /* CLFLUSH instruction */ | ||
158 | +#define X86_FEATURE_DS ( 0*32+21) /* "dts" Debug Store */ | ||
159 | +#define X86_FEATURE_ACPI ( 0*32+22) /* ACPI via MSR */ | ||
160 | +#define X86_FEATURE_MMX ( 0*32+23) /* Multimedia Extensions */ | ||
161 | +#define X86_FEATURE_FXSR ( 0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */ | ||
162 | +#define X86_FEATURE_XMM ( 0*32+25) /* "sse" */ | ||
163 | +#define X86_FEATURE_XMM2 ( 0*32+26) /* "sse2" */ | ||
164 | +#define X86_FEATURE_SELFSNOOP ( 0*32+27) /* "ss" CPU self snoop */ | ||
165 | +#define X86_FEATURE_HT ( 0*32+28) /* Hyper-Threading */ | ||
166 | +#define X86_FEATURE_ACC ( 0*32+29) /* "tm" Automatic clock control */ | ||
167 | +#define X86_FEATURE_IA64 ( 0*32+30) /* IA-64 processor */ | ||
168 | +#define X86_FEATURE_PBE ( 0*32+31) /* Pending Break Enable */ | ||
169 | |||
170 | /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */ | ||
171 | /* Don't duplicate feature flags which are redundant with Intel! */ | ||
172 | -#define X86_FEATURE_SYSCALL ( 1*32+11) /* SYSCALL/SYSRET */ | ||
173 | -#define X86_FEATURE_MP ( 1*32+19) /* MP Capable. */ | ||
174 | -#define X86_FEATURE_NX ( 1*32+20) /* Execute Disable */ | ||
175 | -#define X86_FEATURE_MMXEXT ( 1*32+22) /* AMD MMX extensions */ | ||
176 | -#define X86_FEATURE_FXSR_OPT ( 1*32+25) /* FXSAVE/FXRSTOR optimizations */ | ||
177 | -#define X86_FEATURE_GBPAGES ( 1*32+26) /* "pdpe1gb" GB pages */ | ||
178 | -#define X86_FEATURE_RDTSCP ( 1*32+27) /* RDTSCP */ | ||
179 | -#define X86_FEATURE_LM ( 1*32+29) /* Long Mode (x86-64) */ | ||
180 | -#define X86_FEATURE_3DNOWEXT ( 1*32+30) /* AMD 3DNow! extensions */ | ||
181 | -#define X86_FEATURE_3DNOW ( 1*32+31) /* 3DNow! */ | ||
182 | +#define X86_FEATURE_SYSCALL ( 1*32+11) /* SYSCALL/SYSRET */ | ||
183 | +#define X86_FEATURE_MP ( 1*32+19) /* MP Capable */ | ||
184 | +#define X86_FEATURE_NX ( 1*32+20) /* Execute Disable */ | ||
185 | +#define X86_FEATURE_MMXEXT ( 1*32+22) /* AMD MMX extensions */ | ||
186 | +#define X86_FEATURE_FXSR_OPT ( 1*32+25) /* FXSAVE/FXRSTOR optimizations */ | ||
187 | +#define X86_FEATURE_GBPAGES ( 1*32+26) /* "pdpe1gb" GB pages */ | ||
188 | +#define X86_FEATURE_RDTSCP ( 1*32+27) /* RDTSCP */ | ||
189 | +#define X86_FEATURE_LM ( 1*32+29) /* Long Mode (x86-64, 64-bit support) */ | ||
190 | +#define X86_FEATURE_3DNOWEXT ( 1*32+30) /* AMD 3DNow extensions */ | ||
191 | +#define X86_FEATURE_3DNOW ( 1*32+31) /* 3DNow */ | ||
192 | |||
193 | /* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */ | ||
194 | -#define X86_FEATURE_RECOVERY ( 2*32+ 0) /* CPU in recovery mode */ | ||
195 | -#define X86_FEATURE_LONGRUN ( 2*32+ 1) /* Longrun power control */ | ||
196 | -#define X86_FEATURE_LRTI ( 2*32+ 3) /* LongRun table interface */ | ||
197 | +#define X86_FEATURE_RECOVERY ( 2*32+ 0) /* CPU in recovery mode */ | ||
198 | +#define X86_FEATURE_LONGRUN ( 2*32+ 1) /* Longrun power control */ | ||
199 | +#define X86_FEATURE_LRTI ( 2*32+ 3) /* LongRun table interface */ | ||
200 | |||
201 | /* Other features, Linux-defined mapping, word 3 */ | ||
202 | /* This range is used for feature bits which conflict or are synthesized */ | ||
203 | -#define X86_FEATURE_CXMMX ( 3*32+ 0) /* Cyrix MMX extensions */ | ||
204 | -#define X86_FEATURE_K6_MTRR ( 3*32+ 1) /* AMD K6 nonstandard MTRRs */ | ||
205 | -#define X86_FEATURE_CYRIX_ARR ( 3*32+ 2) /* Cyrix ARRs (= MTRRs) */ | ||
206 | -#define X86_FEATURE_CENTAUR_MCR ( 3*32+ 3) /* Centaur MCRs (= MTRRs) */ | ||
207 | -/* cpu types for specific tunings: */ | ||
208 | -#define X86_FEATURE_K8 ( 3*32+ 4) /* "" Opteron, Athlon64 */ | ||
209 | -#define X86_FEATURE_K7 ( 3*32+ 5) /* "" Athlon */ | ||
210 | -#define X86_FEATURE_P3 ( 3*32+ 6) /* "" P3 */ | ||
211 | -#define X86_FEATURE_P4 ( 3*32+ 7) /* "" P4 */ | ||
212 | -#define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* TSC ticks at a constant rate */ | ||
213 | -#define X86_FEATURE_UP ( 3*32+ 9) /* smp kernel running on up */ | ||
214 | -#define X86_FEATURE_ART ( 3*32+10) /* Platform has always running timer (ART) */ | ||
215 | -#define X86_FEATURE_ARCH_PERFMON ( 3*32+11) /* Intel Architectural PerfMon */ | ||
216 | -#define X86_FEATURE_PEBS ( 3*32+12) /* Precise-Event Based Sampling */ | ||
217 | -#define X86_FEATURE_BTS ( 3*32+13) /* Branch Trace Store */ | ||
218 | -#define X86_FEATURE_SYSCALL32 ( 3*32+14) /* "" syscall in ia32 userspace */ | ||
219 | -#define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in ia32 userspace */ | ||
220 | -#define X86_FEATURE_REP_GOOD ( 3*32+16) /* rep microcode works well */ | ||
221 | -#define X86_FEATURE_MFENCE_RDTSC ( 3*32+17) /* "" Mfence synchronizes RDTSC */ | ||
222 | -#define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" Lfence synchronizes RDTSC */ | ||
223 | -#define X86_FEATURE_ACC_POWER ( 3*32+19) /* AMD Accumulated Power Mechanism */ | ||
224 | -#define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */ | ||
225 | -#define X86_FEATURE_ALWAYS ( 3*32+21) /* "" Always-present feature */ | ||
226 | -#define X86_FEATURE_XTOPOLOGY ( 3*32+22) /* cpu topology enum extensions */ | ||
227 | -#define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */ | ||
228 | -#define X86_FEATURE_NONSTOP_TSC ( 3*32+24) /* TSC does not stop in C states */ | ||
229 | -#define X86_FEATURE_CPUID ( 3*32+25) /* CPU has CPUID instruction itself */ | ||
230 | -#define X86_FEATURE_EXTD_APICID ( 3*32+26) /* has extended APICID (8 bits) */ | ||
231 | -#define X86_FEATURE_AMD_DCM ( 3*32+27) /* multi-node processor */ | ||
232 | -#define X86_FEATURE_APERFMPERF ( 3*32+28) /* APERFMPERF */ | ||
233 | -#define X86_FEATURE_NONSTOP_TSC_S3 ( 3*32+30) /* TSC doesn't stop in S3 state */ | ||
234 | -#define X86_FEATURE_TSC_KNOWN_FREQ ( 3*32+31) /* TSC has known frequency */ | ||
235 | +#define X86_FEATURE_CXMMX ( 3*32+ 0) /* Cyrix MMX extensions */ | ||
236 | +#define X86_FEATURE_K6_MTRR ( 3*32+ 1) /* AMD K6 nonstandard MTRRs */ | ||
237 | +#define X86_FEATURE_CYRIX_ARR ( 3*32+ 2) /* Cyrix ARRs (= MTRRs) */ | ||
238 | +#define X86_FEATURE_CENTAUR_MCR ( 3*32+ 3) /* Centaur MCRs (= MTRRs) */ | ||
239 | + | ||
240 | +/* CPU types for specific tunings: */ | ||
241 | +#define X86_FEATURE_K8 ( 3*32+ 4) /* "" Opteron, Athlon64 */ | ||
242 | +#define X86_FEATURE_K7 ( 3*32+ 5) /* "" Athlon */ | ||
243 | +#define X86_FEATURE_P3 ( 3*32+ 6) /* "" P3 */ | ||
244 | +#define X86_FEATURE_P4 ( 3*32+ 7) /* "" P4 */ | ||
245 | +#define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* TSC ticks at a constant rate */ | ||
246 | +#define X86_FEATURE_UP ( 3*32+ 9) /* SMP kernel running on UP */ | ||
247 | +#define X86_FEATURE_ART ( 3*32+10) /* Always running timer (ART) */ | ||
248 | +#define X86_FEATURE_ARCH_PERFMON ( 3*32+11) /* Intel Architectural PerfMon */ | ||
249 | +#define X86_FEATURE_PEBS ( 3*32+12) /* Precise-Event Based Sampling */ | ||
250 | +#define X86_FEATURE_BTS ( 3*32+13) /* Branch Trace Store */ | ||
251 | +#define X86_FEATURE_SYSCALL32 ( 3*32+14) /* "" syscall in IA32 userspace */ | ||
252 | +#define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in IA32 userspace */ | ||
253 | +#define X86_FEATURE_REP_GOOD ( 3*32+16) /* REP microcode works well */ | ||
254 | +#define X86_FEATURE_MFENCE_RDTSC ( 3*32+17) /* "" MFENCE synchronizes RDTSC */ | ||
255 | +#define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" LFENCE synchronizes RDTSC */ | ||
256 | +#define X86_FEATURE_ACC_POWER ( 3*32+19) /* AMD Accumulated Power Mechanism */ | ||
257 | +#define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */ | ||
258 | +#define X86_FEATURE_ALWAYS ( 3*32+21) /* "" Always-present feature */ | ||
259 | +#define X86_FEATURE_XTOPOLOGY ( 3*32+22) /* CPU topology enum extensions */ | ||
260 | +#define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */ | ||
261 | +#define X86_FEATURE_NONSTOP_TSC ( 3*32+24) /* TSC does not stop in C states */ | ||
262 | +#define X86_FEATURE_CPUID ( 3*32+25) /* CPU has CPUID instruction itself */ | ||
263 | +#define X86_FEATURE_EXTD_APICID ( 3*32+26) /* Extended APICID (8 bits) */ | ||
264 | +#define X86_FEATURE_AMD_DCM ( 3*32+27) /* AMD multi-node processor */ | ||
265 | +#define X86_FEATURE_APERFMPERF ( 3*32+28) /* P-State hardware coordination feedback capability (APERF/MPERF MSRs) */ | ||
266 | +#define X86_FEATURE_NONSTOP_TSC_S3 ( 3*32+30) /* TSC doesn't stop in S3 state */ | ||
267 | +#define X86_FEATURE_TSC_KNOWN_FREQ ( 3*32+31) /* TSC has known frequency */ | ||
268 | |||
269 | -/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ | ||
270 | -#define X86_FEATURE_XMM3 ( 4*32+ 0) /* "pni" SSE-3 */ | ||
271 | -#define X86_FEATURE_PCLMULQDQ ( 4*32+ 1) /* PCLMULQDQ instruction */ | ||
272 | -#define X86_FEATURE_DTES64 ( 4*32+ 2) /* 64-bit Debug Store */ | ||
273 | -#define X86_FEATURE_MWAIT ( 4*32+ 3) /* "monitor" Monitor/Mwait support */ | ||
274 | -#define X86_FEATURE_DSCPL ( 4*32+ 4) /* "ds_cpl" CPL Qual. Debug Store */ | ||
275 | -#define X86_FEATURE_VMX ( 4*32+ 5) /* Hardware virtualization */ | ||
276 | -#define X86_FEATURE_SMX ( 4*32+ 6) /* Safer mode */ | ||
277 | -#define X86_FEATURE_EST ( 4*32+ 7) /* Enhanced SpeedStep */ | ||
278 | -#define X86_FEATURE_TM2 ( 4*32+ 8) /* Thermal Monitor 2 */ | ||
279 | -#define X86_FEATURE_SSSE3 ( 4*32+ 9) /* Supplemental SSE-3 */ | ||
280 | -#define X86_FEATURE_CID ( 4*32+10) /* Context ID */ | ||
281 | -#define X86_FEATURE_SDBG ( 4*32+11) /* Silicon Debug */ | ||
282 | -#define X86_FEATURE_FMA ( 4*32+12) /* Fused multiply-add */ | ||
283 | -#define X86_FEATURE_CX16 ( 4*32+13) /* CMPXCHG16B */ | ||
284 | -#define X86_FEATURE_XTPR ( 4*32+14) /* Send Task Priority Messages */ | ||
285 | -#define X86_FEATURE_PDCM ( 4*32+15) /* Performance Capabilities */ | ||
286 | -#define X86_FEATURE_PCID ( 4*32+17) /* Process Context Identifiers */ | ||
287 | -#define X86_FEATURE_DCA ( 4*32+18) /* Direct Cache Access */ | ||
288 | -#define X86_FEATURE_XMM4_1 ( 4*32+19) /* "sse4_1" SSE-4.1 */ | ||
289 | -#define X86_FEATURE_XMM4_2 ( 4*32+20) /* "sse4_2" SSE-4.2 */ | ||
290 | -#define X86_FEATURE_X2APIC ( 4*32+21) /* x2APIC */ | ||
291 | -#define X86_FEATURE_MOVBE ( 4*32+22) /* MOVBE instruction */ | ||
292 | -#define X86_FEATURE_POPCNT ( 4*32+23) /* POPCNT instruction */ | ||
293 | -#define X86_FEATURE_TSC_DEADLINE_TIMER ( 4*32+24) /* Tsc deadline timer */ | ||
294 | -#define X86_FEATURE_AES ( 4*32+25) /* AES instructions */ | ||
295 | -#define X86_FEATURE_XSAVE ( 4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */ | ||
296 | -#define X86_FEATURE_OSXSAVE ( 4*32+27) /* "" XSAVE enabled in the OS */ | ||
297 | -#define X86_FEATURE_AVX ( 4*32+28) /* Advanced Vector Extensions */ | ||
298 | -#define X86_FEATURE_F16C ( 4*32+29) /* 16-bit fp conversions */ | ||
299 | -#define X86_FEATURE_RDRAND ( 4*32+30) /* The RDRAND instruction */ | ||
300 | -#define X86_FEATURE_HYPERVISOR ( 4*32+31) /* Running on a hypervisor */ | ||
301 | +/* Intel-defined CPU features, CPUID level 0x00000001 (ECX), word 4 */ | ||
302 | +#define X86_FEATURE_XMM3 ( 4*32+ 0) /* "pni" SSE-3 */ | ||
303 | +#define X86_FEATURE_PCLMULQDQ ( 4*32+ 1) /* PCLMULQDQ instruction */ | ||
304 | +#define X86_FEATURE_DTES64 ( 4*32+ 2) /* 64-bit Debug Store */ | ||
305 | +#define X86_FEATURE_MWAIT ( 4*32+ 3) /* "monitor" MONITOR/MWAIT support */ | ||
306 | +#define X86_FEATURE_DSCPL ( 4*32+ 4) /* "ds_cpl" CPL-qualified (filtered) Debug Store */ | ||
307 | +#define X86_FEATURE_VMX ( 4*32+ 5) /* Hardware virtualization */ | ||
308 | +#define X86_FEATURE_SMX ( 4*32+ 6) /* Safer Mode eXtensions */ | ||
309 | +#define X86_FEATURE_EST ( 4*32+ 7) /* Enhanced SpeedStep */ | ||
310 | +#define X86_FEATURE_TM2 ( 4*32+ 8) /* Thermal Monitor 2 */ | ||
311 | +#define X86_FEATURE_SSSE3 ( 4*32+ 9) /* Supplemental SSE-3 */ | ||
312 | +#define X86_FEATURE_CID ( 4*32+10) /* Context ID */ | ||
313 | +#define X86_FEATURE_SDBG ( 4*32+11) /* Silicon Debug */ | ||
314 | +#define X86_FEATURE_FMA ( 4*32+12) /* Fused multiply-add */ | ||
315 | +#define X86_FEATURE_CX16 ( 4*32+13) /* CMPXCHG16B instruction */ | ||
316 | +#define X86_FEATURE_XTPR ( 4*32+14) /* Send Task Priority Messages */ | ||
317 | +#define X86_FEATURE_PDCM ( 4*32+15) /* Perf/Debug Capabilities MSR */ | ||
318 | +#define X86_FEATURE_PCID ( 4*32+17) /* Process Context Identifiers */ | ||
319 | +#define X86_FEATURE_DCA ( 4*32+18) /* Direct Cache Access */ | ||
320 | +#define X86_FEATURE_XMM4_1 ( 4*32+19) /* "sse4_1" SSE-4.1 */ | ||
321 | +#define X86_FEATURE_XMM4_2 ( 4*32+20) /* "sse4_2" SSE-4.2 */ | ||
322 | +#define X86_FEATURE_X2APIC ( 4*32+21) /* X2APIC */ | ||
323 | +#define X86_FEATURE_MOVBE ( 4*32+22) /* MOVBE instruction */ | ||
324 | +#define X86_FEATURE_POPCNT ( 4*32+23) /* POPCNT instruction */ | ||
325 | +#define X86_FEATURE_TSC_DEADLINE_TIMER ( 4*32+24) /* TSC deadline timer */ | ||
326 | +#define X86_FEATURE_AES ( 4*32+25) /* AES instructions */ | ||
327 | +#define X86_FEATURE_XSAVE ( 4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV instructions */ | ||
328 | +#define X86_FEATURE_OSXSAVE ( 4*32+27) /* "" XSAVE instruction enabled in the OS */ | ||
329 | +#define X86_FEATURE_AVX ( 4*32+28) /* Advanced Vector Extensions */ | ||
330 | +#define X86_FEATURE_F16C ( 4*32+29) /* 16-bit FP conversions */ | ||
331 | +#define X86_FEATURE_RDRAND ( 4*32+30) /* RDRAND instruction */ | ||
332 | +#define X86_FEATURE_HYPERVISOR ( 4*32+31) /* Running on a hypervisor */ | ||
333 | |||
334 | /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */ | ||
335 | -#define X86_FEATURE_XSTORE ( 5*32+ 2) /* "rng" RNG present (xstore) */ | ||
336 | -#define X86_FEATURE_XSTORE_EN ( 5*32+ 3) /* "rng_en" RNG enabled */ | ||
337 | -#define X86_FEATURE_XCRYPT ( 5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */ | ||
338 | -#define X86_FEATURE_XCRYPT_EN ( 5*32+ 7) /* "ace_en" on-CPU crypto enabled */ | ||
339 | -#define X86_FEATURE_ACE2 ( 5*32+ 8) /* Advanced Cryptography Engine v2 */ | ||
340 | -#define X86_FEATURE_ACE2_EN ( 5*32+ 9) /* ACE v2 enabled */ | ||
341 | -#define X86_FEATURE_PHE ( 5*32+10) /* PadLock Hash Engine */ | ||
342 | -#define X86_FEATURE_PHE_EN ( 5*32+11) /* PHE enabled */ | ||
343 | -#define X86_FEATURE_PMM ( 5*32+12) /* PadLock Montgomery Multiplier */ | ||
344 | -#define X86_FEATURE_PMM_EN ( 5*32+13) /* PMM enabled */ | ||
345 | +#define X86_FEATURE_XSTORE ( 5*32+ 2) /* "rng" RNG present (xstore) */ | ||
346 | +#define X86_FEATURE_XSTORE_EN ( 5*32+ 3) /* "rng_en" RNG enabled */ | ||
347 | +#define X86_FEATURE_XCRYPT ( 5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */ | ||
348 | +#define X86_FEATURE_XCRYPT_EN ( 5*32+ 7) /* "ace_en" on-CPU crypto enabled */ | ||
349 | +#define X86_FEATURE_ACE2 ( 5*32+ 8) /* Advanced Cryptography Engine v2 */ | ||
350 | +#define X86_FEATURE_ACE2_EN ( 5*32+ 9) /* ACE v2 enabled */ | ||
351 | +#define X86_FEATURE_PHE ( 5*32+10) /* PadLock Hash Engine */ | ||
352 | +#define X86_FEATURE_PHE_EN ( 5*32+11) /* PHE enabled */ | ||
353 | +#define X86_FEATURE_PMM ( 5*32+12) /* PadLock Montgomery Multiplier */ | ||
354 | +#define X86_FEATURE_PMM_EN ( 5*32+13) /* PMM enabled */ | ||
355 | |||
356 | -/* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */ | ||
357 | -#define X86_FEATURE_LAHF_LM ( 6*32+ 0) /* LAHF/SAHF in long mode */ | ||
358 | -#define X86_FEATURE_CMP_LEGACY ( 6*32+ 1) /* If yes HyperThreading not valid */ | ||
359 | -#define X86_FEATURE_SVM ( 6*32+ 2) /* Secure virtual machine */ | ||
360 | -#define X86_FEATURE_EXTAPIC ( 6*32+ 3) /* Extended APIC space */ | ||
361 | -#define X86_FEATURE_CR8_LEGACY ( 6*32+ 4) /* CR8 in 32-bit mode */ | ||
362 | -#define X86_FEATURE_ABM ( 6*32+ 5) /* Advanced bit manipulation */ | ||
363 | -#define X86_FEATURE_SSE4A ( 6*32+ 6) /* SSE-4A */ | ||
364 | -#define X86_FEATURE_MISALIGNSSE ( 6*32+ 7) /* Misaligned SSE mode */ | ||
365 | -#define X86_FEATURE_3DNOWPREFETCH ( 6*32+ 8) /* 3DNow prefetch instructions */ | ||
366 | -#define X86_FEATURE_OSVW ( 6*32+ 9) /* OS Visible Workaround */ | ||
367 | -#define X86_FEATURE_IBS ( 6*32+10) /* Instruction Based Sampling */ | ||
368 | -#define X86_FEATURE_XOP ( 6*32+11) /* extended AVX instructions */ | ||
369 | -#define X86_FEATURE_SKINIT ( 6*32+12) /* SKINIT/STGI instructions */ | ||
370 | -#define X86_FEATURE_WDT ( 6*32+13) /* Watchdog timer */ | ||
371 | -#define X86_FEATURE_LWP ( 6*32+15) /* Light Weight Profiling */ | ||
372 | -#define X86_FEATURE_FMA4 ( 6*32+16) /* 4 operands MAC instructions */ | ||
373 | -#define X86_FEATURE_TCE ( 6*32+17) /* translation cache extension */ | ||
374 | -#define X86_FEATURE_NODEID_MSR ( 6*32+19) /* NodeId MSR */ | ||
375 | -#define X86_FEATURE_TBM ( 6*32+21) /* trailing bit manipulations */ | ||
376 | -#define X86_FEATURE_TOPOEXT ( 6*32+22) /* topology extensions CPUID leafs */ | ||
377 | -#define X86_FEATURE_PERFCTR_CORE ( 6*32+23) /* core performance counter extensions */ | ||
378 | -#define X86_FEATURE_PERFCTR_NB ( 6*32+24) /* NB performance counter extensions */ | ||
379 | -#define X86_FEATURE_BPEXT (6*32+26) /* data breakpoint extension */ | ||
380 | -#define X86_FEATURE_PTSC ( 6*32+27) /* performance time-stamp counter */ | ||
381 | -#define X86_FEATURE_PERFCTR_LLC ( 6*32+28) /* Last Level Cache performance counter extensions */ | ||
382 | -#define X86_FEATURE_MWAITX ( 6*32+29) /* MWAIT extension (MONITORX/MWAITX) */ | ||
383 | +/* More extended AMD flags: CPUID level 0x80000001, ECX, word 6 */ | ||
384 | +#define X86_FEATURE_LAHF_LM ( 6*32+ 0) /* LAHF/SAHF in long mode */ | ||
385 | +#define X86_FEATURE_CMP_LEGACY ( 6*32+ 1) /* If yes HyperThreading not valid */ | ||
386 | +#define X86_FEATURE_SVM ( 6*32+ 2) /* Secure Virtual Machine */ | ||
387 | +#define X86_FEATURE_EXTAPIC ( 6*32+ 3) /* Extended APIC space */ | ||
388 | +#define X86_FEATURE_CR8_LEGACY ( 6*32+ 4) /* CR8 in 32-bit mode */ | ||
389 | +#define X86_FEATURE_ABM ( 6*32+ 5) /* Advanced bit manipulation */ | ||
390 | +#define X86_FEATURE_SSE4A ( 6*32+ 6) /* SSE-4A */ | ||
391 | +#define X86_FEATURE_MISALIGNSSE ( 6*32+ 7) /* Misaligned SSE mode */ | ||
392 | +#define X86_FEATURE_3DNOWPREFETCH ( 6*32+ 8) /* 3DNow prefetch instructions */ | ||
393 | +#define X86_FEATURE_OSVW ( 6*32+ 9) /* OS Visible Workaround */ | ||
394 | +#define X86_FEATURE_IBS ( 6*32+10) /* Instruction Based Sampling */ | ||
395 | +#define X86_FEATURE_XOP ( 6*32+11) /* extended AVX instructions */ | ||
396 | +#define X86_FEATURE_SKINIT ( 6*32+12) /* SKINIT/STGI instructions */ | ||
397 | +#define X86_FEATURE_WDT ( 6*32+13) /* Watchdog timer */ | ||
398 | +#define X86_FEATURE_LWP ( 6*32+15) /* Light Weight Profiling */ | ||
399 | +#define X86_FEATURE_FMA4 ( 6*32+16) /* 4 operands MAC instructions */ | ||
400 | +#define X86_FEATURE_TCE ( 6*32+17) /* Translation Cache Extension */ | ||
401 | +#define X86_FEATURE_NODEID_MSR ( 6*32+19) /* NodeId MSR */ | ||
402 | +#define X86_FEATURE_TBM ( 6*32+21) /* Trailing Bit Manipulations */ | ||
403 | +#define X86_FEATURE_TOPOEXT ( 6*32+22) /* Topology extensions CPUID leafs */ | ||
404 | +#define X86_FEATURE_PERFCTR_CORE ( 6*32+23) /* Core performance counter extensions */ | ||
405 | +#define X86_FEATURE_PERFCTR_NB ( 6*32+24) /* NB performance counter extensions */ | ||
406 | +#define X86_FEATURE_BPEXT ( 6*32+26) /* Data breakpoint extension */ | ||
407 | +#define X86_FEATURE_PTSC ( 6*32+27) /* Performance time-stamp counter */ | ||
408 | +#define X86_FEATURE_PERFCTR_LLC ( 6*32+28) /* Last Level Cache performance counter extensions */ | ||
409 | +#define X86_FEATURE_MWAITX ( 6*32+29) /* MWAIT extension (MONITORX/MWAITX instructions) */ | ||
410 | |||
411 | /* | ||
412 | * Auxiliary flags: Linux defined - For features scattered in various | ||
413 | @@ -187,146 +190,185 @@ | ||
414 | * | ||
415 | * Reuse free bits when adding new feature flags! | ||
416 | */ | ||
417 | -#define X86_FEATURE_RING3MWAIT ( 7*32+ 0) /* Ring 3 MONITOR/MWAIT */ | ||
418 | -#define X86_FEATURE_CPUID_FAULT ( 7*32+ 1) /* Intel CPUID faulting */ | ||
419 | -#define X86_FEATURE_CPB ( 7*32+ 2) /* AMD Core Performance Boost */ | ||
420 | -#define X86_FEATURE_EPB ( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */ | ||
421 | -#define X86_FEATURE_CAT_L3 ( 7*32+ 4) /* Cache Allocation Technology L3 */ | ||
422 | -#define X86_FEATURE_CAT_L2 ( 7*32+ 5) /* Cache Allocation Technology L2 */ | ||
423 | -#define X86_FEATURE_CDP_L3 ( 7*32+ 6) /* Code and Data Prioritization L3 */ | ||
424 | - | ||
425 | -#define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* AMD HW-PState */ | ||
426 | -#define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */ | ||
427 | -#define X86_FEATURE_SME ( 7*32+10) /* AMD Secure Memory Encryption */ | ||
428 | +#define X86_FEATURE_RING3MWAIT ( 7*32+ 0) /* Ring 3 MONITOR/MWAIT instructions */ | ||
429 | +#define X86_FEATURE_CPUID_FAULT ( 7*32+ 1) /* Intel CPUID faulting */ | ||
430 | +#define X86_FEATURE_CPB ( 7*32+ 2) /* AMD Core Performance Boost */ | ||
431 | +#define X86_FEATURE_EPB ( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */ | ||
432 | +#define X86_FEATURE_CAT_L3 ( 7*32+ 4) /* Cache Allocation Technology L3 */ | ||
433 | +#define X86_FEATURE_CAT_L2 ( 7*32+ 5) /* Cache Allocation Technology L2 */ | ||
434 | +#define X86_FEATURE_CDP_L3 ( 7*32+ 6) /* Code and Data Prioritization L3 */ | ||
435 | +#define X86_FEATURE_INVPCID_SINGLE ( 7*32+ 7) /* Effectively INVPCID && CR4.PCIDE=1 */ | ||
436 | +#define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* AMD HW-PState */ | ||
437 | +#define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */ | ||
438 | +#define X86_FEATURE_SME ( 7*32+10) /* AMD Secure Memory Encryption */ | ||
439 | +#define X86_FEATURE_PTI ( 7*32+11) /* Kernel Page Table Isolation enabled */ | ||
440 | +#define X86_FEATURE_RETPOLINE ( 7*32+12) /* "" Generic Retpoline mitigation for Spectre variant 2 */ | ||
441 | +#define X86_FEATURE_RETPOLINE_AMD ( 7*32+13) /* "" AMD Retpoline mitigation for Spectre variant 2 */ | ||
442 | +#define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor Inventory Number */ | ||
443 | |||
444 | -#define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor Inventory Number */ | ||
445 | -#define X86_FEATURE_INTEL_PT ( 7*32+15) /* Intel Processor Trace */ | ||
446 | -#define X86_FEATURE_AVX512_4VNNIW (7*32+16) /* AVX-512 Neural Network Instructions */ | ||
447 | -#define X86_FEATURE_AVX512_4FMAPS (7*32+17) /* AVX-512 Multiply Accumulation Single precision */ | ||
448 | +#define X86_FEATURE_MSR_SPEC_CTRL ( 7*32+16) /* "" MSR SPEC_CTRL is implemented */ | ||
449 | +#define X86_FEATURE_SSBD ( 7*32+17) /* Speculative Store Bypass Disable */ | ||
450 | +#define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth Allocation */ | ||
451 | +#define X86_FEATURE_RSB_CTXSW ( 7*32+19) /* "" Fill RSB on context switches */ | ||
452 | |||
453 | -#define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth Allocation */ | ||
454 | +#define X86_FEATURE_USE_IBPB ( 7*32+21) /* "" Indirect Branch Prediction Barrier enabled */ | ||
455 | +#define X86_FEATURE_USE_IBRS_FW ( 7*32+22) /* "" Use IBRS during runtime firmware calls */ | ||
456 | +#define X86_FEATURE_SPEC_STORE_BYPASS_DISABLE ( 7*32+23) /* "" Disable Speculative Store Bypass. */ | ||
457 | +#define X86_FEATURE_LS_CFG_SSBD ( 7*32+24) /* "" AMD SSBD implementation via LS_CFG MSR */ | ||
458 | +#define X86_FEATURE_IBRS ( 7*32+25) /* Indirect Branch Restricted Speculation */ | ||
459 | +#define X86_FEATURE_IBPB ( 7*32+26) /* Indirect Branch Prediction Barrier */ | ||
460 | +#define X86_FEATURE_STIBP ( 7*32+27) /* Single Thread Indirect Branch Predictors */ | ||
461 | +#define X86_FEATURE_ZEN ( 7*32+28) /* "" CPU is AMD family 0x17 (Zen) */ | ||
462 | |||
463 | /* Virtualization flags: Linux defined, word 8 */ | ||
464 | -#define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */ | ||
465 | -#define X86_FEATURE_VNMI ( 8*32+ 1) /* Intel Virtual NMI */ | ||
466 | -#define X86_FEATURE_FLEXPRIORITY ( 8*32+ 2) /* Intel FlexPriority */ | ||
467 | -#define X86_FEATURE_EPT ( 8*32+ 3) /* Intel Extended Page Table */ | ||
468 | -#define X86_FEATURE_VPID ( 8*32+ 4) /* Intel Virtual Processor ID */ | ||
469 | +#define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */ | ||
470 | +#define X86_FEATURE_VNMI ( 8*32+ 1) /* Intel Virtual NMI */ | ||
471 | +#define X86_FEATURE_FLEXPRIORITY ( 8*32+ 2) /* Intel FlexPriority */ | ||
472 | +#define X86_FEATURE_EPT ( 8*32+ 3) /* Intel Extended Page Table */ | ||
473 | +#define X86_FEATURE_VPID ( 8*32+ 4) /* Intel Virtual Processor ID */ | ||
474 | |||
475 | -#define X86_FEATURE_VMMCALL ( 8*32+15) /* Prefer vmmcall to vmcall */ | ||
476 | -#define X86_FEATURE_XENPV ( 8*32+16) /* "" Xen paravirtual guest */ | ||
477 | +#define X86_FEATURE_VMMCALL ( 8*32+15) /* Prefer VMMCALL to VMCALL */ | ||
478 | +#define X86_FEATURE_XENPV ( 8*32+16) /* "" Xen paravirtual guest */ | ||
479 | |||
480 | |||
481 | -/* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */ | ||
482 | -#define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* {RD/WR}{FS/GS}BASE instructions*/ | ||
483 | -#define X86_FEATURE_TSC_ADJUST ( 9*32+ 1) /* TSC adjustment MSR 0x3b */ | ||
484 | -#define X86_FEATURE_BMI1 ( 9*32+ 3) /* 1st group bit manipulation extensions */ | ||
485 | -#define X86_FEATURE_HLE ( 9*32+ 4) /* Hardware Lock Elision */ | ||
486 | -#define X86_FEATURE_AVX2 ( 9*32+ 5) /* AVX2 instructions */ | ||
487 | -#define X86_FEATURE_SMEP ( 9*32+ 7) /* Supervisor Mode Execution Protection */ | ||
488 | -#define X86_FEATURE_BMI2 ( 9*32+ 8) /* 2nd group bit manipulation extensions */ | ||
489 | -#define X86_FEATURE_ERMS ( 9*32+ 9) /* Enhanced REP MOVSB/STOSB */ | ||
490 | -#define X86_FEATURE_INVPCID ( 9*32+10) /* Invalidate Processor Context ID */ | ||
491 | -#define X86_FEATURE_RTM ( 9*32+11) /* Restricted Transactional Memory */ | ||
492 | -#define X86_FEATURE_CQM ( 9*32+12) /* Cache QoS Monitoring */ | ||
493 | -#define X86_FEATURE_MPX ( 9*32+14) /* Memory Protection Extension */ | ||
494 | -#define X86_FEATURE_RDT_A ( 9*32+15) /* Resource Director Technology Allocation */ | ||
495 | -#define X86_FEATURE_AVX512F ( 9*32+16) /* AVX-512 Foundation */ | ||
496 | -#define X86_FEATURE_AVX512DQ ( 9*32+17) /* AVX-512 DQ (Double/Quad granular) Instructions */ | ||
497 | -#define X86_FEATURE_RDSEED ( 9*32+18) /* The RDSEED instruction */ | ||
498 | -#define X86_FEATURE_ADX ( 9*32+19) /* The ADCX and ADOX instructions */ | ||
499 | -#define X86_FEATURE_SMAP ( 9*32+20) /* Supervisor Mode Access Prevention */ | ||
500 | -#define X86_FEATURE_AVX512IFMA ( 9*32+21) /* AVX-512 Integer Fused Multiply-Add instructions */ | ||
501 | -#define X86_FEATURE_CLFLUSHOPT ( 9*32+23) /* CLFLUSHOPT instruction */ | ||
502 | -#define X86_FEATURE_CLWB ( 9*32+24) /* CLWB instruction */ | ||
503 | -#define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */ | ||
504 | -#define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */ | ||
505 | -#define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */ | ||
506 | -#define X86_FEATURE_SHA_NI ( 9*32+29) /* SHA1/SHA256 Instruction Extensions */ | ||
507 | -#define X86_FEATURE_AVX512BW ( 9*32+30) /* AVX-512 BW (Byte/Word granular) Instructions */ | ||
508 | -#define X86_FEATURE_AVX512VL ( 9*32+31) /* AVX-512 VL (128/256 Vector Length) Extensions */ | ||
509 | +/* Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9 */ | ||
510 | +#define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* RDFSBASE, WRFSBASE, RDGSBASE, WRGSBASE instructions*/ | ||
511 | +#define X86_FEATURE_TSC_ADJUST ( 9*32+ 1) /* TSC adjustment MSR 0x3B */ | ||
512 | +#define X86_FEATURE_BMI1 ( 9*32+ 3) /* 1st group bit manipulation extensions */ | ||
513 | +#define X86_FEATURE_HLE ( 9*32+ 4) /* Hardware Lock Elision */ | ||
514 | +#define X86_FEATURE_AVX2 ( 9*32+ 5) /* AVX2 instructions */ | ||
515 | +#define X86_FEATURE_SMEP ( 9*32+ 7) /* Supervisor Mode Execution Protection */ | ||
516 | +#define X86_FEATURE_BMI2 ( 9*32+ 8) /* 2nd group bit manipulation extensions */ | ||
517 | +#define X86_FEATURE_ERMS ( 9*32+ 9) /* Enhanced REP MOVSB/STOSB instructions */ | ||
518 | +#define X86_FEATURE_INVPCID ( 9*32+10) /* Invalidate Processor Context ID */ | ||
519 | +#define X86_FEATURE_RTM ( 9*32+11) /* Restricted Transactional Memory */ | ||
520 | +#define X86_FEATURE_CQM ( 9*32+12) /* Cache QoS Monitoring */ | ||
521 | +#define X86_FEATURE_MPX ( 9*32+14) /* Memory Protection Extension */ | ||
522 | +#define X86_FEATURE_RDT_A ( 9*32+15) /* Resource Director Technology Allocation */ | ||
523 | +#define X86_FEATURE_AVX512F ( 9*32+16) /* AVX-512 Foundation */ | ||
524 | +#define X86_FEATURE_AVX512DQ ( 9*32+17) /* AVX-512 DQ (Double/Quad granular) Instructions */ | ||
525 | +#define X86_FEATURE_RDSEED ( 9*32+18) /* RDSEED instruction */ | ||
526 | +#define X86_FEATURE_ADX ( 9*32+19) /* ADCX and ADOX instructions */ | ||
527 | +#define X86_FEATURE_SMAP ( 9*32+20) /* Supervisor Mode Access Prevention */ | ||
528 | +#define X86_FEATURE_AVX512IFMA ( 9*32+21) /* AVX-512 Integer Fused Multiply-Add instructions */ | ||
529 | +#define X86_FEATURE_CLFLUSHOPT ( 9*32+23) /* CLFLUSHOPT instruction */ | ||
530 | +#define X86_FEATURE_CLWB ( 9*32+24) /* CLWB instruction */ | ||
531 | +#define X86_FEATURE_INTEL_PT ( 9*32+25) /* Intel Processor Trace */ | ||
532 | +#define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */ | ||
533 | +#define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */ | ||
534 | +#define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */ | ||
535 | +#define X86_FEATURE_SHA_NI ( 9*32+29) /* SHA1/SHA256 Instruction Extensions */ | ||
536 | +#define X86_FEATURE_AVX512BW ( 9*32+30) /* AVX-512 BW (Byte/Word granular) Instructions */ | ||
537 | +#define X86_FEATURE_AVX512VL ( 9*32+31) /* AVX-512 VL (128/256 Vector Length) Extensions */ | ||
538 | |||
539 | -/* Extended state features, CPUID level 0x0000000d:1 (eax), word 10 */ | ||
540 | -#define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT */ | ||
541 | -#define X86_FEATURE_XSAVEC (10*32+ 1) /* XSAVEC */ | ||
542 | -#define X86_FEATURE_XGETBV1 (10*32+ 2) /* XGETBV with ECX = 1 */ | ||
543 | -#define X86_FEATURE_XSAVES (10*32+ 3) /* XSAVES/XRSTORS */ | ||
544 | +/* Extended state features, CPUID level 0x0000000d:1 (EAX), word 10 */ | ||
545 | +#define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT instruction */ | ||
546 | +#define X86_FEATURE_XSAVEC (10*32+ 1) /* XSAVEC instruction */ | ||
547 | +#define X86_FEATURE_XGETBV1 (10*32+ 2) /* XGETBV with ECX = 1 instruction */ | ||
548 | +#define X86_FEATURE_XSAVES (10*32+ 3) /* XSAVES/XRSTORS instructions */ | ||
549 | |||
550 | -/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:0 (edx), word 11 */ | ||
551 | -#define X86_FEATURE_CQM_LLC (11*32+ 1) /* LLC QoS if 1 */ | ||
552 | +/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:0 (EDX), word 11 */ | ||
553 | +#define X86_FEATURE_CQM_LLC (11*32+ 1) /* LLC QoS if 1 */ | ||
554 | |||
555 | -/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (edx), word 12 */ | ||
556 | -#define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring if 1 */ | ||
557 | -#define X86_FEATURE_CQM_MBM_TOTAL (12*32+ 1) /* LLC Total MBM monitoring */ | ||
558 | -#define X86_FEATURE_CQM_MBM_LOCAL (12*32+ 2) /* LLC Local MBM monitoring */ | ||
559 | +/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (EDX), word 12 */ | ||
560 | +#define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring */ | ||
561 | +#define X86_FEATURE_CQM_MBM_TOTAL (12*32+ 1) /* LLC Total MBM monitoring */ | ||
562 | +#define X86_FEATURE_CQM_MBM_LOCAL (12*32+ 2) /* LLC Local MBM monitoring */ | ||
563 | |||
564 | -/* AMD-defined CPU features, CPUID level 0x80000008 (ebx), word 13 */ | ||
565 | -#define X86_FEATURE_CLZERO (13*32+0) /* CLZERO instruction */ | ||
566 | -#define X86_FEATURE_IRPERF (13*32+1) /* Instructions Retired Count */ | ||
567 | +/* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */ | ||
568 | +#define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ | ||
569 | +#define X86_FEATURE_IRPERF (13*32+ 1) /* Instructions Retired Count */ | ||
570 | +#define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* Always save/restore FP error pointers */ | ||
571 | +#define X86_FEATURE_AMD_IBPB (13*32+12) /* "" Indirect Branch Prediction Barrier */ | ||
572 | +#define X86_FEATURE_AMD_IBRS (13*32+14) /* "" Indirect Branch Restricted Speculation */ | ||
573 | +#define X86_FEATURE_AMD_STIBP (13*32+15) /* "" Single Thread Indirect Branch Predictors */ | ||
574 | +#define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store Bypass Disable */ | ||
575 | |||
576 | -/* Thermal and Power Management Leaf, CPUID level 0x00000006 (eax), word 14 */ | ||
577 | -#define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */ | ||
578 | -#define X86_FEATURE_IDA (14*32+ 1) /* Intel Dynamic Acceleration */ | ||
579 | -#define X86_FEATURE_ARAT (14*32+ 2) /* Always Running APIC Timer */ | ||
580 | -#define X86_FEATURE_PLN (14*32+ 4) /* Intel Power Limit Notification */ | ||
581 | -#define X86_FEATURE_PTS (14*32+ 6) /* Intel Package Thermal Status */ | ||
582 | -#define X86_FEATURE_HWP (14*32+ 7) /* Intel Hardware P-states */ | ||
583 | -#define X86_FEATURE_HWP_NOTIFY (14*32+ 8) /* HWP Notification */ | ||
584 | -#define X86_FEATURE_HWP_ACT_WINDOW (14*32+ 9) /* HWP Activity Window */ | ||
585 | -#define X86_FEATURE_HWP_EPP (14*32+10) /* HWP Energy Perf. Preference */ | ||
586 | -#define X86_FEATURE_HWP_PKG_REQ (14*32+11) /* HWP Package Level Request */ | ||
587 | +/* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */ | ||
588 | +#define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */ | ||
589 | +#define X86_FEATURE_IDA (14*32+ 1) /* Intel Dynamic Acceleration */ | ||
590 | +#define X86_FEATURE_ARAT (14*32+ 2) /* Always Running APIC Timer */ | ||
591 | +#define X86_FEATURE_PLN (14*32+ 4) /* Intel Power Limit Notification */ | ||
592 | +#define X86_FEATURE_PTS (14*32+ 6) /* Intel Package Thermal Status */ | ||
593 | +#define X86_FEATURE_HWP (14*32+ 7) /* Intel Hardware P-states */ | ||
594 | +#define X86_FEATURE_HWP_NOTIFY (14*32+ 8) /* HWP Notification */ | ||
595 | +#define X86_FEATURE_HWP_ACT_WINDOW (14*32+ 9) /* HWP Activity Window */ | ||
596 | +#define X86_FEATURE_HWP_EPP (14*32+10) /* HWP Energy Perf. Preference */ | ||
597 | +#define X86_FEATURE_HWP_PKG_REQ (14*32+11) /* HWP Package Level Request */ | ||
598 | |||
599 | -/* AMD SVM Feature Identification, CPUID level 0x8000000a (edx), word 15 */ | ||
600 | -#define X86_FEATURE_NPT (15*32+ 0) /* Nested Page Table support */ | ||
601 | -#define X86_FEATURE_LBRV (15*32+ 1) /* LBR Virtualization support */ | ||
602 | -#define X86_FEATURE_SVML (15*32+ 2) /* "svm_lock" SVM locking MSR */ | ||
603 | -#define X86_FEATURE_NRIPS (15*32+ 3) /* "nrip_save" SVM next_rip save */ | ||
604 | -#define X86_FEATURE_TSCRATEMSR (15*32+ 4) /* "tsc_scale" TSC scaling support */ | ||
605 | -#define X86_FEATURE_VMCBCLEAN (15*32+ 5) /* "vmcb_clean" VMCB clean bits support */ | ||
606 | -#define X86_FEATURE_FLUSHBYASID (15*32+ 6) /* flush-by-ASID support */ | ||
607 | -#define X86_FEATURE_DECODEASSISTS (15*32+ 7) /* Decode Assists support */ | ||
608 | -#define X86_FEATURE_PAUSEFILTER (15*32+10) /* filtered pause intercept */ | ||
609 | -#define X86_FEATURE_PFTHRESHOLD (15*32+12) /* pause filter threshold */ | ||
610 | -#define X86_FEATURE_AVIC (15*32+13) /* Virtual Interrupt Controller */ | ||
611 | -#define X86_FEATURE_V_VMSAVE_VMLOAD (15*32+15) /* Virtual VMSAVE VMLOAD */ | ||
612 | -#define X86_FEATURE_VGIF (15*32+16) /* Virtual GIF */ | ||
613 | +/* AMD SVM Feature Identification, CPUID level 0x8000000a (EDX), word 15 */ | ||
614 | +#define X86_FEATURE_NPT (15*32+ 0) /* Nested Page Table support */ | ||
615 | +#define X86_FEATURE_LBRV (15*32+ 1) /* LBR Virtualization support */ | ||
616 | +#define X86_FEATURE_SVML (15*32+ 2) /* "svm_lock" SVM locking MSR */ | ||
617 | +#define X86_FEATURE_NRIPS (15*32+ 3) /* "nrip_save" SVM next_rip save */ | ||
618 | +#define X86_FEATURE_TSCRATEMSR (15*32+ 4) /* "tsc_scale" TSC scaling support */ | ||
619 | +#define X86_FEATURE_VMCBCLEAN (15*32+ 5) /* "vmcb_clean" VMCB clean bits support */ | ||
620 | +#define X86_FEATURE_FLUSHBYASID (15*32+ 6) /* flush-by-ASID support */ | ||
621 | +#define X86_FEATURE_DECODEASSISTS (15*32+ 7) /* Decode Assists support */ | ||
622 | +#define X86_FEATURE_PAUSEFILTER (15*32+10) /* filtered pause intercept */ | ||
623 | +#define X86_FEATURE_PFTHRESHOLD (15*32+12) /* pause filter threshold */ | ||
624 | +#define X86_FEATURE_AVIC (15*32+13) /* Virtual Interrupt Controller */ | ||
625 | +#define X86_FEATURE_V_VMSAVE_VMLOAD (15*32+15) /* Virtual VMSAVE VMLOAD */ | ||
626 | +#define X86_FEATURE_VGIF (15*32+16) /* Virtual GIF */ | ||
627 | |||
628 | -/* Intel-defined CPU features, CPUID level 0x00000007:0 (ecx), word 16 */ | ||
629 | -#define X86_FEATURE_AVX512VBMI (16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/ | ||
630 | -#define X86_FEATURE_PKU (16*32+ 3) /* Protection Keys for Userspace */ | ||
631 | -#define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */ | ||
632 | -#define X86_FEATURE_AVX512_VPOPCNTDQ (16*32+14) /* POPCNT for vectors of DW/QW */ | ||
633 | -#define X86_FEATURE_LA57 (16*32+16) /* 5-level page tables */ | ||
634 | -#define X86_FEATURE_RDPID (16*32+22) /* RDPID instruction */ | ||
635 | +/* Intel-defined CPU features, CPUID level 0x00000007:0 (ECX), word 16 */ | ||
636 | +#define X86_FEATURE_AVX512VBMI (16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/ | ||
637 | +#define X86_FEATURE_UMIP (16*32+ 2) /* User Mode Instruction Protection */ | ||
638 | +#define X86_FEATURE_PKU (16*32+ 3) /* Protection Keys for Userspace */ | ||
639 | +#define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */ | ||
640 | +#define X86_FEATURE_AVX512_VBMI2 (16*32+ 6) /* Additional AVX512 Vector Bit Manipulation Instructions */ | ||
641 | +#define X86_FEATURE_GFNI (16*32+ 8) /* Galois Field New Instructions */ | ||
642 | +#define X86_FEATURE_VAES (16*32+ 9) /* Vector AES */ | ||
643 | +#define X86_FEATURE_VPCLMULQDQ (16*32+10) /* Carry-Less Multiplication Double Quadword */ | ||
644 | +#define X86_FEATURE_AVX512_VNNI (16*32+11) /* Vector Neural Network Instructions */ | ||
645 | +#define X86_FEATURE_AVX512_BITALG (16*32+12) /* Support for VPOPCNT[B,W] and VPSHUF-BITQMB instructions */ | ||
646 | +#define X86_FEATURE_TME (16*32+13) /* Intel Total Memory Encryption */ | ||
647 | +#define X86_FEATURE_AVX512_VPOPCNTDQ (16*32+14) /* POPCNT for vectors of DW/QW */ | ||
648 | +#define X86_FEATURE_LA57 (16*32+16) /* 5-level page tables */ | ||
649 | +#define X86_FEATURE_RDPID (16*32+22) /* RDPID instruction */ | ||
650 | |||
651 | -/* AMD-defined CPU features, CPUID level 0x80000007 (ebx), word 17 */ | ||
652 | -#define X86_FEATURE_OVERFLOW_RECOV (17*32+0) /* MCA overflow recovery support */ | ||
653 | -#define X86_FEATURE_SUCCOR (17*32+1) /* Uncorrectable error containment and recovery */ | ||
654 | -#define X86_FEATURE_SMCA (17*32+3) /* Scalable MCA */ | ||
655 | +/* AMD-defined CPU features, CPUID level 0x80000007 (EBX), word 17 */ | ||
656 | +#define X86_FEATURE_OVERFLOW_RECOV (17*32+ 0) /* MCA overflow recovery support */ | ||
657 | +#define X86_FEATURE_SUCCOR (17*32+ 1) /* Uncorrectable error containment and recovery */ | ||
658 | +#define X86_FEATURE_SMCA (17*32+ 3) /* Scalable MCA */ | ||
659 | + | ||
660 | +/* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */ | ||
661 | +#define X86_FEATURE_AVX512_4VNNIW (18*32+ 2) /* AVX-512 Neural Network Instructions */ | ||
662 | +#define X86_FEATURE_AVX512_4FMAPS (18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */ | ||
663 | +#define X86_FEATURE_PCONFIG (18*32+18) /* Intel PCONFIG */ | ||
664 | +#define X86_FEATURE_SPEC_CTRL (18*32+26) /* "" Speculation Control (IBRS + IBPB) */ | ||
665 | +#define X86_FEATURE_INTEL_STIBP (18*32+27) /* "" Single Thread Indirect Branch Predictors */ | ||
666 | +#define X86_FEATURE_ARCH_CAPABILITIES (18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */ | ||
667 | +#define X86_FEATURE_SPEC_CTRL_SSBD (18*32+31) /* "" Speculative Store Bypass Disable */ | ||
668 | |||
669 | /* | ||
670 | * BUG word(s) | ||
671 | */ | ||
672 | -#define X86_BUG(x) (NCAPINTS*32 + (x)) | ||
673 | +#define X86_BUG(x) (NCAPINTS*32 + (x)) | ||
674 | |||
675 | -#define X86_BUG_F00F X86_BUG(0) /* Intel F00F */ | ||
676 | -#define X86_BUG_FDIV X86_BUG(1) /* FPU FDIV */ | ||
677 | -#define X86_BUG_COMA X86_BUG(2) /* Cyrix 6x86 coma */ | ||
678 | -#define X86_BUG_AMD_TLB_MMATCH X86_BUG(3) /* "tlb_mmatch" AMD Erratum 383 */ | ||
679 | -#define X86_BUG_AMD_APIC_C1E X86_BUG(4) /* "apic_c1e" AMD Erratum 400 */ | ||
680 | -#define X86_BUG_11AP X86_BUG(5) /* Bad local APIC aka 11AP */ | ||
681 | -#define X86_BUG_FXSAVE_LEAK X86_BUG(6) /* FXSAVE leaks FOP/FIP/FOP */ | ||
682 | -#define X86_BUG_CLFLUSH_MONITOR X86_BUG(7) /* AAI65, CLFLUSH required before MONITOR */ | ||
683 | -#define X86_BUG_SYSRET_SS_ATTRS X86_BUG(8) /* SYSRET doesn't fix up SS attrs */ | ||
684 | +#define X86_BUG_F00F X86_BUG(0) /* Intel F00F */ | ||
685 | +#define X86_BUG_FDIV X86_BUG(1) /* FPU FDIV */ | ||
686 | +#define X86_BUG_COMA X86_BUG(2) /* Cyrix 6x86 coma */ | ||
687 | +#define X86_BUG_AMD_TLB_MMATCH X86_BUG(3) /* "tlb_mmatch" AMD Erratum 383 */ | ||
688 | +#define X86_BUG_AMD_APIC_C1E X86_BUG(4) /* "apic_c1e" AMD Erratum 400 */ | ||
689 | +#define X86_BUG_11AP X86_BUG(5) /* Bad local APIC aka 11AP */ | ||
690 | +#define X86_BUG_FXSAVE_LEAK X86_BUG(6) /* FXSAVE leaks FOP/FIP/FOP */ | ||
691 | +#define X86_BUG_CLFLUSH_MONITOR X86_BUG(7) /* AAI65, CLFLUSH required before MONITOR */ | ||
692 | +#define X86_BUG_SYSRET_SS_ATTRS X86_BUG(8) /* SYSRET doesn't fix up SS attrs */ | ||
693 | #ifdef CONFIG_X86_32 | ||
694 | /* | ||
695 | * 64-bit kernels don't use X86_BUG_ESPFIX. Make the define conditional | ||
696 | * to avoid confusion. | ||
697 | */ | ||
698 | -#define X86_BUG_ESPFIX X86_BUG(9) /* "" IRET to 16-bit SS corrupts ESP/RSP high bits */ | ||
699 | +#define X86_BUG_ESPFIX X86_BUG(9) /* "" IRET to 16-bit SS corrupts ESP/RSP high bits */ | ||
700 | #endif | ||
701 | -#define X86_BUG_NULL_SEG X86_BUG(10) /* Nulling a selector preserves the base */ | ||
702 | -#define X86_BUG_SWAPGS_FENCE X86_BUG(11) /* SWAPGS without input dep on GS */ | ||
703 | -#define X86_BUG_MONITOR X86_BUG(12) /* IPI required to wake up remote CPU */ | ||
704 | -#define X86_BUG_AMD_E400 X86_BUG(13) /* CPU is among the affected by Erratum 400 */ | ||
705 | +#define X86_BUG_NULL_SEG X86_BUG(10) /* Nulling a selector preserves the base */ | ||
706 | +#define X86_BUG_SWAPGS_FENCE X86_BUG(11) /* SWAPGS without input dep on GS */ | ||
707 | +#define X86_BUG_MONITOR X86_BUG(12) /* IPI required to wake up remote CPU */ | ||
708 | +#define X86_BUG_AMD_E400 X86_BUG(13) /* CPU is among the affected by Erratum 400 */ | ||
709 | +#define X86_BUG_CPU_MELTDOWN X86_BUG(14) /* CPU is affected by meltdown attack and needs kernel page table isolation */ | ||
710 | +#define X86_BUG_SPECTRE_V1 X86_BUG(15) /* CPU is affected by Spectre variant 1 attack with conditional branches */ | ||
711 | +#define X86_BUG_SPECTRE_V2 X86_BUG(16) /* CPU is affected by Spectre variant 2 attack with indirect branches */ | ||
712 | +#define X86_BUG_SPEC_STORE_BYPASS X86_BUG(17) /* CPU is affected by speculative store bypass attack */ | ||
713 | + | ||
714 | #endif /* _ASM_X86_CPUFEATURES_H */ | ||
715 | diff --git a/tools/arch/x86/include/asm/disabled-features.h b/tools/arch/x86/include/asm/disabled-features.h | ||
716 | index c10c9128f54e..c6a3af198294 100644 | ||
717 | --- a/tools/arch/x86/include/asm/disabled-features.h | ||
718 | +++ b/tools/arch/x86/include/asm/disabled-features.h | ||
719 | @@ -44,6 +44,12 @@ | ||
720 | # define DISABLE_LA57 (1<<(X86_FEATURE_LA57 & 31)) | ||
721 | #endif | ||
722 | |||
723 | +#ifdef CONFIG_PAGE_TABLE_ISOLATION | ||
724 | +# define DISABLE_PTI 0 | ||
725 | +#else | ||
726 | +# define DISABLE_PTI (1 << (X86_FEATURE_PTI & 31)) | ||
727 | +#endif | ||
728 | + | ||
729 | /* | ||
730 | * Make sure to add features to the correct mask | ||
731 | */ | ||
732 | @@ -54,7 +60,7 @@ | ||
733 | #define DISABLED_MASK4 (DISABLE_PCID) | ||
734 | #define DISABLED_MASK5 0 | ||
735 | #define DISABLED_MASK6 0 | ||
736 | -#define DISABLED_MASK7 0 | ||
737 | +#define DISABLED_MASK7 (DISABLE_PTI) | ||
738 | #define DISABLED_MASK8 0 | ||
739 | #define DISABLED_MASK9 (DISABLE_MPX) | ||
740 | #define DISABLED_MASK10 0 | ||
741 | @@ -65,6 +71,7 @@ | ||
742 | #define DISABLED_MASK15 0 | ||
743 | #define DISABLED_MASK16 (DISABLE_PKU|DISABLE_OSPKE|DISABLE_LA57) | ||
744 | #define DISABLED_MASK17 0 | ||
745 | -#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 18) | ||
746 | +#define DISABLED_MASK18 0 | ||
747 | +#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 19) | ||
748 | |||
749 | #endif /* _ASM_X86_DISABLED_FEATURES_H */ | ||
750 | diff --git a/tools/arch/x86/include/asm/required-features.h b/tools/arch/x86/include/asm/required-features.h | ||
751 | index d91ba04dd007..fb3a6de7440b 100644 | ||
752 | --- a/tools/arch/x86/include/asm/required-features.h | ||
753 | +++ b/tools/arch/x86/include/asm/required-features.h | ||
754 | @@ -106,6 +106,7 @@ | ||
755 | #define REQUIRED_MASK15 0 | ||
756 | #define REQUIRED_MASK16 (NEED_LA57) | ||
757 | #define REQUIRED_MASK17 0 | ||
758 | -#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 18) | ||
759 | +#define REQUIRED_MASK18 0 | ||
760 | +#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 19) | ||
761 | |||
762 | #endif /* _ASM_X86_REQUIRED_FEATURES_H */ | ||
763 | diff --git a/tools/include/uapi/linux/kvm.h b/tools/include/uapi/linux/kvm.h | ||
764 | index 7e99999d6236..857bad91c454 100644 | ||
765 | --- a/tools/include/uapi/linux/kvm.h | ||
766 | +++ b/tools/include/uapi/linux/kvm.h | ||
767 | @@ -931,6 +931,7 @@ struct kvm_ppc_resize_hpt { | ||
768 | #define KVM_CAP_PPC_SMT_POSSIBLE 147 | ||
769 | #define KVM_CAP_HYPERV_SYNIC2 148 | ||
770 | #define KVM_CAP_HYPERV_VP_INDEX 149 | ||
771 | +#define KVM_CAP_S390_BPB 152 | ||
772 | |||
773 | #ifdef KVM_CAP_IRQ_ROUTING | ||
774 | |||
775 | diff --git a/tools/perf/.gitignore b/tools/perf/.gitignore | ||
776 | index 643cc4ba6872..3e5135dded16 100644 | ||
777 | --- a/tools/perf/.gitignore | ||
778 | +++ b/tools/perf/.gitignore | ||
779 | @@ -31,5 +31,6 @@ config.mak.autogen | ||
780 | .config-detected | ||
781 | util/intel-pt-decoder/inat-tables.c | ||
782 | arch/*/include/generated/ | ||
783 | +trace/beauty/generated/ | ||
784 | pmu-events/pmu-events.c | ||
785 | pmu-events/jevents | ||
786 | diff --git a/tools/perf/builtin-record.c b/tools/perf/builtin-record.c | ||
787 | index 3b570e808b31..b205c1340456 100644 | ||
788 | --- a/tools/perf/builtin-record.c | ||
789 | +++ b/tools/perf/builtin-record.c | ||
790 | @@ -926,15 +926,6 @@ static int __cmd_record(struct record *rec, int argc, const char **argv) | ||
791 | } | ||
792 | } | ||
793 | |||
794 | - /* | ||
795 | - * If we have just single event and are sending data | ||
796 | - * through pipe, we need to force the ids allocation, | ||
797 | - * because we synthesize event name through the pipe | ||
798 | - * and need the id for that. | ||
799 | - */ | ||
800 | - if (data->is_pipe && rec->evlist->nr_entries == 1) | ||
801 | - rec->opts.sample_id = true; | ||
802 | - | ||
803 | if (record__open(rec) != 0) { | ||
804 | err = -1; | ||
805 | goto out_child; | ||
806 | diff --git a/tools/perf/perf.h b/tools/perf/perf.h | ||
807 | index de1debcd3ee7..55086389fc06 100644 | ||
808 | --- a/tools/perf/perf.h | ||
809 | +++ b/tools/perf/perf.h | ||
810 | @@ -61,7 +61,6 @@ struct record_opts { | ||
811 | bool tail_synthesize; | ||
812 | bool overwrite; | ||
813 | bool ignore_missing_thread; | ||
814 | - bool sample_id; | ||
815 | unsigned int freq; | ||
816 | unsigned int mmap_pages; | ||
817 | unsigned int auxtrace_mmap_pages; | ||
818 | diff --git a/tools/perf/util/record.c b/tools/perf/util/record.c | ||
819 | index 6f09e4962dad..1e97937b03a9 100644 | ||
820 | --- a/tools/perf/util/record.c | ||
821 | +++ b/tools/perf/util/record.c | ||
822 | @@ -137,7 +137,6 @@ void perf_evlist__config(struct perf_evlist *evlist, struct record_opts *opts, | ||
823 | struct perf_evsel *evsel; | ||
824 | bool use_sample_identifier = false; | ||
825 | bool use_comm_exec; | ||
826 | - bool sample_id = opts->sample_id; | ||
827 | |||
828 | /* | ||
829 | * Set the evsel leader links before we configure attributes, | ||
830 | @@ -164,7 +163,8 @@ void perf_evlist__config(struct perf_evlist *evlist, struct record_opts *opts, | ||
831 | * match the id. | ||
832 | */ | ||
833 | use_sample_identifier = perf_can_sample_identifier(); | ||
834 | - sample_id = true; | ||
835 | + evlist__for_each_entry(evlist, evsel) | ||
836 | + perf_evsel__set_sample_id(evsel, use_sample_identifier); | ||
837 | } else if (evlist->nr_entries > 1) { | ||
838 | struct perf_evsel *first = perf_evlist__first(evlist); | ||
839 | |||
840 | @@ -174,10 +174,6 @@ void perf_evlist__config(struct perf_evlist *evlist, struct record_opts *opts, | ||
841 | use_sample_identifier = perf_can_sample_identifier(); | ||
842 | break; | ||
843 | } | ||
844 | - sample_id = true; | ||
845 | - } | ||
846 | - | ||
847 | - if (sample_id) { | ||
848 | evlist__for_each_entry(evlist, evsel) | ||
849 | perf_evsel__set_sample_id(evsel, use_sample_identifier); | ||
850 | } |