Magellan Linux

Contents of /trunk/kernel26-alx/patches-2.6.20-r6/0002-2.6.20-sched-staircase17_interactive_tunable.patch

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Revision 1175 - (show annotations) (download)
Thu Oct 14 12:15:46 2010 UTC (13 years, 6 months ago) by niro
File size: 3719 byte(s)
-2.6.20-alx-r6 new magellan 0.5.2 kernel
1 Add the interactive tunable for the staircase cpu scheduler. The default
2 behaviour is for nice value to determine cpu proportion only, and wakeup
3 latency is determined by the percentage of the cpu entitlement of a task. The
4 interactive tunable modifies this behaviour such that nice value determines
5 both cpu proportion and wakeup latency.
6
7 Signed-off-by: Con Kolivas <kernel@kolivas.org>
8
9 Documentation/sysctl/kernel.txt | 10 ++++++++++
10 include/linux/sched.h | 1 +
11 kernel/sched.c | 8 +++++++-
12 kernel/sysctl.c | 8 ++++++++
13 4 files changed, 26 insertions(+), 1 deletion(-)
14
15 Index: linux-2.6.20-ck1/include/linux/sched.h
16 ===================================================================
17 --- linux-2.6.20-ck1.orig/include/linux/sched.h 2007-02-16 19:01:30.000000000 +1100
18 +++ linux-2.6.20-ck1/include/linux/sched.h 2007-02-16 19:01:30.000000000 +1100
19 @@ -216,6 +216,7 @@ extern void show_stack(struct task_struc
20
21 void io_schedule(void);
22 long io_schedule_timeout(long timeout);
23 +extern int sched_interactive;
24
25 extern void cpu_init (void);
26 extern void trap_init(void);
27 Index: linux-2.6.20-ck1/kernel/sysctl.c
28 ===================================================================
29 --- linux-2.6.20-ck1.orig/kernel/sysctl.c 2007-02-05 22:52:04.000000000 +1100
30 +++ linux-2.6.20-ck1/kernel/sysctl.c 2007-02-16 19:01:30.000000000 +1100
31 @@ -676,6 +676,14 @@ static ctl_table kern_table[] = {
32 .mode = 0444,
33 .proc_handler = &proc_dointvec,
34 },
35 + {
36 + .ctl_name = CTL_UNNUMBERED,
37 + .procname = "interactive",
38 + .data = &sched_interactive,
39 + .maxlen = sizeof (int),
40 + .mode = 0644,
41 + .proc_handler = &proc_dointvec,
42 + },
43 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86)
44 {
45 .ctl_name = KERN_UNKNOWN_NMI_PANIC,
46 Index: linux-2.6.20-ck1/kernel/sched.c
47 ===================================================================
48 --- linux-2.6.20-ck1.orig/kernel/sched.c 2007-02-16 19:01:30.000000000 +1100
49 +++ linux-2.6.20-ck1/kernel/sched.c 2007-02-16 19:01:30.000000000 +1100
50 @@ -61,6 +61,12 @@
51 #include <asm/unistd.h>
52
53 /*
54 + * sched_interactive - sysctl which allows interactive tasks to have bonus
55 + * raise its priority.
56 + */
57 +int sched_interactive __read_mostly = 1;
58 +
59 +/*
60 * Convert user-nice values [ -20 ... 0 ... 19 ]
61 * to static priority [ MAX_RT_PRIO..MAX_PRIO-1 ],
62 * and back.
63 @@ -867,7 +873,7 @@ static inline int __normal_prio(struct t
64
65 best_bonus = bonus(p);
66 prio = MAX_RT_PRIO + best_bonus;
67 - if (!batch_task(p))
68 + if (sched_interactive && !batch_task(p))
69 prio -= p->bonus;
70
71 rr = rr_interval(p);
72 Index: linux-2.6.20-ck1/Documentation/sysctl/kernel.txt
73 ===================================================================
74 --- linux-2.6.20-ck1.orig/Documentation/sysctl/kernel.txt 2007-02-05 22:51:59.000000000 +1100
75 +++ linux-2.6.20-ck1/Documentation/sysctl/kernel.txt 2007-02-16 19:01:30.000000000 +1100
76 @@ -25,6 +25,7 @@ show up in /proc/sys/kernel:
77 - domainname
78 - hostname
79 - hotplug
80 +- interactive
81 - java-appletviewer [ binfmt_java, obsolete ]
82 - java-interpreter [ binfmt_java, obsolete ]
83 - kstack_depth_to_print [ X86 only ]
84 @@ -164,6 +165,15 @@ Default value is "/sbin/hotplug".
85
86 ==============================================================
87
88 +interactive:
89 +
90 +This flag controls the allocation of dynamic priorities in the cpu
91 +scheduler. It gives low cpu using tasks high priority for lowest
92 +latencies. Nice value is still observed but stricter cpu proportions
93 +are obeyed if this tunable is disabled. Enabled by default.
94 +
95 +==============================================================
96 +
97 l2cr: (PPC only)
98
99 This flag controls the L2 cache of G3 processor boards. If