Contents of /trunk/kernel26-alx/patches-2.6.28-r1/0161-2.6.28-atl2-2.0.4-2.patch
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Revision 750 -
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Tue Jan 20 11:46:37 2009 UTC (15 years, 8 months ago) by niro
File size: 135463 byte(s)
Tue Jan 20 11:46:37 2009 UTC (15 years, 8 months ago) by niro
File size: 135463 byte(s)
ver bump to 2.6.28-alx-r1
1 | Index: linux-2.6.26.noarch/drivers/net/Kconfig |
2 | =================================================================== |
3 | --- linux-2.6.26.noarch.orig/drivers/net/Kconfig |
4 | +++ linux-2.6.26.noarch/drivers/net/Kconfig |
5 | @@ -2375,6 +2375,17 @@ config ATL1E |
6 | To compile this driver as a module, choose M here. The module |
7 | will be called atl1e. |
8 | |
9 | + config ATL2 |
10 | + tristate "Atheros L2 Fast Ethernet support (EXPERIMENTAL)" |
11 | + depends on PCI && EXPERIMENTAL |
12 | + select CRC32 |
13 | + select MII |
14 | + help |
15 | + This driver supports the Atheros L2 fast ethernet adapter. |
16 | + |
17 | + To compile this driver as a module, choose M here. The module |
18 | + will be called atl2. |
19 | + |
20 | endif # NETDEV_1000 |
21 | |
22 | # |
23 | Index: linux-2.6.26.noarch/drivers/net/Makefile |
24 | =================================================================== |
25 | --- linux-2.6.26.noarch.orig/drivers/net/Makefile |
26 | +++ linux-2.6.26.noarch/drivers/net/Makefile |
27 | @@ -17,6 +17,7 @@ obj-$(CONFIG_CAN) += can/ |
28 | obj-$(CONFIG_BONDING) += bonding/ |
29 | obj-$(CONFIG_ATL1) += atlx/ |
30 | obj-$(CONFIG_ATL1E) += atl1e/ |
31 | +obj-$(CONFIG_ATL2) += atl2/ |
32 | obj-$(CONFIG_GIANFAR) += gianfar_driver.o |
33 | obj-$(CONFIG_TEHUTI) += tehuti.o |
34 | |
35 | Index: linux-2.6.26.noarch/drivers/net/atl2/Makefile |
36 | =================================================================== |
37 | --- /dev/null |
38 | +++ linux-2.6.26.noarch/drivers/net/atl2/Makefile |
39 | @@ -0,0 +1,2 @@ |
40 | +obj-$(CONFIG_ATL2) += atl2.o |
41 | +atl2-y += atl2_main.o atl2_hw.o atl2_ethtool.o atl2_param.o |
42 | Index: linux-2.6.26.noarch/drivers/net/atl2/atl2.h |
43 | =================================================================== |
44 | --- /dev/null |
45 | +++ linux-2.6.26.noarch/drivers/net/atl2/atl2.h |
46 | @@ -0,0 +1,120 @@ |
47 | +/* atl2.h -- atl2 driver definitions |
48 | + * |
49 | + * Copyright(c) 2007 Atheros Corporation. All rights reserved. |
50 | + * Copyright(c) 2006 xiong huang <xiong.huang@atheros.com> |
51 | + * Copyright(c) 2007 Chris Snook <csnook@redhat.com> |
52 | + * |
53 | + * Derived from Intel e1000 driver |
54 | + * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. |
55 | + * |
56 | + * This program is free software; you can redistribute it and/or modify it |
57 | + * under the terms of the GNU General Public License as published by the Free |
58 | + * Software Foundation; either version 2 of the License, or (at your option) |
59 | + * any later version. |
60 | + * |
61 | + * This program is distributed in the hope that it will be useful, but WITHOUT |
62 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
63 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
64 | + * more details. |
65 | + * |
66 | + * You should have received a copy of the GNU General Public License along with |
67 | + * this program; if not, write to the Free Software Foundation, Inc., 59 |
68 | + * Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
69 | + */ |
70 | + |
71 | +#ifndef _ATL2_H_ |
72 | +#define _ATL2_H_ |
73 | + |
74 | +#include <asm/atomic.h> |
75 | +#include <linux/netdevice.h> |
76 | + |
77 | +#include "atl2_hw.h" |
78 | + |
79 | +struct atl2_ring_header { |
80 | + /* pointer to the descriptor ring memory */ |
81 | + void *desc; |
82 | + /* physical adress of the descriptor ring */ |
83 | + dma_addr_t dma; |
84 | + /* length of descriptor ring in bytes */ |
85 | + unsigned int size; |
86 | +}; |
87 | + |
88 | +/* board specific private data structure */ |
89 | +struct atl2_adapter { |
90 | + /* OS defined structs */ |
91 | + struct net_device *netdev; |
92 | + struct pci_dev *pdev; |
93 | + struct net_device_stats net_stats; |
94 | +#ifdef NETIF_F_HW_VLAN_TX |
95 | + struct vlan_group *vlgrp; |
96 | +#endif |
97 | + u32 wol; |
98 | + u16 link_speed; |
99 | + u16 link_duplex; |
100 | + |
101 | + spinlock_t stats_lock; |
102 | + spinlock_t tx_lock; |
103 | + |
104 | + struct work_struct reset_task; |
105 | + struct work_struct link_chg_task; |
106 | + struct timer_list watchdog_timer; |
107 | + struct timer_list phy_config_timer; |
108 | + |
109 | + unsigned long cfg_phy; |
110 | + bool mac_disabled; |
111 | + |
112 | + /* All Descriptor memory */ |
113 | + dma_addr_t ring_dma; |
114 | + void *ring_vir_addr; |
115 | + int ring_size; |
116 | + |
117 | + tx_pkt_header_t *txd_ring; |
118 | + dma_addr_t txd_dma; |
119 | + |
120 | + tx_pkt_status_t *txs_ring; |
121 | + dma_addr_t txs_dma; |
122 | + |
123 | + rx_desc_t *rxd_ring; |
124 | + dma_addr_t rxd_dma; |
125 | + |
126 | + u32 txd_ring_size; // bytes per unit |
127 | + u32 txs_ring_size; // dwords per unit |
128 | + u32 rxd_ring_size; // 1536bytes per unit |
129 | + |
130 | + // read /write ptr: |
131 | + // host |
132 | + u32 txd_write_ptr; |
133 | + u32 txs_next_clear; |
134 | + u32 rxd_read_ptr; |
135 | + |
136 | + // nic |
137 | + atomic_t txd_read_ptr; |
138 | + atomic_t txs_write_ptr; |
139 | + u32 rxd_write_ptr; |
140 | + |
141 | + /* Interrupt Moderator timer ( 2us resolution) */ |
142 | + u16 imt; |
143 | + /* Interrupt Clear timer (2us resolution) */ |
144 | + u16 ict; |
145 | + |
146 | + unsigned long flags; |
147 | + /* structs defined in atl2_hw.h */ |
148 | + u32 bd_number; // board number; |
149 | + bool pci_using_64; |
150 | + bool have_msi; |
151 | + struct atl2_hw hw; |
152 | + |
153 | + u32 usr_cmd; |
154 | +// u32 regs_buff[ATL2_REGS_LEN]; |
155 | + u32 pci_state[16]; |
156 | + |
157 | + u32 *config_space; |
158 | +}; |
159 | + |
160 | +enum atl2_state_t { |
161 | + __ATL2_TESTING, |
162 | + __ATL2_RESETTING, |
163 | + __ATL2_DOWN |
164 | +}; |
165 | + |
166 | +#endif /* _ATL2_H_ */ |
167 | Index: linux-2.6.26.noarch/drivers/net/atl2/atl2_ethtool.c |
168 | =================================================================== |
169 | --- /dev/null |
170 | +++ linux-2.6.26.noarch/drivers/net/atl2/atl2_ethtool.c |
171 | @@ -0,0 +1,416 @@ |
172 | +/* atl2_ethtool.c -- atl2 ethtool support |
173 | + * |
174 | + * Copyright(c) 2007 Atheros Corporation. All rights reserved. |
175 | + * Copyright(c) 2006 xiong huang <xiong.huang@atheros.com> |
176 | + * Copyright(c) 2007 Chris Snook <csnook@redhat.com> |
177 | + * |
178 | + * Derived from Intel e1000 driver |
179 | + * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. |
180 | + * |
181 | + * This program is free software; you can redistribute it and/or modify it |
182 | + * under the terms of the GNU General Public License as published by the Free |
183 | + * Software Foundation; either version 2 of the License, or (at your option) |
184 | + * any later version. |
185 | + * |
186 | + * This program is distributed in the hope that it will be useful, but WITHOUT |
187 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
188 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
189 | + * more details. |
190 | + * |
191 | + * You should have received a copy of the GNU General Public License along with |
192 | + * this program; if not, write to the Free Software Foundation, Inc., 59 |
193 | + * Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
194 | + */ |
195 | + |
196 | +#include <linux/bitops.h> |
197 | +#include <linux/ethtool.h> |
198 | +#include <linux/mii.h> |
199 | +#include <linux/netdevice.h> |
200 | +#include <linux/slab.h> |
201 | +#include <linux/string.h> |
202 | +#include <linux/types.h> |
203 | + |
204 | +#include "atl2.h" |
205 | +#include "atl2_hw.h" |
206 | + |
207 | +extern char atl2_driver_name[]; |
208 | +extern char atl2_driver_version[]; |
209 | + |
210 | +extern int atl2_up(struct atl2_adapter *adapter); |
211 | +extern void atl2_down(struct atl2_adapter *adapter); |
212 | +extern void atl2_reinit_locked(struct atl2_adapter *adapter); |
213 | +extern s32 atl2_reset_hw(struct atl2_hw *hw); |
214 | + |
215 | +static int |
216 | +atl2_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd) |
217 | +{ |
218 | + struct atl2_adapter *adapter = netdev_priv(netdev); |
219 | + struct atl2_hw *hw = &adapter->hw; |
220 | + |
221 | + ecmd->supported = (SUPPORTED_10baseT_Half | |
222 | + SUPPORTED_10baseT_Full | |
223 | + SUPPORTED_100baseT_Half | |
224 | + SUPPORTED_100baseT_Full | |
225 | + SUPPORTED_Autoneg | |
226 | + SUPPORTED_TP); |
227 | + ecmd->advertising = ADVERTISED_TP; |
228 | + |
229 | + ecmd->advertising |= ADVERTISED_Autoneg; |
230 | + ecmd->advertising |= hw->autoneg_advertised; |
231 | + |
232 | + ecmd->port = PORT_TP; |
233 | + ecmd->phy_address = 0; |
234 | + ecmd->transceiver = XCVR_INTERNAL; |
235 | + |
236 | + if (adapter->link_speed != SPEED_0) { |
237 | + ecmd->speed = adapter->link_speed; |
238 | + if (adapter->link_duplex == FULL_DUPLEX) |
239 | + ecmd->duplex = DUPLEX_FULL; |
240 | + else |
241 | + ecmd->duplex = DUPLEX_HALF; |
242 | + } else { |
243 | + ecmd->speed = -1; |
244 | + ecmd->duplex = -1; |
245 | + } |
246 | + |
247 | + ecmd->autoneg = AUTONEG_ENABLE; |
248 | + return 0; |
249 | +} |
250 | + |
251 | +static int |
252 | +atl2_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd) |
253 | +{ |
254 | + struct atl2_adapter *adapter = netdev_priv(netdev); |
255 | + struct atl2_hw *hw = &adapter->hw; |
256 | + |
257 | + while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags)) |
258 | + msleep(1); |
259 | + |
260 | + if (ecmd->autoneg == AUTONEG_ENABLE) { |
261 | +#define MY_ADV_MASK (ADVERTISE_10_HALF| \ |
262 | + ADVERTISE_10_FULL| \ |
263 | + ADVERTISE_100_HALF| \ |
264 | + ADVERTISE_100_FULL) |
265 | + |
266 | + if ((ecmd->advertising&MY_ADV_MASK) == MY_ADV_MASK) { |
267 | + hw->MediaType = MEDIA_TYPE_AUTO_SENSOR; |
268 | + hw->autoneg_advertised = MY_ADV_MASK; |
269 | + } else if ((ecmd->advertising&MY_ADV_MASK) == ADVERTISE_100_FULL) { |
270 | + hw->MediaType = MEDIA_TYPE_100M_FULL; |
271 | + hw->autoneg_advertised = ADVERTISE_100_FULL; |
272 | + } else if ((ecmd->advertising&MY_ADV_MASK) == ADVERTISE_100_HALF) { |
273 | + hw->MediaType = MEDIA_TYPE_100M_HALF; |
274 | + hw->autoneg_advertised = ADVERTISE_100_HALF; |
275 | + } else if ((ecmd->advertising&MY_ADV_MASK) == ADVERTISE_10_FULL) { |
276 | + hw->MediaType = MEDIA_TYPE_10M_FULL; |
277 | + hw->autoneg_advertised = ADVERTISE_10_FULL; |
278 | + } else if ((ecmd->advertising&MY_ADV_MASK) == ADVERTISE_10_HALF) { |
279 | + hw->MediaType = MEDIA_TYPE_10M_HALF; |
280 | + hw->autoneg_advertised = ADVERTISE_10_HALF; |
281 | + } else { |
282 | + clear_bit(__ATL2_RESETTING, &adapter->flags); |
283 | + return -EINVAL; |
284 | + } |
285 | + ecmd->advertising = hw->autoneg_advertised | |
286 | + ADVERTISED_TP | ADVERTISED_Autoneg; |
287 | + } else { |
288 | + clear_bit(__ATL2_RESETTING, &adapter->flags); |
289 | + return -EINVAL; |
290 | + } |
291 | + |
292 | + /* reset the link */ |
293 | + if (netif_running(adapter->netdev)) { |
294 | + atl2_down(adapter); |
295 | + atl2_up(adapter); |
296 | + } else |
297 | + atl2_reset_hw(&adapter->hw); |
298 | + |
299 | + clear_bit(__ATL2_RESETTING, &adapter->flags); |
300 | + return 0; |
301 | +} |
302 | + |
303 | +static u32 |
304 | +atl2_get_tx_csum(struct net_device *netdev) |
305 | +{ |
306 | + return (netdev->features & NETIF_F_HW_CSUM) != 0; |
307 | +} |
308 | + |
309 | +static u32 |
310 | +atl2_get_msglevel(struct net_device *netdev) |
311 | +{ |
312 | + return 0; |
313 | +} |
314 | + |
315 | +/* |
316 | + * It's sane for this to be empty, but we might want to take advantage of this. |
317 | + */ |
318 | +static void |
319 | +atl2_set_msglevel(struct net_device *netdev, u32 data) |
320 | +{ |
321 | +} |
322 | + |
323 | +static int |
324 | +atl2_get_regs_len(struct net_device *netdev) |
325 | +{ |
326 | +#define ATL2_REGS_LEN 42 |
327 | + return ATL2_REGS_LEN * sizeof(u32); |
328 | +} |
329 | + |
330 | +static void |
331 | +atl2_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p) |
332 | +{ |
333 | + struct atl2_adapter *adapter = netdev_priv(netdev); |
334 | + struct atl2_hw *hw = &adapter->hw; |
335 | + u32 *regs_buff = p; |
336 | + u16 phy_data; |
337 | + |
338 | + memset(p, 0, ATL2_REGS_LEN * sizeof(u32)); |
339 | + |
340 | + regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id; |
341 | + |
342 | + regs_buff[0] = ATL2_READ_REG(hw, REG_VPD_CAP); |
343 | + regs_buff[1] = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL); |
344 | + regs_buff[2] = ATL2_READ_REG(hw, REG_SPI_FLASH_CONFIG); |
345 | + regs_buff[3] = ATL2_READ_REG(hw, REG_TWSI_CTRL); |
346 | + regs_buff[4] = ATL2_READ_REG(hw, REG_PCIE_DEV_MISC_CTRL); |
347 | + regs_buff[5] = ATL2_READ_REG(hw, REG_MASTER_CTRL); |
348 | + regs_buff[6] = ATL2_READ_REG(hw, REG_MANUAL_TIMER_INIT); |
349 | + regs_buff[7] = ATL2_READ_REG(hw, REG_IRQ_MODU_TIMER_INIT); |
350 | + regs_buff[8] = ATL2_READ_REG(hw, REG_PHY_ENABLE); |
351 | + regs_buff[9] = ATL2_READ_REG(hw, REG_CMBDISDMA_TIMER); |
352 | + regs_buff[10] = ATL2_READ_REG(hw, REG_IDLE_STATUS); |
353 | + regs_buff[11] = ATL2_READ_REG(hw, REG_MDIO_CTRL); |
354 | + regs_buff[12] = ATL2_READ_REG(hw, REG_SERDES_LOCK); |
355 | + regs_buff[13] = ATL2_READ_REG(hw, REG_MAC_CTRL); |
356 | + regs_buff[14] = ATL2_READ_REG(hw, REG_MAC_IPG_IFG); |
357 | + regs_buff[15] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR); |
358 | + regs_buff[16] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR+4); |
359 | + regs_buff[17] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE); |
360 | + regs_buff[18] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE+4); |
361 | + regs_buff[19] = ATL2_READ_REG(hw, REG_MAC_HALF_DUPLX_CTRL); |
362 | + regs_buff[20] = ATL2_READ_REG(hw, REG_MTU); |
363 | + regs_buff[21] = ATL2_READ_REG(hw, REG_WOL_CTRL); |
364 | + regs_buff[22] = ATL2_READ_REG(hw, REG_SRAM_TXRAM_END); |
365 | + regs_buff[23] = ATL2_READ_REG(hw, REG_DESC_BASE_ADDR_HI); |
366 | + regs_buff[24] = ATL2_READ_REG(hw, REG_TXD_BASE_ADDR_LO); |
367 | + regs_buff[25] = ATL2_READ_REG(hw, REG_TXD_MEM_SIZE); |
368 | + regs_buff[26] = ATL2_READ_REG(hw, REG_TXS_BASE_ADDR_LO); |
369 | + regs_buff[27] = ATL2_READ_REG(hw, REG_TXS_MEM_SIZE); |
370 | + regs_buff[28] = ATL2_READ_REG(hw, REG_RXD_BASE_ADDR_LO); |
371 | + regs_buff[29] = ATL2_READ_REG(hw, REG_RXD_BUF_NUM); |
372 | + regs_buff[30] = ATL2_READ_REG(hw, REG_DMAR); |
373 | + regs_buff[31] = ATL2_READ_REG(hw, REG_TX_CUT_THRESH); |
374 | + regs_buff[32] = ATL2_READ_REG(hw, REG_DMAW); |
375 | + regs_buff[33] = ATL2_READ_REG(hw, REG_PAUSE_ON_TH); |
376 | + regs_buff[34] = ATL2_READ_REG(hw, REG_PAUSE_OFF_TH); |
377 | + regs_buff[35] = ATL2_READ_REG(hw, REG_MB_TXD_WR_IDX); |
378 | + regs_buff[36] = ATL2_READ_REG(hw, REG_MB_RXD_RD_IDX); |
379 | + regs_buff[38] = ATL2_READ_REG(hw, REG_ISR); |
380 | + regs_buff[39] = ATL2_READ_REG(hw, REG_IMR); |
381 | + |
382 | + atl2_read_phy_reg(hw, MII_BMCR, &phy_data); |
383 | + regs_buff[40] = (u32)phy_data; |
384 | + atl2_read_phy_reg(hw, MII_BMSR, &phy_data); |
385 | + regs_buff[41] = (u32)phy_data; |
386 | +} |
387 | + |
388 | +static int |
389 | +atl2_get_eeprom_len(struct net_device *netdev) |
390 | +{ |
391 | + struct atl2_adapter *adapter = netdev_priv(netdev); |
392 | + |
393 | + if (!atl2_check_eeprom_exist(&adapter->hw)) { |
394 | + return 512; |
395 | + } else |
396 | + return 0; |
397 | +} |
398 | + |
399 | +static int |
400 | +atl2_get_eeprom(struct net_device *netdev, struct ethtool_eeprom *eeprom, u8 *bytes) |
401 | +{ |
402 | + struct atl2_adapter *adapter = netdev_priv(netdev); |
403 | + struct atl2_hw *hw = &adapter->hw; |
404 | + u32 *eeprom_buff; |
405 | + int first_dword, last_dword; |
406 | + int ret_val = 0; |
407 | + int i; |
408 | + |
409 | + if (eeprom->len == 0) |
410 | + return -EINVAL; |
411 | + |
412 | + if (atl2_check_eeprom_exist(hw)) { |
413 | + return -EINVAL; |
414 | + } |
415 | + |
416 | + eeprom->magic = hw->vendor_id | (hw->device_id << 16); |
417 | + |
418 | + first_dword = eeprom->offset >> 2; |
419 | + last_dword = (eeprom->offset + eeprom->len - 1) >> 2; |
420 | + |
421 | + eeprom_buff = kmalloc(sizeof(u32) * (last_dword - first_dword + 1), GFP_KERNEL); |
422 | + if (!eeprom_buff) |
423 | + return -ENOMEM; |
424 | + |
425 | + for (i=first_dword; i < last_dword; i++) { |
426 | + if (!atl2_read_eeprom(hw, i*4, &(eeprom_buff[i-first_dword]))) |
427 | + return -EIO; |
428 | + } |
429 | + |
430 | + memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 3), |
431 | + eeprom->len); |
432 | + kfree(eeprom_buff); |
433 | + |
434 | + return ret_val; |
435 | +} |
436 | + |
437 | +static int |
438 | +atl2_set_eeprom(struct net_device *netdev, struct ethtool_eeprom *eeprom, u8 *bytes) |
439 | +{ |
440 | + struct atl2_adapter *adapter = netdev_priv(netdev); |
441 | + struct atl2_hw *hw = &adapter->hw; |
442 | + u32 *eeprom_buff; |
443 | + u32 *ptr; |
444 | + int max_len, first_dword, last_dword, ret_val = 0; |
445 | + int i; |
446 | + |
447 | + if (eeprom->len == 0) |
448 | + return -EOPNOTSUPP; |
449 | + |
450 | + if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16))) |
451 | + return -EFAULT; |
452 | + |
453 | + max_len = 512; |
454 | + |
455 | + first_dword = eeprom->offset >> 2; |
456 | + last_dword = (eeprom->offset + eeprom->len - 1) >> 2; |
457 | + eeprom_buff = kmalloc(max_len, GFP_KERNEL); |
458 | + if (!eeprom_buff) |
459 | + return -ENOMEM; |
460 | + |
461 | + ptr = (u32 *)eeprom_buff; |
462 | + |
463 | + if (eeprom->offset & 3) { |
464 | + /* need read/modify/write of first changed EEPROM word */ |
465 | + /* only the second byte of the word is being modified */ |
466 | + if (!atl2_read_eeprom(hw, first_dword*4, &(eeprom_buff[0]))) |
467 | + return -EIO; |
468 | + ptr++; |
469 | + } |
470 | + if (((eeprom->offset + eeprom->len) & 3) ) { |
471 | + /* need read/modify/write of last changed EEPROM word */ |
472 | + /* only the first byte of the word is being modified */ |
473 | + |
474 | + if (!atl2_read_eeprom(hw, last_dword*4, &(eeprom_buff[last_dword - first_dword]))) |
475 | + return -EIO; |
476 | + } |
477 | + |
478 | + /* Device's eeprom is always little-endian, word addressable */ |
479 | + memcpy(ptr, bytes, eeprom->len); |
480 | + |
481 | + for (i = 0; i < last_dword - first_dword + 1; i++) { |
482 | + if (!atl2_write_eeprom(hw, ((first_dword+i)*4), eeprom_buff[i])) |
483 | + return -EIO; |
484 | + } |
485 | + |
486 | + kfree(eeprom_buff); |
487 | + return ret_val; |
488 | +} |
489 | + |
490 | +static void |
491 | +atl2_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *drvinfo) |
492 | +{ |
493 | + struct atl2_adapter *adapter = netdev_priv(netdev); |
494 | + |
495 | + strncpy(drvinfo->driver, atl2_driver_name, 32); |
496 | + strncpy(drvinfo->version, atl2_driver_version, 32); |
497 | + strncpy(drvinfo->fw_version, "L2", 32); |
498 | + strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32); |
499 | + drvinfo->n_stats = 0; |
500 | + drvinfo->testinfo_len = 0; |
501 | + drvinfo->regdump_len = atl2_get_regs_len(netdev); |
502 | + drvinfo->eedump_len = atl2_get_eeprom_len(netdev); |
503 | +} |
504 | + |
505 | +static void |
506 | +atl2_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) |
507 | +{ |
508 | + struct atl2_adapter *adapter = netdev_priv(netdev); |
509 | + |
510 | + wol->supported = WAKE_MAGIC; |
511 | + wol->wolopts = 0; |
512 | + |
513 | + if (adapter->wol & ATL2_WUFC_EX) |
514 | + wol->wolopts |= WAKE_UCAST; |
515 | + if (adapter->wol & ATL2_WUFC_MC) |
516 | + wol->wolopts |= WAKE_MCAST; |
517 | + if (adapter->wol & ATL2_WUFC_BC) |
518 | + wol->wolopts |= WAKE_BCAST; |
519 | + if (adapter->wol & ATL2_WUFC_MAG) |
520 | + wol->wolopts |= WAKE_MAGIC; |
521 | + if (adapter->wol & ATL2_WUFC_LNKC) |
522 | + wol->wolopts |= WAKE_PHY; |
523 | +} |
524 | + |
525 | +static int |
526 | +atl2_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) |
527 | +{ |
528 | + struct atl2_adapter *adapter = netdev_priv(netdev); |
529 | + |
530 | + if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE)) |
531 | + return -EOPNOTSUPP; |
532 | + |
533 | + if (wol->wolopts & (WAKE_MCAST|WAKE_BCAST|WAKE_MCAST)) |
534 | + return -EOPNOTSUPP; |
535 | + |
536 | + /* these settings will always override what we currently have */ |
537 | + adapter->wol = 0; |
538 | + |
539 | + if (wol->wolopts & WAKE_MAGIC) |
540 | + adapter->wol |= ATL2_WUFC_MAG; |
541 | + if (wol->wolopts & WAKE_PHY) |
542 | + adapter->wol |= ATL2_WUFC_LNKC; |
543 | + |
544 | + return 0; |
545 | +} |
546 | + |
547 | +static int |
548 | +atl2_nway_reset(struct net_device *netdev) |
549 | +{ |
550 | + struct atl2_adapter *adapter = netdev_priv(netdev); |
551 | + if (netif_running(netdev)) |
552 | + atl2_reinit_locked(adapter); |
553 | + return 0; |
554 | +} |
555 | + |
556 | +static struct ethtool_ops atl2_ethtool_ops = { |
557 | + .get_settings = atl2_get_settings, |
558 | + .set_settings = atl2_set_settings, |
559 | + .get_drvinfo = atl2_get_drvinfo, |
560 | + .get_regs_len = atl2_get_regs_len, |
561 | + .get_regs = atl2_get_regs, |
562 | + .get_wol = atl2_get_wol, |
563 | + .set_wol = atl2_set_wol, |
564 | + .get_msglevel = atl2_get_msglevel, |
565 | + .set_msglevel = atl2_set_msglevel, |
566 | + .nway_reset = atl2_nway_reset, |
567 | + .get_link = ethtool_op_get_link, |
568 | + .get_eeprom_len = atl2_get_eeprom_len, |
569 | + .get_eeprom = atl2_get_eeprom, |
570 | + .set_eeprom = atl2_set_eeprom, |
571 | + .get_tx_csum = atl2_get_tx_csum, |
572 | + .get_sg = ethtool_op_get_sg, |
573 | + .set_sg = ethtool_op_set_sg, |
574 | +#ifdef NETIF_F_TSO |
575 | + .get_tso = ethtool_op_get_tso, |
576 | +#endif |
577 | +#if 0 //FIXME: not implemented? |
578 | +//#ifdef ETHTOOL_GPERMADDR |
579 | + .get_perm_addr = ethtool_op_get_perm_addr, |
580 | +#endif |
581 | +}; |
582 | + |
583 | +void |
584 | +atl2_set_ethtool_ops(struct net_device *netdev) |
585 | +{ |
586 | + SET_ETHTOOL_OPS(netdev, &atl2_ethtool_ops); |
587 | +} |
588 | Index: linux-2.6.26.noarch/drivers/net/atl2/atl2_hw.c |
589 | =================================================================== |
590 | --- /dev/null |
591 | +++ linux-2.6.26.noarch/drivers/net/atl2/atl2_hw.c |
592 | @@ -0,0 +1,760 @@ |
593 | +/* atl2_hw.c -- atl2 hardware control functions |
594 | + * |
595 | + * Copyright(c) 2007 Atheros Corporation. All rights reserved. |
596 | + * Copyright(c) 2006 xiong huang <xiong.huang@atheros.com> |
597 | + * Copyright(c) 2007 Chris Snook <csnook@redhat.com> |
598 | + * |
599 | + * Derived from Intel e1000 driver |
600 | + * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. |
601 | + * |
602 | + * This program is free software; you can redistribute it and/or modify it |
603 | + * under the terms of the GNU General Public License as published by the Free |
604 | + * Software Foundation; either version 2 of the License, or (at your option) |
605 | + * any later version. |
606 | + * |
607 | + * This program is distributed in the hope that it will be useful, but WITHOUT |
608 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
609 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
610 | + * more details. |
611 | + * |
612 | + * You should have received a copy of the GNU General Public License along with |
613 | + * this program; if not, write to the Free Software Foundation, Inc., 59 |
614 | + * Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
615 | + */ |
616 | + |
617 | +#include <asm/processor.h> |
618 | +#include <linux/crc32.h> |
619 | +#include <linux/etherdevice.h> |
620 | +#include <linux/mii.h> |
621 | +#include <linux/string.h> |
622 | + |
623 | +#include "atl2.h" |
624 | +#include "atl2_hw.h" |
625 | + |
626 | +#define LBYTESWAP( a ) ( ( ( (a) & 0x00ff00ff ) << 8 ) | ( ( (a) & 0xff00ff00 ) >> 8 ) ) |
627 | +#define LONGSWAP( a ) ( ( LBYTESWAP( a ) << 16 ) | ( LBYTESWAP( a ) >> 16 ) ) |
628 | +#define SHORTSWAP( a ) ( ( (a) << 8 ) | ( (a) >> 8 ) ) |
629 | + |
630 | +/* |
631 | + * Reset the transmit and receive units; mask and clear all interrupts. |
632 | + * |
633 | + * hw - Struct containing variables accessed by shared code |
634 | + * return : ATL2_SUCCESS or idle status (if error) |
635 | + */ |
636 | +s32 |
637 | +atl2_reset_hw(struct atl2_hw *hw) |
638 | +{ |
639 | + u32 icr; |
640 | + u16 pci_cfg_cmd_word; |
641 | + int i; |
642 | + |
643 | + /* Workaround for PCI problem when BIOS sets MMRBC incorrectly. */ |
644 | + atl2_read_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word); |
645 | + if ((pci_cfg_cmd_word & |
646 | + (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) != |
647 | + (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) { |
648 | + pci_cfg_cmd_word |= |
649 | + (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER); |
650 | + atl2_write_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word); |
651 | + } |
652 | + |
653 | + /* Clear Interrupt mask to stop board from generating |
654 | + * interrupts & Clear any pending interrupt events |
655 | + */ |
656 | +// ATL2_WRITE_REG(hw, REG_IMR, 0); |
657 | +// ATL2_WRITE_REG(hw, REG_ISR, 0xffffffff); |
658 | + |
659 | + /* Issue Soft Reset to the MAC. This will reset the chip's |
660 | + * transmit, receive, DMA. It will not effect |
661 | + * the current PCI configuration. The global reset bit is self- |
662 | + * clearing, and should clear within a microsecond. |
663 | + */ |
664 | + ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_SOFT_RST); |
665 | + wmb(); |
666 | + msec_delay(1); // delay about 1ms |
667 | + |
668 | + /* Wait at least 10ms for All module to be Idle */ |
669 | + for (i=0; i < 10; i++) { |
670 | + icr = ATL2_READ_REG(hw, REG_IDLE_STATUS); |
671 | + if (!icr) |
672 | + break; |
673 | + msec_delay(1); // delay 1 ms |
674 | + cpu_relax(); |
675 | + } |
676 | + |
677 | + if (icr) |
678 | + return icr; |
679 | + |
680 | + return ATL2_SUCCESS; |
681 | +} |
682 | + |
683 | +#define CUSTOM_SPI_CS_SETUP 2 |
684 | +#define CUSTOM_SPI_CLK_HI 2 |
685 | +#define CUSTOM_SPI_CLK_LO 2 |
686 | +#define CUSTOM_SPI_CS_HOLD 2 |
687 | +#define CUSTOM_SPI_CS_HI 3 |
688 | + |
689 | +static struct atl2_spi_flash_dev flash_table[] = |
690 | +{ |
691 | +/* manu_name WRSR READ PROGRAM WREN WRDI RDSR RDID SECTOR_ERASE CHIP_ERASE */ |
692 | + {"Atmel", 0x0, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62 }, |
693 | + {"SST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60 }, |
694 | + {"ST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xAB, 0xD8, 0xC7 }, |
695 | +}; |
696 | + |
697 | +static bool |
698 | +atl2_spi_read(struct atl2_hw* hw, u32 addr, u32* buf) |
699 | +{ |
700 | + int i; |
701 | + u32 value; |
702 | + |
703 | + ATL2_WRITE_REG(hw, REG_SPI_DATA, 0); |
704 | + ATL2_WRITE_REG(hw, REG_SPI_ADDR, addr); |
705 | + |
706 | + value = SPI_FLASH_CTRL_WAIT_READY | |
707 | + (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) << SPI_FLASH_CTRL_CS_SETUP_SHIFT | |
708 | + (CUSTOM_SPI_CLK_HI & SPI_FLASH_CTRL_CLK_HI_MASK) << SPI_FLASH_CTRL_CLK_HI_SHIFT | |
709 | + (CUSTOM_SPI_CLK_LO & SPI_FLASH_CTRL_CLK_LO_MASK) << SPI_FLASH_CTRL_CLK_LO_SHIFT | |
710 | + (CUSTOM_SPI_CS_HOLD & SPI_FLASH_CTRL_CS_HOLD_MASK) << SPI_FLASH_CTRL_CS_HOLD_SHIFT | |
711 | + (CUSTOM_SPI_CS_HI & SPI_FLASH_CTRL_CS_HI_MASK) << SPI_FLASH_CTRL_CS_HI_SHIFT | |
712 | + (0x1 & SPI_FLASH_CTRL_INS_MASK) << SPI_FLASH_CTRL_INS_SHIFT; |
713 | + |
714 | + ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value); |
715 | + |
716 | + value |= SPI_FLASH_CTRL_START; |
717 | + |
718 | + ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value); |
719 | + |
720 | + for (i = 0; i < 10; i++) |
721 | + { |
722 | + msec_delay(1); // 1ms |
723 | + value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL); |
724 | + if (!(value & SPI_FLASH_CTRL_START)) |
725 | + break; |
726 | + } |
727 | + |
728 | + if (value & SPI_FLASH_CTRL_START) |
729 | + return false; |
730 | + |
731 | + *buf = ATL2_READ_REG(hw, REG_SPI_DATA); |
732 | + |
733 | + return true; |
734 | +} |
735 | + |
736 | +/* |
737 | + * get_permanent_address |
738 | + * return 0 if get valid mac address, |
739 | + */ |
740 | +static int |
741 | +get_permanent_address(struct atl2_hw *hw) |
742 | +{ |
743 | + u32 Addr[2]; |
744 | + u32 i, Control; |
745 | + u16 Register; |
746 | + u8 EthAddr[NODE_ADDRESS_SIZE]; |
747 | + bool KeyValid; |
748 | + |
749 | + if (is_valid_ether_addr(hw->perm_mac_addr)) |
750 | + return 0; |
751 | + |
752 | + Addr[0] = 0; |
753 | + Addr[1] = 0; |
754 | + |
755 | + if (!atl2_check_eeprom_exist(hw)) { /* eeprom exists */ |
756 | + Register = 0; |
757 | + KeyValid = false; |
758 | + |
759 | + /* Read out all EEPROM content */ |
760 | + i = 0; |
761 | + while (1) { |
762 | + if (atl2_read_eeprom(hw, i + 0x100, &Control)) { |
763 | + if (KeyValid) { |
764 | + if (Register == REG_MAC_STA_ADDR) |
765 | + Addr[0] = Control; |
766 | + else if (Register == (REG_MAC_STA_ADDR + 4)) |
767 | + Addr[1] = Control; |
768 | + KeyValid = false; |
769 | + } else if ((Control & 0xff) == 0x5A) { |
770 | + KeyValid = true; |
771 | + Register = (u16) (Control >> 16); |
772 | + } else { |
773 | + break; /* assume data end while encount an invalid KEYWORD */ |
774 | + } |
775 | + } else { |
776 | + break; /* read error */ |
777 | + } |
778 | + i += 4; |
779 | + } |
780 | + |
781 | + *(u32*) &EthAddr[2] = LONGSWAP(Addr[0]); |
782 | + *(u16*) &EthAddr[0] = SHORTSWAP(*(u16*)&Addr[1]); |
783 | + |
784 | + if (is_valid_ether_addr(EthAddr)) { |
785 | + memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE); |
786 | + return 0; |
787 | + } |
788 | + return 1; |
789 | + } |
790 | + |
791 | + // see if SPI FLAHS exist ? |
792 | + Addr[0] = 0; |
793 | + Addr[1] = 0; |
794 | + Register = 0; |
795 | + KeyValid = false; |
796 | + i = 0; |
797 | + while (1) { |
798 | + if (atl2_spi_read(hw, i + 0x1f000, &Control)) { |
799 | + if (KeyValid) { |
800 | + if (Register == REG_MAC_STA_ADDR) |
801 | + Addr[0] = Control; |
802 | + else if (Register == (REG_MAC_STA_ADDR + 4)) |
803 | + Addr[1] = Control; |
804 | + KeyValid = false; |
805 | + } else if ((Control & 0xff) == 0x5A) { |
806 | + KeyValid = true; |
807 | + Register = (u16) (Control >> 16); |
808 | + } else { |
809 | + break; /* data end */ |
810 | + } |
811 | + } else { |
812 | + break; /* read error */ |
813 | + } |
814 | + i += 4; |
815 | + } |
816 | + |
817 | + *(u32*) &EthAddr[2] = LONGSWAP(Addr[0]); |
818 | + *(u16*) &EthAddr[0] = SHORTSWAP(*(u16*)&Addr[1]); |
819 | + if (is_valid_ether_addr(EthAddr)) { |
820 | + memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE); |
821 | + return 0; |
822 | + } |
823 | + /* maybe MAC-address is from BIOS */ |
824 | + Addr[0] = ATL2_READ_REG(hw,REG_MAC_STA_ADDR); |
825 | + Addr[1] = ATL2_READ_REG(hw,REG_MAC_STA_ADDR+4); |
826 | + *(u32*) &EthAddr[2] = LONGSWAP(Addr[0]); |
827 | + *(u16*) &EthAddr[0] = SHORTSWAP(*(u16*)&Addr[1]); |
828 | + |
829 | + if (is_valid_ether_addr(EthAddr)) { |
830 | + memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE); |
831 | + return 0; |
832 | + } |
833 | + |
834 | + return 1; |
835 | +} |
836 | + |
837 | +/* |
838 | + * Reads the adapter's MAC address from the EEPROM |
839 | + * |
840 | + * hw - Struct containing variables accessed by shared code |
841 | + */ |
842 | +s32 |
843 | +atl2_read_mac_addr(struct atl2_hw *hw) |
844 | +{ |
845 | + u16 i; |
846 | + |
847 | + if (get_permanent_address(hw)) { |
848 | + // for test |
849 | + hw->perm_mac_addr[0] = 0x00; |
850 | + hw->perm_mac_addr[1] = 0x13; |
851 | + hw->perm_mac_addr[2] = 0x74; |
852 | + hw->perm_mac_addr[3] = 0x00; |
853 | + hw->perm_mac_addr[4] = 0x5c; |
854 | + hw->perm_mac_addr[5] = 0x38; |
855 | + } |
856 | + |
857 | + for(i = 0; i < NODE_ADDRESS_SIZE; i++) |
858 | + hw->mac_addr[i] = hw->perm_mac_addr[i]; |
859 | + |
860 | + return ATL2_SUCCESS; |
861 | +} |
862 | + |
863 | +/* |
864 | + * Hashes an address to determine its location in the multicast table |
865 | + * |
866 | + * hw - Struct containing variables accessed by shared code |
867 | + * mc_addr - the multicast address to hash |
868 | + * |
869 | + * atl2_hash_mc_addr |
870 | + * purpose |
871 | + * set hash value for a multicast address |
872 | + * hash calcu processing : |
873 | + * 1. calcu 32bit CRC for multicast address |
874 | + * 2. reverse crc with MSB to LSB |
875 | + */ |
876 | +u32 |
877 | +atl2_hash_mc_addr(struct atl2_hw *hw, u8 *mc_addr) |
878 | +{ |
879 | + u32 crc32, value=0; |
880 | + int i; |
881 | + |
882 | + crc32 = ether_crc_le(6, mc_addr); |
883 | + |
884 | + for (i=0; i<32; i++) |
885 | + value |= (((crc32>>i)&1)<<(31-i)); |
886 | + |
887 | + return value; |
888 | +} |
889 | + |
890 | +/* |
891 | + * Sets the bit in the multicast table corresponding to the hash value. |
892 | + * |
893 | + * hw - Struct containing variables accessed by shared code |
894 | + * hash_value - Multicast address hash value |
895 | + */ |
896 | +void |
897 | +atl2_hash_set(struct atl2_hw *hw, u32 hash_value) |
898 | +{ |
899 | + u32 hash_bit, hash_reg; |
900 | + u32 mta; |
901 | + |
902 | + /* The HASH Table is a register array of 2 32-bit registers. |
903 | + * It is treated like an array of 64 bits. We want to set |
904 | + * bit BitArray[hash_value]. So we figure out what register |
905 | + * the bit is in, read it, OR in the new bit, then write |
906 | + * back the new value. The register is determined by the |
907 | + * upper 7 bits of the hash value and the bit within that |
908 | + * register are determined by the lower 5 bits of the value. |
909 | + */ |
910 | + hash_reg = (hash_value >> 31) & 0x1; |
911 | + hash_bit = (hash_value >> 26) & 0x1F; |
912 | + |
913 | + mta = ATL2_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg); |
914 | + |
915 | + mta |= (1 << hash_bit); |
916 | + |
917 | + ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta); |
918 | +} |
919 | + |
920 | +/* |
921 | + * atl2_init_pcie - init PCIE module |
922 | + */ |
923 | +static void |
924 | +atl2_init_pcie(struct atl2_hw *hw) |
925 | +{ |
926 | + u32 value; |
927 | + value = LTSSM_TEST_MODE_DEF; |
928 | + ATL2_WRITE_REG(hw, REG_LTSSM_TEST_MODE, value); |
929 | + |
930 | + value = PCIE_DLL_TX_CTRL1_DEF; |
931 | + ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, value); |
932 | +} |
933 | + |
934 | +void |
935 | +atl2_init_flash_opcode(struct atl2_hw *hw) |
936 | +{ |
937 | + if (hw->flash_vendor >= ARRAY_SIZE(flash_table)) { |
938 | + hw->flash_vendor = 0; // ATMEL |
939 | + } |
940 | + // Init OP table |
941 | + ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_PROGRAM, flash_table[hw->flash_vendor].cmdPROGRAM); |
942 | + ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_SC_ERASE, flash_table[hw->flash_vendor].cmdSECTOR_ERASE); |
943 | + ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_CHIP_ERASE, flash_table[hw->flash_vendor].cmdCHIP_ERASE); |
944 | + ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDID, flash_table[hw->flash_vendor].cmdRDID); |
945 | + ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WREN, flash_table[hw->flash_vendor].cmdWREN); |
946 | + ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDSR, flash_table[hw->flash_vendor].cmdRDSR); |
947 | + ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WRSR, flash_table[hw->flash_vendor].cmdWRSR); |
948 | + ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_READ, flash_table[hw->flash_vendor].cmdREAD); |
949 | +} |
950 | + |
951 | +/******************************************************************** |
952 | +* Performs basic configuration of the adapter. |
953 | +* |
954 | +* hw - Struct containing variables accessed by shared code |
955 | +* Assumes that the controller has previously been reset and is in a |
956 | +* post-reset uninitialized state. Initializes multicast table, |
957 | +* and Calls routines to setup link |
958 | +* Leaves the transmit and receive units disabled and uninitialized. |
959 | +********************************************************************/ |
960 | +s32 |
961 | +atl2_init_hw(struct atl2_hw *hw) |
962 | +{ |
963 | + u32 ret_val = 0; |
964 | + |
965 | + atl2_init_pcie(hw); |
966 | + |
967 | + /* Zero out the Multicast HASH table */ |
968 | + /* clear the old settings from the multicast hash table */ |
969 | + ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0); |
970 | + ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0); |
971 | + |
972 | + atl2_init_flash_opcode(hw); |
973 | + |
974 | + ret_val = atl2_phy_init(hw); |
975 | + |
976 | + return ret_val; |
977 | +} |
978 | + |
979 | +/* |
980 | + * Detects the current speed and duplex settings of the hardware. |
981 | + * |
982 | + * hw - Struct containing variables accessed by shared code |
983 | + * speed - Speed of the connection |
984 | + * duplex - Duplex setting of the connection |
985 | + */ |
986 | +s32 |
987 | +atl2_get_speed_and_duplex(struct atl2_hw *hw, u16 *speed, u16 *duplex) |
988 | +{ |
989 | + s32 ret_val; |
990 | + u16 phy_data; |
991 | + |
992 | + // ; --- Read PHY Specific Status Register (17) |
993 | + ret_val = atl2_read_phy_reg(hw, MII_AT001_PSSR, &phy_data); |
994 | + if (ret_val) |
995 | + return ret_val; |
996 | + |
997 | + if (!(phy_data & MII_AT001_PSSR_SPD_DPLX_RESOLVED)) |
998 | + return ATL2_ERR_PHY_RES; |
999 | + |
1000 | + switch(phy_data & MII_AT001_PSSR_SPEED) { |
1001 | + case MII_AT001_PSSR_100MBS: |
1002 | + *speed = SPEED_100; |
1003 | + break; |
1004 | + case MII_AT001_PSSR_10MBS: |
1005 | + *speed = SPEED_10; |
1006 | + break; |
1007 | + default: |
1008 | + return ATL2_ERR_PHY_SPEED; |
1009 | + break; |
1010 | + } |
1011 | + |
1012 | + if (phy_data & MII_AT001_PSSR_DPLX) { |
1013 | + *duplex = FULL_DUPLEX; |
1014 | + } else { |
1015 | + *duplex = HALF_DUPLEX; |
1016 | + } |
1017 | + |
1018 | + return ATL2_SUCCESS; |
1019 | +} |
1020 | + |
1021 | +/* |
1022 | + * Reads the value from a PHY register |
1023 | + * hw - Struct containing variables accessed by shared code |
1024 | + * reg_addr - address of the PHY register to read |
1025 | + */ |
1026 | +s32 |
1027 | +atl2_read_phy_reg(struct atl2_hw *hw, u16 reg_addr, u16 *phy_data) |
1028 | +{ |
1029 | + u32 val; |
1030 | + int i; |
1031 | + |
1032 | + val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT | |
1033 | + MDIO_START | |
1034 | + MDIO_SUP_PREAMBLE | |
1035 | + MDIO_RW | |
1036 | + MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT; |
1037 | + ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val); |
1038 | + |
1039 | + wmb(); |
1040 | + |
1041 | + for (i=0; i<MDIO_WAIT_TIMES; i++) { |
1042 | + usec_delay(2); |
1043 | + val = ATL2_READ_REG(hw, REG_MDIO_CTRL); |
1044 | + if (!(val & (MDIO_START | MDIO_BUSY))) { |
1045 | + break; |
1046 | + } |
1047 | + wmb(); |
1048 | + } |
1049 | + if (!(val & (MDIO_START | MDIO_BUSY))) { |
1050 | + *phy_data = (u16)val; |
1051 | + return ATL2_SUCCESS; |
1052 | + } |
1053 | + |
1054 | + return ATL2_ERR_PHY; |
1055 | +} |
1056 | + |
1057 | +/* |
1058 | + * Writes a value to a PHY register |
1059 | + * hw - Struct containing variables accessed by shared code |
1060 | + * reg_addr - address of the PHY register to write |
1061 | + * data - data to write to the PHY |
1062 | + */ |
1063 | +s32 |
1064 | +atl2_write_phy_reg(struct atl2_hw *hw, u32 reg_addr, u16 phy_data) |
1065 | +{ |
1066 | + int i; |
1067 | + u32 val; |
1068 | + |
1069 | + val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT | |
1070 | + (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT | |
1071 | + MDIO_SUP_PREAMBLE | |
1072 | + MDIO_START | |
1073 | + MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT; |
1074 | + ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val); |
1075 | + |
1076 | + wmb(); |
1077 | + |
1078 | + for (i=0; i<MDIO_WAIT_TIMES; i++) { |
1079 | + usec_delay(2); |
1080 | + val = ATL2_READ_REG(hw, REG_MDIO_CTRL); |
1081 | + if (!(val & (MDIO_START | MDIO_BUSY))) { |
1082 | + break; |
1083 | + } |
1084 | + wmb(); |
1085 | + } |
1086 | + |
1087 | + if (!(val & (MDIO_START | MDIO_BUSY))) |
1088 | + return ATL2_SUCCESS; |
1089 | + |
1090 | + return ATL2_ERR_PHY; |
1091 | +} |
1092 | + |
1093 | +/* |
1094 | + * Configures PHY autoneg and flow control advertisement settings |
1095 | + * |
1096 | + * hw - Struct containing variables accessed by shared code |
1097 | + */ |
1098 | +static s32 |
1099 | +atl2_phy_setup_autoneg_adv(struct atl2_hw *hw) |
1100 | +{ |
1101 | + s32 ret_val; |
1102 | + s16 mii_autoneg_adv_reg; |
1103 | + |
1104 | + /* Read the MII Auto-Neg Advertisement Register (Address 4). */ |
1105 | + mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK; |
1106 | + |
1107 | + /* Need to parse autoneg_advertised and set up |
1108 | + * the appropriate PHY registers. First we will parse for |
1109 | + * autoneg_advertised software override. Since we can advertise |
1110 | + * a plethora of combinations, we need to check each bit |
1111 | + * individually. |
1112 | + */ |
1113 | + |
1114 | + /* First we clear all the 10/100 mb speed bits in the Auto-Neg |
1115 | + * Advertisement Register (Address 4) and the 1000 mb speed bits in |
1116 | + * the 1000Base-T Control Register (Address 9). |
1117 | + */ |
1118 | + mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK; |
1119 | + |
1120 | + /* Need to parse MediaType and setup the |
1121 | + * appropriate PHY registers. |
1122 | + */ |
1123 | + switch (hw->MediaType) { |
1124 | + case MEDIA_TYPE_AUTO_SENSOR: |
1125 | + mii_autoneg_adv_reg |= |
1126 | + (MII_AR_10T_HD_CAPS | |
1127 | + MII_AR_10T_FD_CAPS | |
1128 | + MII_AR_100TX_HD_CAPS | |
1129 | + MII_AR_100TX_FD_CAPS); |
1130 | + hw->autoneg_advertised = |
1131 | + ADVERTISE_10_HALF | |
1132 | + ADVERTISE_10_FULL | |
1133 | + ADVERTISE_100_HALF | |
1134 | + ADVERTISE_100_FULL; |
1135 | + break; |
1136 | + case MEDIA_TYPE_100M_FULL: |
1137 | + mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS; |
1138 | + hw->autoneg_advertised = ADVERTISE_100_FULL; |
1139 | + break; |
1140 | + case MEDIA_TYPE_100M_HALF: |
1141 | + mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS; |
1142 | + hw->autoneg_advertised = ADVERTISE_100_HALF; |
1143 | + break; |
1144 | + case MEDIA_TYPE_10M_FULL: |
1145 | + mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS; |
1146 | + hw->autoneg_advertised = ADVERTISE_10_FULL; |
1147 | + break; |
1148 | + default: |
1149 | + mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS; |
1150 | + hw->autoneg_advertised = ADVERTISE_10_HALF; |
1151 | + break; |
1152 | + } |
1153 | + |
1154 | + /* flow control fixed to enable all */ |
1155 | + mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE); |
1156 | + |
1157 | + hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg; |
1158 | + |
1159 | + ret_val = atl2_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg); |
1160 | + |
1161 | + if(ret_val) |
1162 | + return ret_val; |
1163 | + |
1164 | + return ATL2_SUCCESS; |
1165 | +} |
1166 | + |
1167 | +/* |
1168 | + * Resets the PHY and make all config validate |
1169 | + * |
1170 | + * hw - Struct containing variables accessed by shared code |
1171 | + * |
1172 | + * Sets bit 15 and 12 of the MII Control regiser (for F001 bug) |
1173 | + */ |
1174 | +static s32 |
1175 | +atl2_phy_commit(struct atl2_hw *hw) |
1176 | +{ |
1177 | + s32 ret_val; |
1178 | + u16 phy_data; |
1179 | + |
1180 | +/* FIXME: use or remove -- CHS |
1181 | + if (hw->MediaType == MEDIA_TYPE_AUTO_SENSOR) { |
1182 | + phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN; |
1183 | + } else { |
1184 | + switch (hw->MediaType) |
1185 | + { |
1186 | + case MEDIA_TYPE_100M_FULL: |
1187 | + phy_data = MII_CR_FULL_DUPLEX|MII_CR_SPEED_100|MII_CR_RESET; |
1188 | + break; |
1189 | + case MEDIA_TYPE_100M_HALF: |
1190 | + phy_data = MII_CR_SPEED_100|MII_CR_RESET; |
1191 | + break; |
1192 | + case MEDIA_TYPE_10M_FULL: |
1193 | + phy_data = MII_CR_FULL_DUPLEX|MII_CR_SPEED_10|MII_CR_RESET; |
1194 | + break; |
1195 | + default: // MEDIA_TYPE_10M_HALF: |
1196 | + phy_data = MII_CR_SPEED_10|MII_CR_RESET; |
1197 | + break; |
1198 | + } |
1199 | + } |
1200 | +*/ |
1201 | + phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG; |
1202 | + ret_val = atl2_write_phy_reg(hw, MII_BMCR, phy_data); |
1203 | + if (ret_val) { // bug fixed |
1204 | + u32 val; |
1205 | + int i; |
1206 | + /* pcie serdes link may be down ! */ |
1207 | + for (i=0; i < 25; i++) { |
1208 | + msec_delay(1); |
1209 | + val = ATL2_READ_REG(hw, REG_MDIO_CTRL); |
1210 | + if (!(val & (MDIO_START | MDIO_BUSY))) |
1211 | + break; |
1212 | + } |
1213 | + |
1214 | + if (0 != (val & (MDIO_START | MDIO_BUSY))) { |
1215 | + printk(KERN_ERR "atl2: PCIe link down for at least 25ms !\n"); |
1216 | + return ret_val; |
1217 | + } |
1218 | + } |
1219 | + return ATL2_SUCCESS; |
1220 | +} |
1221 | + |
1222 | +s32 |
1223 | +atl2_phy_init(struct atl2_hw *hw) |
1224 | +{ |
1225 | + s32 ret_val; |
1226 | + u16 phy_val; |
1227 | + |
1228 | + if (hw->phy_configured) |
1229 | + return 0; |
1230 | + |
1231 | + /* Enable PHY */ |
1232 | + ATL2_WRITE_REGW(hw, REG_PHY_ENABLE, 1); |
1233 | + ATL2_WRITE_FLUSH(hw); |
1234 | + msec_delay(1); |
1235 | + |
1236 | + /* check if the PHY is in powersaving mode */ |
1237 | + atl2_write_phy_reg(hw, MII_DBG_ADDR, 0); |
1238 | + atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val); |
1239 | + |
1240 | + /* 024E / 124E 0r 0274 / 1274 ? */ |
1241 | + if (phy_val & 0x1000) { |
1242 | + phy_val &= ~0x1000; |
1243 | + atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val); |
1244 | + } |
1245 | + |
1246 | + msec_delay(1); |
1247 | + |
1248 | + |
1249 | + /*Enable PHY LinkChange Interrupt */ |
1250 | + ret_val = atl2_write_phy_reg(hw, 18, 0xC00); |
1251 | + if (ret_val) |
1252 | + return ret_val; |
1253 | + |
1254 | + /* setup AutoNeg parameters */ |
1255 | + ret_val = atl2_phy_setup_autoneg_adv(hw); |
1256 | + if(ret_val) |
1257 | + return ret_val; |
1258 | + |
1259 | + /* SW.Reset & En-Auto-Neg to restart Auto-Neg */ |
1260 | + ret_val = atl2_phy_commit(hw); |
1261 | + if (ret_val) |
1262 | + return ret_val; |
1263 | + |
1264 | + hw->phy_configured = true; |
1265 | + |
1266 | + return ret_val; |
1267 | +} |
1268 | + |
1269 | +void |
1270 | +atl2_set_mac_addr(struct atl2_hw *hw) |
1271 | +{ |
1272 | + u32 value; |
1273 | + // 00-0B-6A-F6-00-DC |
1274 | + // 0: 6AF600DC 1: 000B |
1275 | + // low dword |
1276 | + value = (((u32)hw->mac_addr[2]) << 24) | |
1277 | + (((u32)hw->mac_addr[3]) << 16) | |
1278 | + (((u32)hw->mac_addr[4]) << 8 ) | |
1279 | + (((u32)hw->mac_addr[5]) ) ; |
1280 | + ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value); |
1281 | + // hight dword |
1282 | + value = (((u32)hw->mac_addr[0]) << 8 ) | |
1283 | + (((u32)hw->mac_addr[1]) ) ; |
1284 | + ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value); |
1285 | +} |
1286 | + |
1287 | +/* |
1288 | + * check_eeprom_exist |
1289 | + * return 0 if eeprom exist |
1290 | + */ |
1291 | +int |
1292 | +atl2_check_eeprom_exist(struct atl2_hw *hw) |
1293 | +{ |
1294 | + u32 value; |
1295 | + |
1296 | + value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL); |
1297 | + if (value & SPI_FLASH_CTRL_EN_VPD) { |
1298 | + value &= ~SPI_FLASH_CTRL_EN_VPD; |
1299 | + ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value); |
1300 | + } |
1301 | + value = ATL2_READ_REGW(hw, REG_PCIE_CAP_LIST); |
1302 | + return ((value & 0xFF00) == 0x6C00) ? 0 : 1; |
1303 | +} |
1304 | + |
1305 | +// FIXME: This doesn't look right. -- CHS |
1306 | +bool |
1307 | +atl2_write_eeprom(struct atl2_hw *hw, u32 offset, u32 value) |
1308 | +{ |
1309 | + return true; |
1310 | +} |
1311 | + |
1312 | +bool |
1313 | +atl2_read_eeprom(struct atl2_hw *hw, u32 Offset, u32 *pValue) |
1314 | +{ |
1315 | + int i; |
1316 | + u32 Control; |
1317 | + |
1318 | + if (Offset & 0x3) |
1319 | + return false; /* address do not align */ |
1320 | + |
1321 | + ATL2_WRITE_REG(hw, REG_VPD_DATA, 0); |
1322 | + Control = (Offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT; |
1323 | + ATL2_WRITE_REG(hw, REG_VPD_CAP, Control); |
1324 | + |
1325 | + for (i = 0; i < 10; i++) { |
1326 | + msec_delay(2); |
1327 | + Control = ATL2_READ_REG(hw, REG_VPD_CAP); |
1328 | + if (Control & VPD_CAP_VPD_FLAG) |
1329 | + break; |
1330 | + } |
1331 | + |
1332 | + if (Control & VPD_CAP_VPD_FLAG) { |
1333 | + *pValue = ATL2_READ_REG(hw, REG_VPD_DATA); |
1334 | + return true; |
1335 | + } |
1336 | + return false; /* timeout */ |
1337 | +} |
1338 | + |
1339 | +void |
1340 | +atl2_force_ps(struct atl2_hw *hw) |
1341 | +{ |
1342 | + u16 phy_val; |
1343 | + |
1344 | + atl2_write_phy_reg(hw, MII_DBG_ADDR, 0); |
1345 | + atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val); |
1346 | + atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val | 0x1000); |
1347 | + |
1348 | + atl2_write_phy_reg(hw, MII_DBG_ADDR, 2); |
1349 | + atl2_write_phy_reg(hw, MII_DBG_DATA, 0x3000); |
1350 | + atl2_write_phy_reg(hw, MII_DBG_ADDR, 3); |
1351 | + atl2_write_phy_reg(hw, MII_DBG_DATA, 0); |
1352 | +} |
1353 | Index: linux-2.6.26.noarch/drivers/net/atl2/atl2_hw.h |
1354 | =================================================================== |
1355 | --- /dev/null |
1356 | +++ linux-2.6.26.noarch/drivers/net/atl2/atl2_hw.h |
1357 | @@ -0,0 +1,758 @@ |
1358 | +/* atl2_hw.h -- atl2 hardware definitions |
1359 | + * |
1360 | + * Copyright(c) 2007 Atheros Corporation. All rights reserved. |
1361 | + * Copyright(c) 2006 xiong huang <xiong.huang@atheros.com> |
1362 | + * Copyright(c) 2007 Chris Snook <csnook@redhat.com> |
1363 | + * |
1364 | + * Derived from Intel e1000 driver |
1365 | + * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. |
1366 | + * |
1367 | + * This program is free software; you can redistribute it and/or modify it |
1368 | + * under the terms of the GNU General Public License as published by the Free |
1369 | + * Software Foundation; either version 2 of the License, or (at your option) |
1370 | + * any later version. |
1371 | + * |
1372 | + * This program is distributed in the hope that it will be useful, but WITHOUT |
1373 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
1374 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
1375 | + * more details. |
1376 | + * |
1377 | + * You should have received a copy of the GNU General Public License along with |
1378 | + * this program; if not, write to the Free Software Foundation, Inc., 59 |
1379 | + * Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
1380 | + * |
1381 | + * Some of these defines are unused for various reasons. Some describe |
1382 | + * hardware features we don't yet use. Some are specific to the cousin atl1 |
1383 | + * hardware, which we may merge this driver with in the future. Please |
1384 | + * remember this is a surrogate for hardware specs, and don't unnecessarily |
1385 | + * abuse the content or formatting. -- CHS |
1386 | + */ |
1387 | + |
1388 | +#ifndef _ATL2_HW_H_ |
1389 | +#define _ATL2_HW_H_ |
1390 | + |
1391 | +#include "atl2_osdep.h" |
1392 | + |
1393 | +struct atl2_adapter; |
1394 | +struct atl2_hw; |
1395 | + |
1396 | +/* function prototype */ |
1397 | +s32 atl2_reset_hw(struct atl2_hw *hw); |
1398 | +s32 atl2_read_mac_addr(struct atl2_hw *hw); |
1399 | +s32 atl2_init_hw(struct atl2_hw *hw); |
1400 | +s32 atl2_get_speed_and_duplex(struct atl2_hw *hw, u16 *speed, u16 *duplex); |
1401 | +u32 atl2_auto_get_fc(struct atl2_adapter *adapter, u16 duplex); |
1402 | +u32 atl2_hash_mc_addr(struct atl2_hw *hw, u8 *mc_addr); |
1403 | +void atl2_hash_set(struct atl2_hw *hw, u32 hash_value); |
1404 | +s32 atl2_read_phy_reg(struct atl2_hw *hw, u16 reg_addr, u16 *phy_data); |
1405 | +s32 atl2_write_phy_reg(struct atl2_hw *hw, u32 reg_addr, u16 phy_data); |
1406 | +void atl2_read_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value); |
1407 | +void atl2_write_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value); |
1408 | +s32 atl2_validate_mdi_setting(struct atl2_hw *hw); |
1409 | +void atl2_set_mac_addr(struct atl2_hw *hw); |
1410 | +bool atl2_read_eeprom(struct atl2_hw *hw, u32 Offset, u32 *pValue); |
1411 | +bool atl2_write_eeprom(struct atl2_hw *hw, u32 offset, u32 value); |
1412 | +s32 atl2_phy_init(struct atl2_hw *hw); |
1413 | +int atl2_check_eeprom_exist(struct atl2_hw *hw); |
1414 | +void atl2_force_ps(struct atl2_hw *hw); |
1415 | + |
1416 | +/* register definition */ |
1417 | +#define REG_PM_CTRLSTAT 0x44 |
1418 | + |
1419 | +#define REG_PCIE_CAP_LIST 0x58 |
1420 | + |
1421 | +#define REG_VPD_CAP 0x6C |
1422 | +#define VPD_CAP_ID_MASK 0xff |
1423 | +#define VPD_CAP_ID_SHIFT 0 |
1424 | +#define VPD_CAP_NEXT_PTR_MASK 0xFF |
1425 | +#define VPD_CAP_NEXT_PTR_SHIFT 8 |
1426 | +#define VPD_CAP_VPD_ADDR_MASK 0x7FFF |
1427 | +#define VPD_CAP_VPD_ADDR_SHIFT 16 |
1428 | +#define VPD_CAP_VPD_FLAG 0x80000000 |
1429 | + |
1430 | +#define REG_VPD_DATA 0x70 |
1431 | + |
1432 | +#define REG_SPI_FLASH_CTRL 0x200 |
1433 | +#define SPI_FLASH_CTRL_STS_NON_RDY 0x1 |
1434 | +#define SPI_FLASH_CTRL_STS_WEN 0x2 |
1435 | +#define SPI_FLASH_CTRL_STS_WPEN 0x80 |
1436 | +#define SPI_FLASH_CTRL_DEV_STS_MASK 0xFF |
1437 | +#define SPI_FLASH_CTRL_DEV_STS_SHIFT 0 |
1438 | +#define SPI_FLASH_CTRL_INS_MASK 0x7 |
1439 | +#define SPI_FLASH_CTRL_INS_SHIFT 8 |
1440 | +#define SPI_FLASH_CTRL_START 0x800 |
1441 | +#define SPI_FLASH_CTRL_EN_VPD 0x2000 |
1442 | +#define SPI_FLASH_CTRL_LDSTART 0x8000 |
1443 | +#define SPI_FLASH_CTRL_CS_HI_MASK 0x3 |
1444 | +#define SPI_FLASH_CTRL_CS_HI_SHIFT 16 |
1445 | +#define SPI_FLASH_CTRL_CS_HOLD_MASK 0x3 |
1446 | +#define SPI_FLASH_CTRL_CS_HOLD_SHIFT 18 |
1447 | +#define SPI_FLASH_CTRL_CLK_LO_MASK 0x3 |
1448 | +#define SPI_FLASH_CTRL_CLK_LO_SHIFT 20 |
1449 | +#define SPI_FLASH_CTRL_CLK_HI_MASK 0x3 |
1450 | +#define SPI_FLASH_CTRL_CLK_HI_SHIFT 22 |
1451 | +#define SPI_FLASH_CTRL_CS_SETUP_MASK 0x3 |
1452 | +#define SPI_FLASH_CTRL_CS_SETUP_SHIFT 24 |
1453 | +#define SPI_FLASH_CTRL_EROM_PGSZ_MASK 0x3 |
1454 | +#define SPI_FLASH_CTRL_EROM_PGSZ_SHIFT 26 |
1455 | +#define SPI_FLASH_CTRL_WAIT_READY 0x10000000 |
1456 | + |
1457 | +#define REG_SPI_ADDR 0x204 |
1458 | + |
1459 | +#define REG_SPI_DATA 0x208 |
1460 | + |
1461 | +#define REG_SPI_FLASH_CONFIG 0x20C |
1462 | +#define SPI_FLASH_CONFIG_LD_ADDR_MASK 0xFFFFFF |
1463 | +#define SPI_FLASH_CONFIG_LD_ADDR_SHIFT 0 |
1464 | +#define SPI_FLASH_CONFIG_VPD_ADDR_MASK 0x3 |
1465 | +#define SPI_FLASH_CONFIG_VPD_ADDR_SHIFT 24 |
1466 | +#define SPI_FLASH_CONFIG_LD_EXIST 0x4000000 |
1467 | + |
1468 | +#define REG_SPI_FLASH_OP_PROGRAM 0x210 |
1469 | +#define REG_SPI_FLASH_OP_SC_ERASE 0x211 |
1470 | +#define REG_SPI_FLASH_OP_CHIP_ERASE 0x212 |
1471 | +#define REG_SPI_FLASH_OP_RDID 0x213 |
1472 | +#define REG_SPI_FLASH_OP_WREN 0x214 |
1473 | +#define REG_SPI_FLASH_OP_RDSR 0x215 |
1474 | +#define REG_SPI_FLASH_OP_WRSR 0x216 |
1475 | +#define REG_SPI_FLASH_OP_READ 0x217 |
1476 | + |
1477 | +#define REG_TWSI_CTRL 0x218 |
1478 | +#define TWSI_CTRL_LD_OFFSET_MASK 0xFF |
1479 | +#define TWSI_CTRL_LD_OFFSET_SHIFT 0 |
1480 | +#define TWSI_CTRL_LD_SLV_ADDR_MASK 0x7 |
1481 | +#define TWSI_CTRL_LD_SLV_ADDR_SHIFT 8 |
1482 | +#define TWSI_CTRL_SW_LDSTART 0x800 |
1483 | +#define TWSI_CTRL_HW_LDSTART 0x1000 |
1484 | +#define TWSI_CTRL_SMB_SLV_ADDR_MASK 0x0x7F |
1485 | +#define TWSI_CTRL_SMB_SLV_ADDR_SHIFT 15 |
1486 | +#define TWSI_CTRL_LD_EXIST 0x400000 |
1487 | +#define TWSI_CTRL_READ_FREQ_SEL_MASK 0x3 |
1488 | +#define TWSI_CTRL_READ_FREQ_SEL_SHIFT 23 |
1489 | +#define TWSI_CTRL_FREQ_SEL_100K 0 |
1490 | +#define TWSI_CTRL_FREQ_SEL_200K 1 |
1491 | +#define TWSI_CTRL_FREQ_SEL_300K 2 |
1492 | +#define TWSI_CTRL_FREQ_SEL_400K 3 |
1493 | +#define TWSI_CTRL_SMB_SLV_ADDR |
1494 | +#define TWSI_CTRL_WRITE_FREQ_SEL_MASK 0x3 |
1495 | +#define TWSI_CTRL_WRITE_FREQ_SEL_SHIFT 24 |
1496 | + |
1497 | +#define REG_PCIE_DEV_MISC_CTRL 0x21C |
1498 | +#define PCIE_DEV_MISC_CTRL_EXT_PIPE 0x2 |
1499 | +#define PCIE_DEV_MISC_CTRL_RETRY_BUFDIS 0x1 |
1500 | +#define PCIE_DEV_MISC_CTRL_SPIROM_EXIST 0x4 |
1501 | +#define PCIE_DEV_MISC_CTRL_SERDES_ENDIAN 0x8 |
1502 | +#define PCIE_DEV_MISC_CTRL_SERDES_SEL_DIN 0x10 |
1503 | + |
1504 | +#define REG_PCIE_PHYMISC 0x1000 |
1505 | +#define PCIE_PHYMISC_FORCE_RCV_DET 0x4 |
1506 | + |
1507 | +#define REG_PCIE_DLL_TX_CTRL1 0x1104 |
1508 | +#define PCIE_DLL_TX_CTRL1_SEL_NOR_CLK 0x0400 |
1509 | +#define PCIE_DLL_TX_CTRL1_DEF 0x0568 |
1510 | + |
1511 | +#define REG_LTSSM_TEST_MODE 0x12FC |
1512 | +#define LTSSM_TEST_MODE_DEF 0x6500 |
1513 | + |
1514 | +/* Master Control Register */ |
1515 | +#define REG_MASTER_CTRL 0x1400 |
1516 | +#define MASTER_CTRL_SOFT_RST 0x1 |
1517 | +#define MASTER_CTRL_MTIMER_EN 0x2 |
1518 | +#define MASTER_CTRL_ITIMER_EN 0x4 |
1519 | +#define MASTER_CTRL_MANUAL_INT 0x8 |
1520 | +#define MASTER_CTRL_REV_NUM_SHIFT 16 |
1521 | +#define MASTER_CTRL_REV_NUM_MASK 0xff |
1522 | +#define MASTER_CTRL_DEV_ID_SHIFT 24 |
1523 | +#define MASTER_CTRL_DEV_ID_MASK 0xff |
1524 | + |
1525 | +/* Timer Initial Value Register */ |
1526 | +#define REG_MANUAL_TIMER_INIT 0x1404 |
1527 | + |
1528 | +/* IRQ ModeratorTimer Initial Value Register */ |
1529 | +#define REG_IRQ_MODU_TIMER_INIT 0x1408 |
1530 | + |
1531 | +#define REG_PHY_ENABLE 0x140C |
1532 | +// IRQ Anti-Lost Timer Initial Value Register |
1533 | +//#define REG_IRQ_CLR_TIMER 0x140c // Maximum allowance for software to clear the interrupt. |
1534 | +// IRQ Anti-Lost Timer Initial Value Register |
1535 | +#define REG_CMBDISDMA_TIMER 0x140E |
1536 | + |
1537 | +/* Block IDLE Status Register */ |
1538 | +#define REG_IDLE_STATUS 0x1410 |
1539 | +#define IDLE_STATUS_RXMAC 1 /* 1: RXMAC state machine is in non-IDLE state. 0: RXMAC is idling */ |
1540 | +#define IDLE_STATUS_TXMAC 2 /* 1: TXMAC state machine is in non-IDLE state. 0: TXMAC is idling */ |
1541 | +#define IDLE_STATUS_DMAR 8 /* 1: DMAR state machine is in non-IDLE state. 0: DMAR is idling */ |
1542 | +#define IDLE_STATUS_DMAW 4 /* 1: DMAW state machine is in non-IDLE state. 0: DMAW is idling */ |
1543 | + |
1544 | +/* MDIO Control Register */ |
1545 | +#define REG_MDIO_CTRL 0x1414 |
1546 | +#define MDIO_DATA_MASK 0xffff /* On MDIO write, the 16-bit control data to write to PHY MII management register */ |
1547 | +#define MDIO_DATA_SHIFT 0 /* On MDIO read, the 16-bit status data that was read from the PHY MII management register. */ |
1548 | +#define MDIO_REG_ADDR_MASK 0x1f /* MDIO register address */ |
1549 | +#define MDIO_REG_ADDR_SHIFT 16 |
1550 | +#define MDIO_RW 0x200000 /* 1: read, 0: write */ |
1551 | +#define MDIO_SUP_PREAMBLE 0x400000 /* Suppress preamble */ |
1552 | +#define MDIO_START 0x800000 /* Write 1 to initiate the MDIO master. And this bit is self cleared after one cycle. */ |
1553 | +#define MDIO_CLK_SEL_SHIFT 24 |
1554 | +#define MDIO_CLK_25_4 0 |
1555 | +#define MDIO_CLK_25_6 2 |
1556 | +#define MDIO_CLK_25_8 3 |
1557 | +#define MDIO_CLK_25_10 4 |
1558 | +#define MDIO_CLK_25_14 5 |
1559 | +#define MDIO_CLK_25_20 6 |
1560 | +#define MDIO_CLK_25_28 7 |
1561 | +#define MDIO_BUSY 0x8000000 |
1562 | +#define MDIO_WAIT_TIMES 10 |
1563 | + |
1564 | +/* SerDes Lock Detect Control and Status Register */ |
1565 | +#define REG_SERDES_LOCK 0x1424 |
1566 | +#define SERDES_LOCK_DETECT 1 /* 1: SerDes lock detected. This signal comes from Analog SerDes. */ |
1567 | +#define SERDES_LOCK_DETECT_EN 2 /* 1: Enable SerDes Lock detect function. */ |
1568 | + |
1569 | +/* MAC Control Register */ |
1570 | +#define REG_MAC_CTRL 0x1480 |
1571 | +#define MAC_CTRL_TX_EN 1 /* 1: Transmit Enable */ |
1572 | +#define MAC_CTRL_RX_EN 2 /* 1: Receive Enable */ |
1573 | +#define MAC_CTRL_TX_FLOW 4 /* 1: Transmit Flow Control Enable */ |
1574 | +#define MAC_CTRL_RX_FLOW 8 /* 1: Receive Flow Control Enable */ |
1575 | +#define MAC_CTRL_LOOPBACK 0x10 /* 1: Loop back at G/MII Interface */ |
1576 | +#define MAC_CTRL_DUPLX 0x20 /* 1: Full-duplex mode 0: Half-duplex mode */ |
1577 | +#define MAC_CTRL_ADD_CRC 0x40 /* 1: Instruct MAC to attach CRC on all egress Ethernet frames */ |
1578 | +#define MAC_CTRL_PAD 0x80 /* 1: Instruct MAC to pad short frames to 60-bytes, and then attach CRC. This bit has higher priority over CRC_EN */ |
1579 | +#define MAC_CTRL_PRMLEN_SHIFT 10 /* Preamble length, it's 0x07 by standard */ |
1580 | +#define MAC_CTRL_PRMLEN_MASK 0xf |
1581 | +#define MAC_CTRL_RMV_VLAN 0x4000 /* 1: to remove VLAN Tag automatically from all receive packets */ |
1582 | +#define MAC_CTRL_PROMIS_EN 0x8000 /* 1: Promiscuous Mode Enable */ |
1583 | +#define MAC_CTRL_DBG_TX_BKPRESURE 0x100000 /* 1: transmit maximum backoff (half-duplex test bit) */ |
1584 | +#define MAC_CTRL_MC_ALL_EN 0x2000000 /* 1: upload all multicast frame without error to system */ |
1585 | +#define MAC_CTRL_BC_EN 0x4000000 /* 1: upload all broadcast frame without error to system */ |
1586 | +#define MAC_CTRL_MACLP_CLK_PHY 0x8000000 /* 1: MAC-LoopBack clock from phy, 0:from sys_25M */ |
1587 | +#define MAC_CTRL_HALF_LEFT_BUF_SHIFT 28 |
1588 | +#define MAC_CTRL_HALF_LEFT_BUF_MASK 0xF /* When half-duplex mode, should hold some bytes for mac retry . (8*4bytes unit) */ |
1589 | + |
1590 | +/* MAC IPG/IFG Control Register */ |
1591 | +#define REG_MAC_IPG_IFG 0x1484 |
1592 | +#define MAC_IPG_IFG_IPGT_SHIFT 0 /* Desired back to back inter-packet gap. The default is 96-bit time. */ |
1593 | +#define MAC_IPG_IFG_IPGT_MASK 0x7f |
1594 | +#define MAC_IPG_IFG_MIFG_SHIFT 8 /* Minimum number of IFG to enforce in between RX frames. */ |
1595 | +#define MAC_IPG_IFG_MIFG_MASK 0xff /* Frame gap below such IFP is dropped. */ |
1596 | +#define MAC_IPG_IFG_IPGR1_SHIFT 16 /* 64bit Carrier-Sense window */ |
1597 | +#define MAC_IPG_IFG_IPGR1_MASK 0x7f |
1598 | +#define MAC_IPG_IFG_IPGR2_SHIFT 24 /* 96-bit IPG window */ |
1599 | +#define MAC_IPG_IFG_IPGR2_MASK 0x7f |
1600 | + |
1601 | +/* MAC STATION ADDRESS */ |
1602 | +#define REG_MAC_STA_ADDR 0x1488 |
1603 | + |
1604 | +/* Hash table for multicast address */ |
1605 | +#define REG_RX_HASH_TABLE 0x1490 |
1606 | + |
1607 | +/* MAC Half-Duplex Control Register */ |
1608 | +#define REG_MAC_HALF_DUPLX_CTRL 0x1498 |
1609 | +#define MAC_HALF_DUPLX_CTRL_LCOL_SHIFT 0 /* Collision Window. */ |
1610 | +#define MAC_HALF_DUPLX_CTRL_LCOL_MASK 0x3ff |
1611 | +#define MAC_HALF_DUPLX_CTRL_RETRY_SHIFT 12 /* Retransmission maximum, afterwards the packet will be discarded. */ |
1612 | +#define MAC_HALF_DUPLX_CTRL_RETRY_MASK 0xf |
1613 | +#define MAC_HALF_DUPLX_CTRL_EXC_DEF_EN 0x10000 /* 1: Allow the transmission of a packet which has been excessively deferred */ |
1614 | +#define MAC_HALF_DUPLX_CTRL_NO_BACK_C 0x20000 /* 1: No back-off on collision, immediately start the retransmission. */ |
1615 | +#define MAC_HALF_DUPLX_CTRL_NO_BACK_P 0x40000 /* 1: No back-off on backpressure, immediately start the transmission after back pressure */ |
1616 | +#define MAC_HALF_DUPLX_CTRL_ABEBE 0x80000 /* 1: Alternative Binary Exponential Back-off Enabled */ |
1617 | +#define MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT 20 /* Maximum binary exponential number. */ |
1618 | +#define MAC_HALF_DUPLX_CTRL_ABEBT_MASK 0xf |
1619 | +#define MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT 24 /* IPG to start JAM for collision based flow control in half-duplex */ |
1620 | +#define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK 0xf /* mode. In unit of 8-bit time. */ |
1621 | + |
1622 | +/* Maximum Frame Length Control Register */ |
1623 | +#define REG_MTU 0x149c |
1624 | + |
1625 | +/* Wake-On-Lan control register */ |
1626 | +#define REG_WOL_CTRL 0x14a0 |
1627 | +#define WOL_PATTERN_EN 0x00000001 |
1628 | +#define WOL_PATTERN_PME_EN 0x00000002 |
1629 | +#define WOL_MAGIC_EN 0x00000004 |
1630 | +#define WOL_MAGIC_PME_EN 0x00000008 |
1631 | +#define WOL_LINK_CHG_EN 0x00000010 |
1632 | +#define WOL_LINK_CHG_PME_EN 0x00000020 |
1633 | +#define WOL_PATTERN_ST 0x00000100 |
1634 | +#define WOL_MAGIC_ST 0x00000200 |
1635 | +#define WOL_LINKCHG_ST 0x00000400 |
1636 | +#define WOL_PT0_EN 0x00010000 |
1637 | +#define WOL_PT1_EN 0x00020000 |
1638 | +#define WOL_PT2_EN 0x00040000 |
1639 | +#define WOL_PT3_EN 0x00080000 |
1640 | +#define WOL_PT4_EN 0x00100000 |
1641 | +#define WOL_PT0_MATCH 0x01000000 |
1642 | +#define WOL_PT1_MATCH 0x02000000 |
1643 | +#define WOL_PT2_MATCH 0x04000000 |
1644 | +#define WOL_PT3_MATCH 0x08000000 |
1645 | +#define WOL_PT4_MATCH 0x10000000 |
1646 | + |
1647 | +/* Internal SRAM Partition Register */ |
1648 | +#define REG_SRAM_TXRAM_END 0x1500 /* Internal tail address of TXRAM default: 2byte*1024 */ |
1649 | +#define REG_SRAM_RXRAM_END 0x1502 /* Internal tail address of RXRAM default: 2byte*1024 */ |
1650 | + |
1651 | +/* |
1652 | +#define REG_SRAM_TCPH_PATH_ADDR (REG_SRAM_RFD_ADDR+48) |
1653 | +#define SRAM_TCPH_ADDR_MASK 0x0fff |
1654 | +#define SRAM_TCPH_ADDR_SHIFT 0 |
1655 | +#define SRAM_PATH_ADDR_MASK 0x0fff |
1656 | +#define SRAM_PATH_ADDR_SHIFT 16 |
1657 | +*/ |
1658 | + |
1659 | +/* Descriptor Control register */ |
1660 | +#define REG_DESC_BASE_ADDR_HI 0x1540 |
1661 | +#define REG_TXD_BASE_ADDR_LO 0x1544 /* The base address of the Transmit Data Memory low 32-bit(dword align) */ |
1662 | +#define REG_TXD_MEM_SIZE 0x1548 /* Transmit Data Memory size(by double word , max 256KB) */ |
1663 | +#define REG_TXS_BASE_ADDR_LO 0x154C /* The base address of the Transmit Status Memory low 32-bit(dword word align) */ |
1664 | +#define REG_TXS_MEM_SIZE 0x1550 /* double word unit, max 4*2047 bytes. */ |
1665 | +#define REG_RXD_BASE_ADDR_LO 0x1554 /* The base address of the Transmit Status Memory low 32-bit(unit 8 bytes) */ |
1666 | +#define REG_RXD_BUF_NUM 0x1558 /* Receive Data & Status Memory buffer number (unit 1536bytes, max 1536*2047) */ |
1667 | + |
1668 | +/* DMAR Control Register */ |
1669 | +#define REG_DMAR 0x1580 |
1670 | +#define DMAR_EN 0x1 /* 1: Enable DMAR */ |
1671 | + |
1672 | +/* TX Cur-Through (early tx threshold) Control Register */ |
1673 | +#define REG_TX_CUT_THRESH 0x1590 /* TxMac begin transmit packet threshold(unit word) */ |
1674 | + |
1675 | +/* DMAW Control Register */ |
1676 | +#define REG_DMAW 0x15A0 |
1677 | +#define DMAW_EN 0x1 |
1678 | + |
1679 | +/* Flow control register */ |
1680 | +#define REG_PAUSE_ON_TH 0x15A8 /* RXD high watermark of overflow threshold configuration register */ |
1681 | +#define REG_PAUSE_OFF_TH 0x15AA /* RXD lower watermark of overflow threshold configuration register */ |
1682 | + |
1683 | +/* Mailbox Register */ |
1684 | +#define REG_MB_TXD_WR_IDX 0x15f0 /* double word align */ |
1685 | +#define REG_MB_RXD_RD_IDX 0x15F4 /* RXD Read index (unit: 1536byets) */ |
1686 | + |
1687 | +/* Interrupt Status Register */ |
1688 | +#define REG_ISR 0x1600 |
1689 | +#define ISR_TIMER 1 /* Interrupt when Timer is counted down to zero */ |
1690 | +#define ISR_MANUAL 2 /* Software manual interrupt, for debug. Set when SW_MAN_INT_EN is set in Table 51 Selene Master Control Register (Offset 0x1400). */ |
1691 | +#define ISR_RXF_OV 4 /* RXF overflow interrupt */ |
1692 | +#define ISR_TXF_UR 8 /* TXF underrun interrupt */ |
1693 | +#define ISR_TXS_OV 0x10 /* Internal transmit status buffer full interrupt */ |
1694 | +#define ISR_RXS_OV 0x20 /* Internal receive status buffer ful interrupt */ |
1695 | +#define ISR_LINK_CHG 0x40 /* Link Status Change Interrupt */ |
1696 | +#define ISR_HOST_TXD_UR 0x80 |
1697 | +#define ISR_HOST_RXD_OV 0x100 /* Host rx data memory full , one pulse */ |
1698 | +//#define ISR_HOST_TXS_OV 0x200 /* Host tx status memory full , one pulse */ |
1699 | +#define ISR_DMAR_TO_RST 0x200 /* DMAR op timeout interrupt. SW should do Reset */ |
1700 | +#define ISR_DMAW_TO_RST 0x400 |
1701 | +#define ISR_PHY 0x800 /* phy interrupt */ |
1702 | +#define ISR_TS_UPDATE 0x10000 /* interrupt after new tx pkt status written to host */ |
1703 | +#define ISR_RS_UPDATE 0x20000 /* interrupt ater new rx pkt status written to host. */ |
1704 | +#define ISR_TX_EARLY 0x40000 /* interrupt when txmac begin transmit one packet */ |
1705 | +#define ISR_UR_DETECTED 0x1000000 |
1706 | +#define ISR_FERR_DETECTED 0x2000000 |
1707 | +#define ISR_NFERR_DETECTED 0x4000000 |
1708 | +#define ISR_CERR_DETECTED 0x8000000 |
1709 | +#define ISR_PHY_LINKDOWN 0x10000000 |
1710 | +#define ISR_DIS_INT 0x80000000 |
1711 | + |
1712 | +#define ISR_TX_EVENT (ISR_TXF_UR|ISR_TXS_OV|ISR_HOST_TXD_UR|ISR_TS_UPDATE|ISR_TX_EARLY) |
1713 | +#define ISR_RX_EVENT (ISR_RXF_OV|ISR_RXS_OV|ISR_HOST_RXD_OV|ISR_RS_UPDATE) |
1714 | + |
1715 | +/* Interrupt Mask Register */ |
1716 | +#define REG_IMR 0x1604 |
1717 | + |
1718 | +#define IMR_NORMAL_MASK (\ |
1719 | + /*ISR_LINK_CHG |*/\ |
1720 | + ISR_MANUAL |\ |
1721 | + ISR_DMAR_TO_RST |\ |
1722 | + ISR_DMAW_TO_RST |\ |
1723 | + ISR_PHY |\ |
1724 | + ISR_PHY_LINKDOWN |\ |
1725 | + ISR_TS_UPDATE |\ |
1726 | + ISR_RS_UPDATE ) |
1727 | + |
1728 | +/* Receive MAC Statistics Registers */ |
1729 | +#define REG_STS_RX_PAUSE 0x1700 /* The number of Pause packet received */ |
1730 | +#define REG_STS_RXD_OV 0x1704 /* The number of frame dropped due to occurrence of RX FIFO overflow */ |
1731 | +#define REG_STS_RXS_OV 0x1708 /* The number of frame dropped due to occerrence of RX Status Buffer Overflow */ |
1732 | +#define REG_STS_RX_FILTER 0x170C /* The number of packet dropped due to address filtering */ |
1733 | + |
1734 | +/* MII definitions */ |
1735 | + |
1736 | +/* PHY Common Register */ |
1737 | +#define MII_AT001_CR 0x09 |
1738 | +#define MII_AT001_SR 0x0A |
1739 | +#define MII_AT001_ESR 0x0F |
1740 | +#define MII_AT001_PSCR 0x10 |
1741 | +#define MII_AT001_PSSR 0x11 |
1742 | +#define MII_SMARTSPEED 0x14 |
1743 | +#define MII_DBG_ADDR 0x1D |
1744 | +#define MII_DBG_DATA 0x1E |
1745 | + |
1746 | +/* PHY Control Register */ |
1747 | +#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */ |
1748 | +#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ |
1749 | +#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ |
1750 | +#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ |
1751 | +#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */ |
1752 | +#define MII_CR_POWER_DOWN 0x0800 /* Power down */ |
1753 | +#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ |
1754 | +#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */ |
1755 | +#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ |
1756 | +#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ |
1757 | +#define MII_CR_SPEED_MASK 0x2040 |
1758 | +#define MII_CR_SPEED_1000 0x0040 |
1759 | +#define MII_CR_SPEED_100 0x2000 |
1760 | +#define MII_CR_SPEED_10 0x0000 |
1761 | + |
1762 | +/* PHY Status Register */ |
1763 | +#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */ |
1764 | +#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ |
1765 | +#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ |
1766 | +#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ |
1767 | +#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ |
1768 | +#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ |
1769 | +#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ |
1770 | +#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */ |
1771 | +#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ |
1772 | +#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ |
1773 | +#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ |
1774 | +#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ |
1775 | +#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ |
1776 | +#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ |
1777 | +#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ |
1778 | + |
1779 | +/* Link partner ability register. */ |
1780 | +#define MII_LPA_SLCT 0x001f /* Same as advertise selector */ |
1781 | +#define MII_LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */ |
1782 | +#define MII_LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */ |
1783 | +#define MII_LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */ |
1784 | +#define MII_LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */ |
1785 | +#define MII_LPA_100BASE4 0x0200 /* 100BASE-T4 */ |
1786 | +#define MII_LPA_PAUSE 0x0400 /* PAUSE */ |
1787 | +#define MII_LPA_ASYPAUSE 0x0800 /* Asymmetrical PAUSE */ |
1788 | +#define MII_LPA_RFAULT 0x2000 /* Link partner faulted */ |
1789 | +#define MII_LPA_LPACK 0x4000 /* Link partner acked us */ |
1790 | +#define MII_LPA_NPAGE 0x8000 /* Next page bit */ |
1791 | + |
1792 | +/* Autoneg Advertisement Register */ |
1793 | +#define MII_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */ |
1794 | +#define MII_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ |
1795 | +#define MII_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ |
1796 | +#define MII_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ |
1797 | +#define MII_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ |
1798 | +#define MII_AR_100T4_CAPS 0x0200 /* 100T4 Capable */ |
1799 | +#define MII_AR_PAUSE 0x0400 /* Pause operation desired */ |
1800 | +#define MII_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ |
1801 | +#define MII_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */ |
1802 | +#define MII_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */ |
1803 | +#define MII_AR_SPEED_MASK 0x01E0 |
1804 | +#define MII_AR_DEFAULT_CAP_MASK 0x0DE0 |
1805 | + |
1806 | +/* 1000BASE-T Control Register */ |
1807 | +#define MII_AT001_CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ |
1808 | +#define MII_AT001_CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ |
1809 | +#define MII_AT001_CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port, 0=DTE device */ |
1810 | +#define MII_AT001_CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master, 0=Configure PHY as Slave */ |
1811 | +#define MII_AT001_CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value, 0=Automatic Master/Slave config */ |
1812 | +#define MII_AT001_CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */ |
1813 | +#define MII_AT001_CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */ |
1814 | +#define MII_AT001_CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */ |
1815 | +#define MII_AT001_CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */ |
1816 | +#define MII_AT001_CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */ |
1817 | +#define MII_AT001_CR_1000T_SPEED_MASK 0x0300 |
1818 | +#define MII_AT001_CR_1000T_DEFAULT_CAP_MASK 0x0300 |
1819 | + |
1820 | +/* 1000BASE-T Status Register */ |
1821 | +#define MII_AT001_SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */ |
1822 | +#define MII_AT001_SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */ |
1823 | +#define MII_AT001_SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ |
1824 | +#define MII_AT001_SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ |
1825 | +#define MII_AT001_SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */ |
1826 | +#define MII_AT001_SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */ |
1827 | +#define MII_AT001_SR_1000T_REMOTE_RX_STATUS_SHIFT 12 |
1828 | +#define MII_AT001_SR_1000T_LOCAL_RX_STATUS_SHIFT 13 |
1829 | + |
1830 | +/* Extended Status Register */ |
1831 | +#define MII_AT001_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */ |
1832 | +#define MII_AT001_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */ |
1833 | +#define MII_AT001_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */ |
1834 | +#define MII_AT001_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */ |
1835 | + |
1836 | +/* AT001 PHY Specific Control Register */ |
1837 | +#define MII_AT001_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */ |
1838 | +#define MII_AT001_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */ |
1839 | +#define MII_AT001_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled *// |
1840 | +#define MII_AT001_PSCR_MAC_POWERDOWN 0x0008 |
1841 | +#define MII_AT001_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low, 0=CLK125 toggling */ |
1842 | +#define MII_AT001_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5, Manual MDI configuration */ |
1843 | +#define MII_AT001_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ |
1844 | +#define MII_AT001_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */ |
1845 | +#define MII_AT001_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled all speeds. */ |
1846 | +#define MII_AT001_PSCR_10BT_EXT_DIST_ENABLE 0x0080 /* 1=Enable Extended 10BASE-T distance (Lower 10BASE-T RX Threshold), 0=Normal 10BASE-T RX Threshold */ |
1847 | +#define MII_AT001_PSCR_MII_5BIT_ENABLE 0x0100 /* 1=5-Bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */ |
1848 | +#define MII_AT001_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */ |
1849 | +#define MII_AT001_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */ |
1850 | +#define MII_AT001_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ |
1851 | +#define MII_AT001_PSCR_POLARITY_REVERSAL_SHIFT 1 |
1852 | +#define MII_AT001_PSCR_AUTO_X_MODE_SHIFT 5 |
1853 | +#define MII_AT001_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7 |
1854 | + |
1855 | +/* AT001 PHY Specific Status Register */ |
1856 | +#define MII_AT001_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */ |
1857 | +#define MII_AT001_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */ |
1858 | +#define MII_AT001_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ |
1859 | +#define MII_AT001_PSSR_10MBS 0x0000 /* 00=10Mbs */ |
1860 | +#define MII_AT001_PSSR_100MBS 0x4000 /* 01=100Mbs */ |
1861 | +#define MII_AT001_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ |
1862 | + |
1863 | +/* PCI Command Register Bit Definitions */ |
1864 | +#define PCI_REG_COMMAND 0x04 |
1865 | +#define CMD_IO_SPACE 0x0001 |
1866 | +#define CMD_MEMORY_SPACE 0x0002 |
1867 | +#define CMD_BUS_MASTER 0x0004 |
1868 | + |
1869 | +/* Wake Up Filter Control */ |
1870 | +#define ATL2_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ |
1871 | +#define ATL2_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ |
1872 | +#define ATL2_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ |
1873 | +#define ATL2_WUFC_MC 0x00000008 /* Multicast Wakeup Enable */ |
1874 | +#define ATL2_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ |
1875 | + |
1876 | +/* Error Codes */ |
1877 | +#define ATL2_SUCCESS 0 |
1878 | +#define ATL2_ERR_EEPROM 1 |
1879 | +#define ATL2_ERR_PHY 2 |
1880 | +#define ATL2_ERR_CONFIG 3 |
1881 | +#define ATL2_ERR_PARAM 4 |
1882 | +#define ATL2_ERR_MAC_TYPE 5 |
1883 | +#define ATL2_ERR_PHY_TYPE 6 |
1884 | +#define ATL2_ERR_PHY_SPEED 7 |
1885 | +#define ATL2_ERR_PHY_RES 8 |
1886 | + |
1887 | +#define SPEED_0 0xffff |
1888 | +#define SPEED_10 10 |
1889 | +#define SPEED_100 100 |
1890 | +#define HALF_DUPLEX 1 |
1891 | +#define FULL_DUPLEX 2 |
1892 | + |
1893 | +#define MEDIA_TYPE_AUTO_SENSOR 0 |
1894 | +#define MEDIA_TYPE_100M_FULL 1 |
1895 | +#define MEDIA_TYPE_100M_HALF 2 |
1896 | +#define MEDIA_TYPE_10M_FULL 3 |
1897 | +#define MEDIA_TYPE_10M_HALF 4 |
1898 | + |
1899 | +#define ADVERTISE_10_HALF 0x0001 |
1900 | +#define ADVERTISE_10_FULL 0x0002 |
1901 | +#define ADVERTISE_100_HALF 0x0004 |
1902 | +#define ADVERTISE_100_FULL 0x0008 |
1903 | +#define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */ |
1904 | +#define ADVERTISE_1000_FULL 0x0020 |
1905 | + |
1906 | +#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x000F /* Everything */ |
1907 | +#define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds*/ |
1908 | +#define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds*/ |
1909 | + |
1910 | +/* The size (in bytes) of a ethernet packet */ |
1911 | +#define ENET_HEADER_SIZE 14 |
1912 | +#define MAXIMUM_ETHERNET_FRAME_SIZE 1518 /* with FCS */ |
1913 | +#define MINIMUM_ETHERNET_FRAME_SIZE 64 /* with FCS */ |
1914 | +#define ETHERNET_FCS_SIZE 4 |
1915 | +#define MAX_JUMBO_FRAME_SIZE 0x2000 |
1916 | +#define VLAN_SIZE 4 |
1917 | + |
1918 | +#define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */ |
1919 | +#define PHY_FORCE_TIME 20 /* 2.0 Seconds */ |
1920 | + |
1921 | +/* For checksumming , the sum of all words in the EEPROM should equal 0xBABA */ |
1922 | +#define EEPROM_SUM 0xBABA |
1923 | +#define NODE_ADDRESS_SIZE 6 |
1924 | + |
1925 | +typedef struct _tx_pkt_header { |
1926 | + unsigned pkt_size : 11; |
1927 | + unsigned : 4; // reserved |
1928 | + unsigned ins_vlan : 1; // txmac should insert vlan |
1929 | + unsigned short vlan ; // vlan tag |
1930 | +} tx_pkt_header_t; |
1931 | +/* FIXME: replace above bitfields with MASK/SHIFT defines below */ |
1932 | +#define TX_PKT_HEADER_SIZE_MASK 0x7FF |
1933 | +#define TX_PKT_HEADER_SIZE_SHIFT 0 |
1934 | +#define TX_PKT_HEADER_INS_VLAN_MASK 0x1 |
1935 | +#define TX_PKT_HEADER_INS_VLAN_SHIFT 15 |
1936 | +#define TX_PKT_HEADER_VLAN_TAG_MASK 0xFFFF |
1937 | +#define TX_PKT_HEADER_VLAN_TAG_SHIFT 16 |
1938 | + |
1939 | +typedef struct _tx_pkt_status { |
1940 | + unsigned pkt_size : 11; |
1941 | + unsigned : 5; // reserved |
1942 | + unsigned ok : 1; // current packet is transmitted ok without error |
1943 | + unsigned bcast : 1; // current packet is broadcast |
1944 | + unsigned mcast : 1; // current packet is multicast |
1945 | + unsigned pause : 1; // transmiited a pause frame |
1946 | + unsigned ctrl : 1; |
1947 | + unsigned defer : 1; // current packet is xmitted with defer. |
1948 | + unsigned exc_defer : 1; |
1949 | + unsigned single_col : 1; |
1950 | + unsigned multi_col : 1; |
1951 | + unsigned late_col : 1; |
1952 | + unsigned abort_col : 1; |
1953 | + unsigned underun : 1; // current packet is abort due to txram underrun. |
1954 | + unsigned : 3; // reserved |
1955 | + unsigned update : 1; // always 1'b1 in tx_status_buf. |
1956 | +} tx_pkt_status_t; |
1957 | +/* FIXME: replace above bitfields with MASK/SHIFT defines below */ |
1958 | +#define TX_PKT_STATUS_SIZE_MASK 0x7FF |
1959 | +#define TX_PKT_STATUS_SIZE_SHIFT 0 |
1960 | +#define TX_PKT_STATUS_OK_MASK 0x1 |
1961 | +#define TX_PKT_STATUS_OK_SHIFT 16 |
1962 | +#define TX_PKT_STATUS_BCAST_MASK 0x1 |
1963 | +#define TX_PKT_STATUS_BCAST_SHIFT 17 |
1964 | +#define TX_PKT_STATUS_MCAST_MASK 0x1 |
1965 | +#define TX_PKT_STATUS_MCAST_SHIFT 18 |
1966 | +#define TX_PKT_STATUS_PAUSE_MASK 0x1 |
1967 | +#define TX_PKT_STATUS_PAUSE_SHIFT 19 |
1968 | +#define TX_PKT_STATUS_CTRL_MASK 0x1 |
1969 | +#define TX_PKT_STATUS_CTRL_SHIFT 20 |
1970 | +#define TX_PKT_STATUS_DEFER_MASK 0x1 |
1971 | +#define TX_PKT_STATUS_DEFER_SHIFT 21 |
1972 | +#define TX_PKT_STATUS_EXC_DEFER_MASK 0x1 |
1973 | +#define TX_PKT_STATUS_EXC_DEFER_SHIFT 22 |
1974 | +#define TX_PKT_STATUS_SINGLE_COL_MASK 0x1 |
1975 | +#define TX_PKT_STATUS_SINGLE_COL_SHIFT 23 |
1976 | +#define TX_PKT_STATUS_MULTI_COL_MASK 0x1 |
1977 | +#define TX_PKT_STATUS_MULTI_COL_SHIFT 24 |
1978 | +#define TX_PKT_STATUS_LATE_COL_MASK 0x1 |
1979 | +#define TX_PKT_STATUS_LATE_COL_SHIFT 25 |
1980 | +#define TX_PKT_STATUS_ABORT_COL_MASK 0x1 |
1981 | +#define TX_PKT_STATUS_ABORT_COL_SHIFT 26 |
1982 | +#define TX_PKT_STATUS_UNDERRUN_MASK 0x1 |
1983 | +#define TX_PKT_STATUS_UNDERRUN_SHIFT 27 |
1984 | +#define TX_PKT_STATUS_UPDATE_MASK 0x1 |
1985 | +#define TX_PKT_STATUS_UPDATE_SHIFT 31 |
1986 | + |
1987 | +typedef struct _rx_pkt_status { |
1988 | + unsigned pkt_size : 11; // packet size, max 2047bytes |
1989 | + unsigned : 5; // reserved |
1990 | + unsigned ok : 1; // current packet is received ok without error. |
1991 | + unsigned bcast : 1; // current packet is broadcast. |
1992 | + unsigned mcast : 1; // current packet is multicast. |
1993 | + unsigned pause : 1; |
1994 | + unsigned ctrl : 1; |
1995 | + unsigned crc : 1; // received a packet with crc error. |
1996 | + unsigned code : 1; // received a packet with code error. |
1997 | + unsigned runt : 1; // received a packet less than 64bytes with good crc |
1998 | + unsigned frag : 1; // ....................................with bad crc |
1999 | + unsigned trunc : 1; // current frame is cutted due to rxram full. |
2000 | + unsigned align : 1; // this packet is alignment error. |
2001 | + unsigned vlan : 1; // this packet has vlan |
2002 | + unsigned : 3; // reserved |
2003 | + unsigned update : 1; |
2004 | + unsigned short vtag ; // vlan tag |
2005 | + unsigned : 16; |
2006 | +} rx_pkt_status_t; |
2007 | +/* FIXME: replace above bitfields with MASK/SHIFT defines below */ |
2008 | +#define RX_PKT_STATUS_SIZE_MASK 0x7FF |
2009 | +#define RX_PKT_STATUS_SIZE_SHIFT 0 |
2010 | +#define RX_PKT_STATUS_OK_MASK 0x1 |
2011 | +#define RX_PKT_STATUS_OK_SHIFT 16 |
2012 | +#define RX_PKT_STATUS_BCAST_MASK 0x1 |
2013 | +#define RX_PKT_STATUS_BCAST_SHIFT 17 |
2014 | +#define RX_PKT_STATUS_MCAST_MASK 0x1 |
2015 | +#define RX_PKT_STATUS_MCAST_SHIFT 18 |
2016 | +#define RX_PKT_STATUS_PAUSE_MASK 0x1 |
2017 | +#define RX_PKT_STATUS_PAUSE_SHIFT 19 |
2018 | +#define RX_PKT_STATUS_CTRL_MASK 0x1 |
2019 | +#define RX_PKT_STATUS_CTRL_SHIFT 20 |
2020 | +#define RX_PKT_STATUS_CRC_MASK 0x1 |
2021 | +#define RX_PKT_STATUS_CRC_SHIFT 21 |
2022 | +#define RX_PKT_STATUS_CODE_MASK 0x1 |
2023 | +#define RX_PKT_STATUS_CODE_SHIFT 22 |
2024 | +#define RX_PKT_STATUS_RUNT_MASK 0x1 |
2025 | +#define RX_PKT_STATUS_RUNT_SHIFT 23 |
2026 | +#define RX_PKT_STATUS_FRAG_MASK 0x1 |
2027 | +#define RX_PKT_STATUS_FRAG_SHIFT 24 |
2028 | +#define RX_PKT_STATUS_TRUNK_MASK 0x1 |
2029 | +#define RX_PKT_STATUS_TRUNK_SHIFT 25 |
2030 | +#define RX_PKT_STATUS_ALIGN_MASK 0x1 |
2031 | +#define RX_PKT_STATUS_ALIGN_SHIFT 26 |
2032 | +#define RX_PKT_STATUS_VLAN_MASK 0x1 |
2033 | +#define RX_PKT_STATUS_VLAN_SHIFT 27 |
2034 | +#define RX_PKT_STATUS_UPDATE_MASK 0x1 |
2035 | +#define RX_PKT_STATUS_UPDATE_SHIFT 31 |
2036 | +#define RX_PKT_STATUS_VLAN_TAG_MASK 0xFFFF |
2037 | +#define RX_PKT_STATUS_VLAN_TAG_SHIFT 32 |
2038 | + |
2039 | +typedef struct _rx_desc { |
2040 | + rx_pkt_status_t status; |
2041 | + unsigned char packet[1536-sizeof(rx_pkt_status_t)]; |
2042 | +} rx_desc_t; |
2043 | + |
2044 | +typedef enum { |
2045 | + atl2_10_half = 0, |
2046 | + atl2_10_full = 1, |
2047 | + atl2_100_half = 2, |
2048 | + atl2_100_full = 3 |
2049 | +} atl2_speed_duplex_type; |
2050 | + |
2051 | +struct atl2_spi_flash_dev { |
2052 | + const char *manu_name; /* manufacturer id */ |
2053 | + /* op-code */ |
2054 | + u8 cmdWRSR; |
2055 | + u8 cmdREAD; |
2056 | + u8 cmdPROGRAM; |
2057 | + u8 cmdWREN; |
2058 | + u8 cmdWRDI; |
2059 | + u8 cmdRDSR; |
2060 | + u8 cmdRDID; |
2061 | + u8 cmdSECTOR_ERASE; |
2062 | + u8 cmdCHIP_ERASE; |
2063 | +}; |
2064 | + |
2065 | +/* Structure containing variables used by the shared code (atl2_hw.c) */ |
2066 | +struct atl2_hw { |
2067 | + u8 *hw_addr; |
2068 | + void *back; |
2069 | + |
2070 | + u8 preamble_len; |
2071 | + u8 max_retry; // Retransmission maximum , afterwards the packet will be discarded. |
2072 | + u8 jam_ipg; // IPG to start JAM for collision based flow control in half-duplex mode. In unit of 8-bit time. |
2073 | + u8 ipgt; // Desired back to back inter-packet gap. The default is 96-bit time. |
2074 | + u8 min_ifg; // Minimum number of IFG to enforce in between RX frames. Frame gap below such IFP is dropped. |
2075 | + u8 ipgr1; // 64bit Carrier-Sense window |
2076 | + u8 ipgr2; // 96-bit IPG window |
2077 | + u8 retry_buf; // When half-duplex mode, should hold some bytes for mac retry . (8*4bytes unit) |
2078 | + |
2079 | + u16 fc_rxd_hi; |
2080 | + u16 fc_rxd_lo; |
2081 | + u16 lcol; // Collision Window |
2082 | + u16 max_frame_size; |
2083 | + |
2084 | + u16 MediaType; |
2085 | + u16 autoneg_advertised; |
2086 | + u16 pci_cmd_word; |
2087 | + |
2088 | + u16 mii_autoneg_adv_reg; |
2089 | + |
2090 | + u32 mem_rang; |
2091 | + u32 txcw; |
2092 | + u32 mc_filter_type; |
2093 | + u32 num_mc_addrs; |
2094 | + u32 collision_delta; |
2095 | + u32 tx_packet_delta; |
2096 | + u16 phy_spd_default; |
2097 | + |
2098 | + u16 device_id; |
2099 | + u16 vendor_id; |
2100 | + u16 subsystem_id; |
2101 | + u16 subsystem_vendor_id; |
2102 | + u8 revision_id; |
2103 | + |
2104 | + // spi flash |
2105 | + u8 flash_vendor; |
2106 | + |
2107 | + u8 dma_fairness; |
2108 | + u8 mac_addr[NODE_ADDRESS_SIZE]; |
2109 | + u8 perm_mac_addr[NODE_ADDRESS_SIZE]; |
2110 | + |
2111 | + // bool phy_preamble_sup; |
2112 | + bool phy_configured; |
2113 | +}; |
2114 | + |
2115 | +#endif /* _ATL2_HW_H_ */ |
2116 | Index: linux-2.6.26.noarch/drivers/net/atl2/atl2_main.c |
2117 | =================================================================== |
2118 | --- /dev/null |
2119 | +++ linux-2.6.26.noarch/drivers/net/atl2/atl2_main.c |
2120 | @@ -0,0 +1,1851 @@ |
2121 | +/* atl2_main.c -- atl2 driver main functions |
2122 | + * |
2123 | + * Copyright(c) 2007 Atheros Corporation. All rights reserved. |
2124 | + * Copyright(c) 2006 xiong huang <xiong.huang@atheros.com> |
2125 | + * Copyright(c) 2007 Chris Snook <csnook@redhat.com> |
2126 | + * |
2127 | + * Derived from Intel e1000 driver |
2128 | + * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. |
2129 | + * |
2130 | + * This program is free software; you can redistribute it and/or modify it |
2131 | + * under the terms of the GNU General Public License as published by the Free |
2132 | + * Software Foundation; either version 2 of the License, or (at your option) |
2133 | + * any later version. |
2134 | + * |
2135 | + * This program is distributed in the hope that it will be useful, but WITHOUT |
2136 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
2137 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
2138 | + * more details. |
2139 | + * |
2140 | + * You should have received a copy of the GNU General Public License along with |
2141 | + * this program; if not, write to the Free Software Foundation, Inc., 59 |
2142 | + * Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
2143 | + */ |
2144 | + |
2145 | +#include <asm/atomic.h> |
2146 | +#include <linux/dma-mapping.h> |
2147 | +#include <linux/etherdevice.h> |
2148 | +#include <linux/hardirq.h> |
2149 | +#include <linux/if_vlan.h> |
2150 | +#include <linux/in.h> |
2151 | +#include <linux/interrupt.h> |
2152 | +#include <linux/ip.h> |
2153 | +#include <linux/irqflags.h> |
2154 | +#include <linux/irqreturn.h> |
2155 | +#include <linux/mii.h> |
2156 | +#include <linux/net.h> |
2157 | +#include <linux/netdevice.h> |
2158 | +#include <linux/pci.h> |
2159 | +#include <linux/pci_ids.h> |
2160 | +#include <linux/pm.h> |
2161 | +#include <linux/skbuff.h> |
2162 | +#include <linux/spinlock.h> |
2163 | +#include <linux/string.h> |
2164 | +#include <linux/tcp.h> |
2165 | +#include <linux/timer.h> |
2166 | +#include <linux/types.h> |
2167 | +#include <linux/workqueue.h> |
2168 | + |
2169 | +#include "atl2.h" |
2170 | + |
2171 | +#define ATL2_DRV_VERSION "2.0.4" |
2172 | + |
2173 | +char atl2_driver_name[] = "atl2"; |
2174 | +static const char atl2_driver_string[] = "Atheros(R) L2 Ethernet Driver"; |
2175 | +static char atl2_copyright[] = "Copyright (c) 2007 Atheros Corporation."; |
2176 | +char atl2_driver_version[] = ATL2_DRV_VERSION; |
2177 | + |
2178 | +MODULE_AUTHOR("Atheros Corporation <xiong.huang@atheros.com>, Chris Snook <csnook@redhat.com>"); |
2179 | +MODULE_DESCRIPTION("Atheros Fast Ethernet Network Driver"); |
2180 | +MODULE_LICENSE("GPL"); |
2181 | +MODULE_VERSION(ATL2_DRV_VERSION); |
2182 | + |
2183 | +/* FIXME: remove this after merging, goes in pci_ids.h */ |
2184 | +#ifndef PCI_DEVICE_ID_ATTANSIC_L2 |
2185 | +#define PCI_DEVICE_ID_ATTANSIC_L2 0x2048 |
2186 | +#endif |
2187 | + |
2188 | +/* |
2189 | + * atl2_pci_tbl - PCI Device ID Table |
2190 | + */ |
2191 | +static struct pci_device_id atl2_pci_tbl[] = { |
2192 | + {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L2)}, |
2193 | + /* required last entry */ |
2194 | + {0,} |
2195 | +}; |
2196 | +MODULE_DEVICE_TABLE(pci, atl2_pci_tbl); |
2197 | + |
2198 | +extern void atl2_set_ethtool_ops(struct net_device *netdev); |
2199 | +#ifdef ETHTOOL_OPS_COMPAT |
2200 | +extern int ethtool_ioctl(struct ifreq *ifr); |
2201 | +#endif |
2202 | + |
2203 | +#define COPYBREAK_DEFAULT 256 |
2204 | +static unsigned int copybreak __read_mostly = COPYBREAK_DEFAULT; |
2205 | +module_param(copybreak, uint, 0644); |
2206 | +MODULE_PARM_DESC(copybreak, "Maximum size of packet that is copied to a new buffer on receive"); |
2207 | + |
2208 | +extern void atl2_check_options(struct atl2_adapter *adapter); |
2209 | +#ifdef SIOCDEVPRIVATE |
2210 | +extern int atl2_priv_ioctl(struct net_device* netdev, struct ifreq* ifr); |
2211 | +#endif |
2212 | + |
2213 | +/** |
2214 | + * atl2_sw_init - Initialize general software structures (struct atl2_adapter) |
2215 | + * @adapter: board private structure to initialize |
2216 | + * |
2217 | + * atl2_sw_init initializes the Adapter private data structure. |
2218 | + * Fields are initialized based on PCI device information and |
2219 | + * OS network device settings (MTU size). |
2220 | + **/ |
2221 | +static int __devinit |
2222 | +atl2_sw_init(struct atl2_adapter *adapter) |
2223 | +{ |
2224 | + struct atl2_hw *hw = &adapter->hw; |
2225 | + struct pci_dev *pdev = adapter->pdev; |
2226 | + |
2227 | + /* PCI config space info */ |
2228 | + hw->vendor_id = pdev->vendor; |
2229 | + hw->device_id = pdev->device; |
2230 | + hw->subsystem_vendor_id = pdev->subsystem_vendor; |
2231 | + hw->subsystem_id = pdev->subsystem_device; |
2232 | + |
2233 | + pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id); |
2234 | + pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word); |
2235 | + |
2236 | + adapter->wol = 0; |
2237 | + adapter->ict = 50000; // 100ms |
2238 | + adapter->link_speed = SPEED_0; // hardware init |
2239 | + adapter->link_duplex = FULL_DUPLEX; |
2240 | + |
2241 | + hw->phy_configured = false; |
2242 | + hw->preamble_len = 7; |
2243 | + hw->ipgt = 0x60; |
2244 | + hw->min_ifg = 0x50; |
2245 | + hw->ipgr1 = 0x40; |
2246 | + hw->ipgr2 = 0x60; |
2247 | + hw->retry_buf = 2; |
2248 | + hw->max_retry = 0xf; |
2249 | + hw->lcol = 0x37; |
2250 | + hw->jam_ipg = 7; |
2251 | + hw->fc_rxd_hi = 0; |
2252 | + hw->fc_rxd_lo = 0; |
2253 | + hw->max_frame_size = adapter->netdev->mtu; |
2254 | + |
2255 | + spin_lock_init(&adapter->stats_lock); |
2256 | + spin_lock_init(&adapter->tx_lock); |
2257 | + |
2258 | + set_bit(__ATL2_DOWN, &adapter->flags); |
2259 | + |
2260 | + return 0; |
2261 | +} |
2262 | + |
2263 | +/** |
2264 | + * atl2_set_multi - Multicast and Promiscuous mode set |
2265 | + * @netdev: network interface device structure |
2266 | + * |
2267 | + * The set_multi entry point is called whenever the multicast address |
2268 | + * list or the network interface flags are updated. This routine is |
2269 | + * responsible for configuring the hardware for proper multicast, |
2270 | + * promiscuous mode, and all-multi behavior. |
2271 | + **/ |
2272 | +static void |
2273 | +atl2_set_multi(struct net_device *netdev) |
2274 | +{ |
2275 | + struct atl2_adapter *adapter = netdev_priv(netdev); |
2276 | + struct atl2_hw *hw = &adapter->hw; |
2277 | + struct dev_mc_list *mc_ptr; |
2278 | + u32 rctl; |
2279 | + u32 hash_value; |
2280 | + |
2281 | + /* Check for Promiscuous and All Multicast modes */ |
2282 | + rctl = ATL2_READ_REG(hw, REG_MAC_CTRL); |
2283 | + |
2284 | + if(netdev->flags & IFF_PROMISC) { |
2285 | + rctl |= MAC_CTRL_PROMIS_EN; |
2286 | + } else if(netdev->flags & IFF_ALLMULTI) { |
2287 | + rctl |= MAC_CTRL_MC_ALL_EN; |
2288 | + rctl &= ~MAC_CTRL_PROMIS_EN; |
2289 | + } else { |
2290 | + rctl &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN); |
2291 | + } |
2292 | + |
2293 | + ATL2_WRITE_REG(hw, REG_MAC_CTRL, rctl); |
2294 | + |
2295 | + /* clear the old settings from the multicast hash table */ |
2296 | + ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0); |
2297 | + ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0); |
2298 | + |
2299 | + /* comoute mc addresses' hash value ,and put it into hash table */ |
2300 | + for(mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) { |
2301 | + hash_value = atl2_hash_mc_addr(hw, mc_ptr->dmi_addr); |
2302 | + atl2_hash_set(hw, hash_value); |
2303 | + } |
2304 | +} |
2305 | + |
2306 | +static void |
2307 | +init_ring_ptrs(struct atl2_adapter *adapter) |
2308 | +{ |
2309 | + // Read / Write Ptr Initialize: |
2310 | + adapter->txd_write_ptr = 0; |
2311 | + atomic_set(&adapter->txd_read_ptr, 0); |
2312 | + |
2313 | + adapter->rxd_read_ptr = 0; |
2314 | + adapter->rxd_write_ptr = 0; |
2315 | + |
2316 | + atomic_set(&adapter->txs_write_ptr, 0); |
2317 | + adapter->txs_next_clear = 0; |
2318 | +} |
2319 | + |
2320 | +/** |
2321 | + * atl2_configure - Configure Transmit&Receive Unit after Reset |
2322 | + * @adapter: board private structure |
2323 | + * |
2324 | + * Configure the Tx /Rx unit of the MAC after a reset. |
2325 | + **/ |
2326 | +static int |
2327 | +atl2_configure(struct atl2_adapter *adapter) |
2328 | +{ |
2329 | + struct atl2_hw * hw = &adapter->hw; |
2330 | + u32 value; |
2331 | + |
2332 | + // clear interrupt status |
2333 | + ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0xffffffff); |
2334 | + |
2335 | + // set MAC Address |
2336 | + value = (((u32)hw->mac_addr[2]) << 24) | |
2337 | + (((u32)hw->mac_addr[3]) << 16) | |
2338 | + (((u32)hw->mac_addr[4]) << 8 ) | |
2339 | + (((u32)hw->mac_addr[5]) ) ; |
2340 | + ATL2_WRITE_REG(hw, REG_MAC_STA_ADDR, value); |
2341 | + value = (((u32)hw->mac_addr[0]) << 8 ) | |
2342 | + (((u32)hw->mac_addr[1]) ) ; |
2343 | + ATL2_WRITE_REG(hw, (REG_MAC_STA_ADDR+4), value); |
2344 | + |
2345 | + // HI base address |
2346 | + ATL2_WRITE_REG(hw, REG_DESC_BASE_ADDR_HI, |
2347 | + (u32)((adapter->ring_dma & 0xffffffff00000000ULL) >> 32)); |
2348 | + |
2349 | + // LO base address |
2350 | + ATL2_WRITE_REG(hw, REG_TXD_BASE_ADDR_LO, |
2351 | + (u32)(adapter->txd_dma & 0x00000000ffffffffULL)); |
2352 | + ATL2_WRITE_REG(hw, REG_TXS_BASE_ADDR_LO, |
2353 | + (u32)(adapter->txs_dma & 0x00000000ffffffffULL)); |
2354 | + ATL2_WRITE_REG(hw, REG_RXD_BASE_ADDR_LO, |
2355 | + (u32)(adapter->rxd_dma & 0x00000000ffffffffULL)); |
2356 | + |
2357 | + // element count |
2358 | + ATL2_WRITE_REGW(hw, REG_TXD_MEM_SIZE, (u16)(adapter->txd_ring_size/4)); |
2359 | + ATL2_WRITE_REGW(hw, REG_TXS_MEM_SIZE, (u16)adapter->txs_ring_size); |
2360 | + ATL2_WRITE_REGW(hw, REG_RXD_BUF_NUM, (u16)adapter->rxd_ring_size); |
2361 | + |
2362 | + /* config Internal SRAM */ |
2363 | +/* |
2364 | + ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_tx_end); |
2365 | + ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_rx_end); |
2366 | +*/ |
2367 | + |
2368 | + /* config IPG/IFG */ |
2369 | + value = (((u32)hw->ipgt & MAC_IPG_IFG_IPGT_MASK) << MAC_IPG_IFG_IPGT_SHIFT) | |
2370 | + (((u32)hw->min_ifg & MAC_IPG_IFG_MIFG_MASK) << MAC_IPG_IFG_MIFG_SHIFT) | |
2371 | + (((u32)hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK) << MAC_IPG_IFG_IPGR1_SHIFT)| |
2372 | + (((u32)hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK) << MAC_IPG_IFG_IPGR2_SHIFT); |
2373 | + ATL2_WRITE_REG(hw, REG_MAC_IPG_IFG, value); |
2374 | + |
2375 | + /* config Half-Duplex Control */ |
2376 | + value = ((u32)hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) | |
2377 | + (((u32)hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK) << |
2378 | + MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) | |
2379 | + MAC_HALF_DUPLX_CTRL_EXC_DEF_EN | |
2380 | + (0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) | |
2381 | + (((u32)hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK) << |
2382 | + MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT); |
2383 | + ATL2_WRITE_REG(hw, REG_MAC_HALF_DUPLX_CTRL, value); |
2384 | + |
2385 | + /* set Interrupt Moderator Timer */ |
2386 | + ATL2_WRITE_REGW(hw, REG_IRQ_MODU_TIMER_INIT, adapter->imt); |
2387 | + ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_ITIMER_EN); |
2388 | + |
2389 | + /* set Interrupt Clear Timer */ |
2390 | + ATL2_WRITE_REGW(hw, REG_CMBDISDMA_TIMER, adapter->ict); |
2391 | + |
2392 | + /* set MTU */ |
2393 | + ATL2_WRITE_REG(hw, REG_MTU, adapter->netdev->mtu + |
2394 | + ENET_HEADER_SIZE + VLAN_SIZE + ETHERNET_FCS_SIZE); |
2395 | + |
2396 | + /* 1590 */ |
2397 | + ATL2_WRITE_REG(hw, REG_TX_CUT_THRESH, 0x177); |
2398 | + |
2399 | + /* flow control */ |
2400 | + ATL2_WRITE_REGW(hw, REG_PAUSE_ON_TH, hw->fc_rxd_hi); |
2401 | + ATL2_WRITE_REGW(hw, REG_PAUSE_OFF_TH, hw->fc_rxd_lo); |
2402 | + |
2403 | + /* Init mailbox */ |
2404 | + ATL2_WRITE_REGW(hw, REG_MB_TXD_WR_IDX, (u16)adapter->txd_write_ptr); |
2405 | + ATL2_WRITE_REGW(hw, REG_MB_RXD_RD_IDX, (u16)adapter->rxd_read_ptr); |
2406 | + |
2407 | + /* enable DMA read/write */ |
2408 | + ATL2_WRITE_REGB(hw, REG_DMAR, DMAR_EN); |
2409 | + ATL2_WRITE_REGB(hw, REG_DMAW, DMAW_EN); |
2410 | + |
2411 | + value = ATL2_READ_REG(&adapter->hw, REG_ISR); |
2412 | + if ((value & ISR_PHY_LINKDOWN) != 0) { |
2413 | + value = 1; // config failed |
2414 | + } else { |
2415 | + value = 0; |
2416 | + } |
2417 | + |
2418 | + // clear all interrupt status |
2419 | + ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0x3fffffff); |
2420 | + ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0); |
2421 | + return value; |
2422 | +} |
2423 | + |
2424 | +/** |
2425 | + * atl2_setup_ring_resources - allocate Tx / RX descriptor resources |
2426 | + * @adapter: board private structure |
2427 | + * |
2428 | + * Return 0 on success, negative on failure |
2429 | + **/ |
2430 | +static s32 |
2431 | +atl2_setup_ring_resources(struct atl2_adapter *adapter) |
2432 | +{ |
2433 | + struct pci_dev *pdev = adapter->pdev; |
2434 | + int size; |
2435 | + u8 offset = 0; |
2436 | + |
2437 | + /* real ring DMA buffer */ |
2438 | + adapter->ring_size = size = |
2439 | + adapter->txd_ring_size * 1 + 7 + // dword align |
2440 | + adapter->txs_ring_size * 4 + 7 + // dword align |
2441 | + adapter->rxd_ring_size * 1536 + 127; // 128bytes align |
2442 | + |
2443 | + adapter->ring_vir_addr = pci_alloc_consistent(pdev, size, &adapter->ring_dma); |
2444 | + if (!adapter->ring_vir_addr) { |
2445 | + return -ENOMEM; |
2446 | + } |
2447 | +#if 0 |
2448 | + if (adapter->pci_using_64) { |
2449 | + // test whether HIDWORD dma buffer is not cross boundary |
2450 | + if ( ((adapter->ring_dma &0xffffffff00000000ULL)>>32) |
2451 | + != (((adapter->ring_dma+size)&0xffffffff00000000ULL)>>32) ) { |
2452 | + pci_free_consistent(pdev, adapter->ring_size, adapter->ring_vir_addr, adapter->ring_dma); |
2453 | + DEBUGOUT("memory allocated cross 32bit boundary !"); |
2454 | + return -ENOMEM; |
2455 | + } |
2456 | + } |
2457 | +#endif |
2458 | + memset(adapter->ring_vir_addr, 0, adapter->ring_size); |
2459 | + |
2460 | + // Init TXD Ring |
2461 | + adapter->txd_dma = adapter->ring_dma ; |
2462 | + offset = (adapter->txd_dma & 0x7) ? (8 - (adapter->txd_dma & 0x7)) : 0; |
2463 | + adapter->txd_dma += offset; |
2464 | + adapter->txd_ring = (tx_pkt_header_t*) (adapter->ring_vir_addr + offset); |
2465 | + |
2466 | + // Init TXS Ring |
2467 | + adapter->txs_dma = adapter->txd_dma + adapter->txd_ring_size; |
2468 | + offset = (adapter->txs_dma & 0x7) ? (8- (adapter->txs_dma & 0x7)) : 0; |
2469 | + adapter->txs_dma += offset; |
2470 | + adapter->txs_ring = (tx_pkt_status_t*) |
2471 | + (((u8*)adapter->txd_ring) + (adapter->txd_ring_size+offset)); |
2472 | + |
2473 | + // Init RXD Ring |
2474 | + adapter->rxd_dma = adapter->txs_dma + adapter->txs_ring_size*4; |
2475 | + offset = (adapter->rxd_dma & 127) ? (128 - (adapter->rxd_dma & 127)) : 0; |
2476 | + if (offset > 7) { |
2477 | + offset -= 8; |
2478 | + } else { |
2479 | + offset += (128 - 8); |
2480 | + } |
2481 | + adapter->rxd_dma += offset; |
2482 | + adapter->rxd_ring = (rx_desc_t*) (((u8*)adapter->txs_ring) + |
2483 | + (adapter->txs_ring_size*4 + offset)); |
2484 | + |
2485 | +// Read / Write Ptr Initialize: |
2486 | +// init_ring_ptrs(adapter); |
2487 | + |
2488 | + return ATL2_SUCCESS; |
2489 | +} |
2490 | + |
2491 | +/** |
2492 | + * atl2_irq_enable - Enable default interrupt generation settings |
2493 | + * @adapter: board private structure |
2494 | + **/ |
2495 | +static inline void |
2496 | +atl2_irq_enable(struct atl2_adapter *adapter) |
2497 | +{ |
2498 | + ATL2_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK); |
2499 | + ATL2_WRITE_FLUSH(&adapter->hw); |
2500 | +} |
2501 | + |
2502 | +/** |
2503 | + * atl2_irq_disable - Mask off interrupt generation on the NIC |
2504 | + * @adapter: board private structure |
2505 | + **/ |
2506 | +static inline void |
2507 | +atl2_irq_disable(struct atl2_adapter *adapter) |
2508 | +{ |
2509 | + ATL2_WRITE_REG(&adapter->hw, REG_IMR, 0); |
2510 | + ATL2_WRITE_FLUSH(&adapter->hw); |
2511 | + synchronize_irq(adapter->pdev->irq); |
2512 | +} |
2513 | + |
2514 | +#ifdef NETIF_F_HW_VLAN_TX |
2515 | +static void |
2516 | +atl2_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp) |
2517 | +{ |
2518 | + struct atl2_adapter *adapter = netdev_priv(netdev); |
2519 | + u32 ctrl; |
2520 | + |
2521 | + atl2_irq_disable(adapter); |
2522 | + adapter->vlgrp = grp; |
2523 | + |
2524 | + if(grp) { |
2525 | + /* enable VLAN tag insert/strip */ |
2526 | + ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL); |
2527 | + ctrl |= MAC_CTRL_RMV_VLAN; |
2528 | + ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl); |
2529 | + } else { |
2530 | + /* disable VLAN tag insert/strip */ |
2531 | + ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL); |
2532 | + ctrl &= ~MAC_CTRL_RMV_VLAN; |
2533 | + ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl); |
2534 | + } |
2535 | + |
2536 | + atl2_irq_enable(adapter); |
2537 | +} |
2538 | + |
2539 | +static void |
2540 | +atl2_restore_vlan(struct atl2_adapter *adapter) |
2541 | +{ |
2542 | + atl2_vlan_rx_register(adapter->netdev, adapter->vlgrp); |
2543 | +} |
2544 | +#endif |
2545 | + |
2546 | +static void |
2547 | +atl2_intr_rx(struct atl2_adapter* adapter) |
2548 | +{ |
2549 | + struct net_device *netdev = adapter->netdev; |
2550 | + rx_desc_t* rxd; |
2551 | + struct sk_buff* skb; |
2552 | + |
2553 | + do { |
2554 | + rxd = adapter->rxd_ring+adapter->rxd_write_ptr; |
2555 | + if (!rxd->status.update) |
2556 | + break; // end of tx |
2557 | + |
2558 | + // clear this flag at once |
2559 | + rxd->status.update = 0; |
2560 | + |
2561 | + if (rxd->status.ok && rxd->status.pkt_size >= 60) { |
2562 | + int rx_size = (int)(rxd->status.pkt_size - 4); |
2563 | + // alloc new buffer |
2564 | + skb = netdev_alloc_skb(netdev, rx_size + NET_IP_ALIGN); |
2565 | + if (NULL == skb) { |
2566 | + printk(KERN_WARNING"%s: Memory squeeze, deferring packet.\n", |
2567 | + netdev->name); |
2568 | + /* We should check that some rx space is free. |
2569 | + * If not, free one and mark stats->rx_dropped++. */ |
2570 | + adapter->net_stats.rx_dropped++; |
2571 | + break; |
2572 | + } |
2573 | +/* FIXME: ??? |
2574 | + if (rx_size > 1400) { |
2575 | + int s,c; |
2576 | + c = 0; |
2577 | + printk("rx_size= %d\n", rx_size); |
2578 | + for (s=0; s < 800; s++) { |
2579 | + if (0 == c) { |
2580 | + printk("%04x ", s); |
2581 | + } |
2582 | + printk("%02x ", rxd->packet[s]); |
2583 | + if (++c == 16) { |
2584 | + c = 0; |
2585 | + printk("\n"); |
2586 | + } |
2587 | + } |
2588 | + printk(KERN_WARNING"\n"); |
2589 | + } |
2590 | +*/ |
2591 | + skb_reserve(skb, NET_IP_ALIGN); |
2592 | + skb->dev = netdev; |
2593 | +/* gone in 2.6.23, just use memcpy? -- CHS |
2594 | + eth_copy_and_sum(skb, rxd->packet, rx_size, 0); */ |
2595 | + memcpy(skb->data, rxd->packet, rx_size); /* totally untested -- CHS */ |
2596 | + skb_put(skb, rx_size); |
2597 | + /* FIXME ??? |
2598 | + memcpy(skb_put(skb, rx_size), |
2599 | + rxd->packet, |
2600 | + rx_size); |
2601 | + */ |
2602 | + skb->protocol = eth_type_trans(skb, netdev); |
2603 | +#ifdef NETIF_F_HW_VLAN_TX |
2604 | + if(adapter->vlgrp && (rxd->status.vlan)) { |
2605 | + u16 vlan_tag = (rxd->status.vtag>>4) | |
2606 | + ((rxd->status.vtag&7) << 13) | |
2607 | + ((rxd->status.vtag&8) << 9); |
2608 | + vlan_hwaccel_rx(skb, adapter->vlgrp, vlan_tag); |
2609 | + } else |
2610 | +#endif |
2611 | + netif_rx(skb); |
2612 | + adapter->net_stats.rx_bytes += rx_size; |
2613 | + adapter->net_stats.rx_packets++; |
2614 | + netdev->last_rx = jiffies; |
2615 | + } else { |
2616 | + adapter->net_stats.rx_errors++; |
2617 | + |
2618 | + if (rxd->status.ok && rxd->status.pkt_size <= 60) { |
2619 | + adapter->net_stats.rx_length_errors++; |
2620 | + } |
2621 | + if (rxd->status.mcast) adapter->net_stats.multicast++; |
2622 | + if (rxd->status.crc) adapter->net_stats.rx_crc_errors++; |
2623 | + if (rxd->status.align) adapter->net_stats.rx_frame_errors++; |
2624 | + } |
2625 | + |
2626 | + // advance write ptr |
2627 | + if (++adapter->rxd_write_ptr == adapter->rxd_ring_size) |
2628 | + adapter->rxd_write_ptr = 0; |
2629 | + } while (1); |
2630 | + |
2631 | + // update mailbox ? |
2632 | + adapter->rxd_read_ptr = adapter->rxd_write_ptr; |
2633 | + ATL2_WRITE_REGW(&adapter->hw, REG_MB_RXD_RD_IDX, adapter->rxd_read_ptr); |
2634 | +} |
2635 | + |
2636 | +static void |
2637 | +atl2_intr_tx(struct atl2_adapter* adapter) |
2638 | +{ |
2639 | + u32 txd_read_ptr; |
2640 | + u32 txs_write_ptr; |
2641 | + tx_pkt_status_t* txs; |
2642 | + tx_pkt_header_t* txph; |
2643 | + int free_hole = 0; |
2644 | + |
2645 | + do { |
2646 | + txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr); |
2647 | + txs = adapter->txs_ring + txs_write_ptr; |
2648 | + if (!txs->update) |
2649 | + break; // tx stop here |
2650 | + |
2651 | + free_hole = 1; |
2652 | + txs->update = 0; |
2653 | + |
2654 | + if (++txs_write_ptr == adapter->txs_ring_size) |
2655 | + txs_write_ptr = 0; |
2656 | + atomic_set(&adapter->txs_write_ptr, (int)txs_write_ptr); |
2657 | + |
2658 | + txd_read_ptr = (u32) atomic_read(&adapter->txd_read_ptr); |
2659 | + txph = (tx_pkt_header_t*) (((u8*)adapter->txd_ring) + txd_read_ptr); |
2660 | + |
2661 | + if ( txph->pkt_size != txs->pkt_size) { |
2662 | + tx_pkt_status_t* old_txs = txs; |
2663 | + printk(KERN_WARNING |
2664 | + "%s: txs packet size do not coinsist with txd" |
2665 | + " txd_:0x%08x, txs_:0x%08x!\n", |
2666 | + adapter->netdev->name, |
2667 | + *(u32*)txph, *(u32*)txs); |
2668 | + printk(KERN_WARNING |
2669 | + "txd read ptr: 0x%x\n", |
2670 | + txd_read_ptr); |
2671 | + txs = adapter->txs_ring + txs_write_ptr; |
2672 | + printk(KERN_WARNING |
2673 | + "txs-behind:0x%08x\n", |
2674 | + *(u32*)txs); |
2675 | + if (txs_write_ptr < 2) { |
2676 | + txs = adapter->txs_ring + |
2677 | + (adapter->txs_ring_size + |
2678 | + txs_write_ptr - 2); |
2679 | + } else { |
2680 | + txs = adapter->txs_ring + (txs_write_ptr - 2); |
2681 | + } |
2682 | + printk(KERN_WARNING |
2683 | + "txs-before:0x%08x\n", |
2684 | + *(u32*)txs); |
2685 | + txs = old_txs; |
2686 | + } |
2687 | + |
2688 | + txd_read_ptr += (((u32)(txph->pkt_size)+7)& ~3);//4for TPH |
2689 | + if (txd_read_ptr >= adapter->txd_ring_size) |
2690 | + txd_read_ptr -= adapter->txd_ring_size; |
2691 | + |
2692 | + atomic_set(&adapter->txd_read_ptr, (int)txd_read_ptr); |
2693 | + |
2694 | + // tx statistics: |
2695 | + if (txs->ok) |
2696 | + adapter->net_stats.tx_packets++; |
2697 | + else |
2698 | + adapter->net_stats.tx_errors++; |
2699 | + |
2700 | + if (txs->defer) adapter->net_stats.collisions++; |
2701 | + if (txs->abort_col) adapter->net_stats.tx_aborted_errors++; |
2702 | + if (txs->late_col) adapter->net_stats.tx_window_errors++; |
2703 | + if (txs->underun) adapter->net_stats.tx_fifo_errors++; |
2704 | + } while (1); |
2705 | + |
2706 | + if (free_hole) { |
2707 | + if(netif_queue_stopped(adapter->netdev) && |
2708 | + netif_carrier_ok(adapter->netdev)) |
2709 | + netif_wake_queue(adapter->netdev); |
2710 | + } |
2711 | +} |
2712 | + |
2713 | +static void |
2714 | +atl2_check_for_link(struct atl2_adapter* adapter) |
2715 | +{ |
2716 | + struct net_device *netdev = adapter->netdev; |
2717 | + u16 phy_data = 0; |
2718 | + |
2719 | + spin_lock(&adapter->stats_lock); |
2720 | + atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data); |
2721 | + atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data); |
2722 | + spin_unlock(&adapter->stats_lock); |
2723 | + |
2724 | + // notify upper layer link down ASAP |
2725 | + if (!(phy_data & BMSR_LSTATUS)) { // Link Down |
2726 | + if (netif_carrier_ok(netdev)) { // old link state: Up |
2727 | + printk(KERN_INFO "%s: %s NIC Link is Down\n", |
2728 | + atl2_driver_name, netdev->name); |
2729 | + adapter->link_speed = SPEED_0; |
2730 | + netif_carrier_off(netdev); |
2731 | + netif_stop_queue(netdev); |
2732 | + } |
2733 | + } |
2734 | + schedule_work(&adapter->link_chg_task); |
2735 | +} |
2736 | + |
2737 | +static inline void |
2738 | +atl2_clear_phy_int(struct atl2_adapter *adapter) |
2739 | +{ |
2740 | + u16 phy_data; |
2741 | + spin_lock(&adapter->stats_lock); |
2742 | + atl2_read_phy_reg(&adapter->hw, 19, &phy_data); |
2743 | + spin_unlock(&adapter->stats_lock); |
2744 | +} |
2745 | + |
2746 | +/** |
2747 | + * atl2_intr - Interrupt Handler |
2748 | + * @irq: interrupt number |
2749 | + * @data: pointer to a network interface device structure |
2750 | + * @pt_regs: CPU registers structure |
2751 | + **/ |
2752 | +static irqreturn_t |
2753 | +atl2_intr(int irq, void *data) |
2754 | +{ |
2755 | + struct atl2_adapter *adapter = netdev_priv(data); |
2756 | + struct atl2_hw *hw = &adapter->hw; |
2757 | + u32 status; |
2758 | + |
2759 | + status = ATL2_READ_REG(hw, REG_ISR); |
2760 | + if (0 == status) |
2761 | + return IRQ_NONE; |
2762 | + |
2763 | + // link event |
2764 | + if (status & ISR_PHY) { |
2765 | + atl2_clear_phy_int(adapter); |
2766 | + } |
2767 | + |
2768 | + // clear ISR status, and Enable CMB DMA/Disable Interrupt |
2769 | + ATL2_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT); |
2770 | + |
2771 | + // FIXME: if PCIe link is down, how did we read the register? -- CHS |
2772 | + // check if PCIE PHY Link down |
2773 | + if (status & ISR_PHY_LINKDOWN) { |
2774 | + if(netif_running(adapter->netdev)) { // reset MAC |
2775 | + ATL2_WRITE_REG(hw, REG_ISR, 0); |
2776 | + ATL2_WRITE_REG(hw, REG_IMR, 0); |
2777 | + ATL2_WRITE_FLUSH(hw); |
2778 | + schedule_work(&adapter->reset_task); |
2779 | + return IRQ_HANDLED; |
2780 | + } |
2781 | + } |
2782 | + |
2783 | + // check if DMA read/write error ? |
2784 | + if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) |
2785 | + { |
2786 | + //ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, MASTER_CTRL_SOFT_RST); |
2787 | + ATL2_WRITE_REG(hw, REG_ISR, 0); |
2788 | + ATL2_WRITE_REG(hw, REG_IMR, 0); |
2789 | + ATL2_WRITE_FLUSH(hw); |
2790 | + schedule_work(&adapter->reset_task); |
2791 | + return IRQ_HANDLED; |
2792 | + } |
2793 | + |
2794 | + // link event |
2795 | + if (status & (ISR_PHY | ISR_MANUAL)) |
2796 | + { |
2797 | + adapter->net_stats.tx_carrier_errors++; |
2798 | + atl2_check_for_link(adapter); |
2799 | + } |
2800 | + |
2801 | + // transmit event |
2802 | + if (status & ISR_TX_EVENT) { |
2803 | + atl2_intr_tx(adapter); |
2804 | + } |
2805 | + |
2806 | + // rx exception |
2807 | + if (status & ISR_RX_EVENT) { |
2808 | + atl2_intr_rx(adapter); |
2809 | + } |
2810 | + |
2811 | + // re-enable Interrupt |
2812 | + ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0); |
2813 | + return IRQ_HANDLED; |
2814 | +} |
2815 | + |
2816 | +static int |
2817 | +atl2_request_irq(struct atl2_adapter *adapter) |
2818 | +{ |
2819 | + struct net_device *netdev = adapter->netdev; |
2820 | + int flags, err = 0; |
2821 | + |
2822 | + flags = IRQF_SHARED; |
2823 | +#ifdef CONFIG_PCI_MSI |
2824 | + adapter->have_msi = true; |
2825 | + if ((err = pci_enable_msi(adapter->pdev))) |
2826 | + adapter->have_msi = false; |
2827 | + |
2828 | + if (adapter->have_msi) |
2829 | + flags &= ~IRQF_SHARED; |
2830 | +#endif |
2831 | + |
2832 | + return request_irq(adapter->pdev->irq, &atl2_intr, flags, netdev->name, netdev); |
2833 | +} |
2834 | + |
2835 | +/** |
2836 | + * atl2_free_ring_resources - Free Tx / RX descriptor Resources |
2837 | + * @adapter: board private structure |
2838 | + * |
2839 | + * Free all transmit software resources |
2840 | + **/ |
2841 | +static void |
2842 | +atl2_free_ring_resources(struct atl2_adapter *adapter) |
2843 | +{ |
2844 | + struct pci_dev *pdev = adapter->pdev; |
2845 | + pci_free_consistent(pdev, adapter->ring_size, adapter->ring_vir_addr, adapter->ring_dma); |
2846 | +} |
2847 | + |
2848 | +/** |
2849 | + * atl2_open - Called when a network interface is made active |
2850 | + * @netdev: network interface device structure |
2851 | + * |
2852 | + * Returns 0 on success, negative value on failure |
2853 | + * |
2854 | + * The open entry point is called when a network interface is made |
2855 | + * active by the system (IFF_UP). At this point all resources needed |
2856 | + * for transmit and receive operations are allocated, the interrupt |
2857 | + * handler is registered with the OS, the watchdog timer is started, |
2858 | + * and the stack is notified that the interface is ready. |
2859 | + **/ |
2860 | +static int |
2861 | +atl2_open(struct net_device *netdev) |
2862 | +{ |
2863 | + struct atl2_adapter *adapter = netdev_priv(netdev); |
2864 | + int err; |
2865 | + u32 val; |
2866 | + |
2867 | + /* disallow open during test */ |
2868 | + if (test_bit(__ATL2_TESTING, &adapter->flags)) |
2869 | + return -EBUSY; |
2870 | + |
2871 | + /* allocate transmit descriptors */ |
2872 | + if((err = atl2_setup_ring_resources(adapter))) |
2873 | + return err; |
2874 | + |
2875 | + if((err = atl2_init_hw(&adapter->hw))) { |
2876 | + err = -EIO; |
2877 | + goto err_init_hw; |
2878 | + } |
2879 | + |
2880 | + /* hardware has been reset, we need to reload some things */ |
2881 | + atl2_set_multi(netdev); |
2882 | + init_ring_ptrs(adapter); |
2883 | + |
2884 | +#ifdef NETIF_F_HW_VLAN_TX |
2885 | + atl2_restore_vlan(adapter); |
2886 | +#endif |
2887 | + |
2888 | + if (atl2_configure(adapter)) { |
2889 | + err = -EIO; |
2890 | + goto err_config; |
2891 | + } |
2892 | + |
2893 | + if ((err = atl2_request_irq(adapter))) |
2894 | + goto err_req_irq; |
2895 | + |
2896 | + clear_bit(__ATL2_DOWN, &adapter->flags); |
2897 | + |
2898 | + mod_timer(&adapter->watchdog_timer, jiffies + 4*HZ); |
2899 | + |
2900 | + val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL); |
2901 | + ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, val | MASTER_CTRL_MANUAL_INT); |
2902 | + |
2903 | + atl2_irq_enable(adapter); |
2904 | + |
2905 | + return 0; |
2906 | + |
2907 | +err_init_hw: |
2908 | +err_req_irq: |
2909 | +err_config: |
2910 | + atl2_free_ring_resources(adapter); |
2911 | + atl2_reset_hw(&adapter->hw); |
2912 | + |
2913 | + return err; |
2914 | +} |
2915 | + |
2916 | +void |
2917 | +atl2_down(struct atl2_adapter *adapter) |
2918 | +{ |
2919 | + struct net_device *netdev = adapter->netdev; |
2920 | + |
2921 | + /* signal that we're down so the interrupt handler does not |
2922 | + * reschedule our watchdog timer */ |
2923 | + set_bit(__ATL2_DOWN, &adapter->flags); |
2924 | + |
2925 | +#ifdef NETIF_F_LLTX |
2926 | + netif_stop_queue(netdev); |
2927 | +#else |
2928 | + netif_tx_disable(netdev); |
2929 | +#endif |
2930 | + |
2931 | + /* reset MAC to disable all RX/TX */ |
2932 | + atl2_reset_hw(&adapter->hw); |
2933 | + msleep(1); |
2934 | + |
2935 | + atl2_irq_disable(adapter); |
2936 | + |
2937 | + del_timer_sync(&adapter->watchdog_timer); |
2938 | + del_timer_sync(&adapter->phy_config_timer); |
2939 | + clear_bit(0, &adapter->cfg_phy); |
2940 | + |
2941 | + netif_carrier_off(netdev); |
2942 | + adapter->link_speed = SPEED_0; |
2943 | + adapter->link_duplex = -1; |
2944 | + |
2945 | +// atl2_reset(adapter); |
2946 | +} |
2947 | + |
2948 | +static void |
2949 | +atl2_free_irq(struct atl2_adapter *adapter) |
2950 | +{ |
2951 | + struct net_device *netdev = adapter->netdev; |
2952 | + |
2953 | + free_irq(adapter->pdev->irq, netdev); |
2954 | + |
2955 | +#ifdef CONFIG_PCI_MSI |
2956 | + if (adapter->have_msi) |
2957 | + pci_disable_msi(adapter->pdev); |
2958 | +#endif |
2959 | +} |
2960 | + |
2961 | +/** |
2962 | + * atl2_close - Disables a network interface |
2963 | + * @netdev: network interface device structure |
2964 | + * |
2965 | + * Returns 0, this is not allowed to fail |
2966 | + * |
2967 | + * The close entry point is called when an interface is de-activated |
2968 | + * by the OS. The hardware is still under the drivers control, but |
2969 | + * needs to be disabled. A global MAC reset is issued to stop the |
2970 | + * hardware, and all transmit and receive resources are freed. |
2971 | + **/ |
2972 | +static int |
2973 | +atl2_close(struct net_device *netdev) |
2974 | +{ |
2975 | + struct atl2_adapter *adapter = netdev_priv(netdev); |
2976 | + |
2977 | + WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags)); |
2978 | + |
2979 | + atl2_down(adapter); |
2980 | + atl2_free_irq(adapter); |
2981 | + atl2_free_ring_resources(adapter); |
2982 | + |
2983 | + return 0; |
2984 | +} |
2985 | + |
2986 | +static inline int |
2987 | +TxsFreeUnit(struct atl2_adapter *adapter) |
2988 | +{ |
2989 | + u32 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr); |
2990 | + |
2991 | + return (adapter->txs_next_clear >= txs_write_ptr) ? |
2992 | + (int) (adapter->txs_ring_size - adapter->txs_next_clear + |
2993 | + txs_write_ptr - 1) : |
2994 | + (int) (txs_write_ptr - adapter->txs_next_clear - 1); |
2995 | +} |
2996 | + |
2997 | +static inline int |
2998 | +TxdFreeBytes(struct atl2_adapter *adapter) |
2999 | +{ |
3000 | + u32 txd_read_ptr = (u32)atomic_read(&adapter->txd_read_ptr); |
3001 | + |
3002 | + return (adapter->txd_write_ptr >= txd_read_ptr) ? |
3003 | + (int) (adapter->txd_ring_size - adapter->txd_write_ptr + |
3004 | + txd_read_ptr - 1): |
3005 | + (int) (txd_read_ptr - adapter->txd_write_ptr - 1); |
3006 | +} |
3007 | + |
3008 | +static int |
3009 | +atl2_xmit_frame(struct sk_buff *skb, struct net_device *netdev) |
3010 | +{ |
3011 | + struct atl2_adapter *adapter = netdev_priv(netdev); |
3012 | + unsigned long flags; |
3013 | + tx_pkt_header_t* txph; |
3014 | + u32 offset, copy_len; |
3015 | + int txs_unused; |
3016 | + int txbuf_unused; |
3017 | + |
3018 | + if (test_bit(__ATL2_DOWN, &adapter->flags)) { |
3019 | + dev_kfree_skb_any(skb); |
3020 | + return NETDEV_TX_OK; |
3021 | + } |
3022 | + |
3023 | + if (unlikely(skb->len <= 0)) { |
3024 | + dev_kfree_skb_any(skb); |
3025 | + return NETDEV_TX_OK; |
3026 | + } |
3027 | + |
3028 | +#ifdef NETIF_F_LLTX |
3029 | + local_irq_save(flags); |
3030 | + if (!spin_trylock(&adapter->tx_lock)) { |
3031 | + /* Collision - tell upper layer to requeue */ |
3032 | + local_irq_restore(flags); |
3033 | + return NETDEV_TX_LOCKED; |
3034 | + } |
3035 | +#else |
3036 | + spin_lock_irqsave(&adapter->tx_lock, flags); |
3037 | +#endif |
3038 | + txs_unused = TxsFreeUnit(adapter); |
3039 | + txbuf_unused = TxdFreeBytes(adapter); |
3040 | + |
3041 | + if (txs_unused < 1 || skb->len > txbuf_unused) { |
3042 | + // no enough resource |
3043 | + netif_stop_queue(netdev); |
3044 | + spin_unlock_irqrestore(&adapter->tx_lock, flags); |
3045 | + return NETDEV_TX_BUSY; |
3046 | + } |
3047 | + |
3048 | + offset = adapter->txd_write_ptr; |
3049 | + |
3050 | + txph = (tx_pkt_header_t*) (((u8*)adapter->txd_ring)+offset); |
3051 | + |
3052 | + *(u32*)txph = 0; |
3053 | + txph->pkt_size = skb->len; |
3054 | + |
3055 | + offset += 4; |
3056 | + if (offset >= adapter->txd_ring_size) |
3057 | + offset -= adapter->txd_ring_size; |
3058 | + copy_len = adapter->txd_ring_size - offset; |
3059 | + if (copy_len >= skb->len) { |
3060 | + memcpy(((u8*)adapter->txd_ring)+offset, skb->data, skb->len); |
3061 | + offset += ((u32)(skb->len+3)&~3); |
3062 | + } else { |
3063 | + memcpy(((u8*)adapter->txd_ring)+offset, skb->data, copy_len); |
3064 | + memcpy((u8*)adapter->txd_ring, skb->data+copy_len, skb->len-copy_len); |
3065 | + offset = ((u32)(skb->len-copy_len+3)&~3); |
3066 | + } |
3067 | +#ifdef NETIF_F_HW_VLAN_TX |
3068 | + if (adapter->vlgrp && vlan_tx_tag_present(skb)) { |
3069 | + u16 vlan_tag = vlan_tx_tag_get(skb); |
3070 | + vlan_tag = (vlan_tag << 4) | |
3071 | + (vlan_tag >> 13) | |
3072 | + ((vlan_tag >>9) & 0x8); |
3073 | + txph->ins_vlan = 1; |
3074 | + txph->vlan = vlan_tag; |
3075 | + } |
3076 | +#endif |
3077 | + if (offset >= adapter->txd_ring_size) |
3078 | + offset -= adapter->txd_ring_size; |
3079 | + adapter->txd_write_ptr = offset; |
3080 | + |
3081 | + // clear txs before send |
3082 | + adapter->txs_ring[adapter->txs_next_clear].update = 0; |
3083 | + if (++adapter->txs_next_clear == adapter->txs_ring_size) |
3084 | + adapter->txs_next_clear = 0; |
3085 | + |
3086 | + ATL2_WRITE_REGW(&adapter->hw, REG_MB_TXD_WR_IDX, (adapter->txd_write_ptr >> 2)); |
3087 | + |
3088 | + spin_unlock_irqrestore(&adapter->tx_lock, flags); |
3089 | + |
3090 | + netdev->trans_start = jiffies; |
3091 | + dev_kfree_skb_any(skb); |
3092 | + return NETDEV_TX_OK; |
3093 | +} |
3094 | + |
3095 | +/** |
3096 | + * atl2_get_stats - Get System Network Statistics |
3097 | + * @netdev: network interface device structure |
3098 | + * |
3099 | + * Returns the address of the device statistics structure. |
3100 | + * The statistics are actually updated from the timer callback. |
3101 | + **/ |
3102 | +static struct net_device_stats * |
3103 | +atl2_get_stats(struct net_device *netdev) |
3104 | +{ |
3105 | + struct atl2_adapter *adapter = netdev_priv(netdev); |
3106 | + |
3107 | + return &adapter->net_stats; |
3108 | +} |
3109 | + |
3110 | +/** |
3111 | + * atl2_change_mtu - Change the Maximum Transfer Unit |
3112 | + * @netdev: network interface device structure |
3113 | + * @new_mtu: new value for maximum frame size |
3114 | + * |
3115 | + * Returns 0 on success, negative on failure |
3116 | + **/ |
3117 | +static int |
3118 | +atl2_change_mtu(struct net_device *netdev, int new_mtu) |
3119 | +{ |
3120 | + struct atl2_adapter *adapter = netdev_priv(netdev); |
3121 | + struct atl2_hw *hw = &adapter->hw; |
3122 | + |
3123 | + if ((new_mtu < 40) || (new_mtu > (ETH_DATA_LEN + VLAN_SIZE))) |
3124 | + return -EINVAL; |
3125 | + |
3126 | + /* set MTU */ |
3127 | + if (hw->max_frame_size != new_mtu) { |
3128 | +// while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags)) |
3129 | +// msleep(1); |
3130 | + netdev->mtu = new_mtu; |
3131 | + |
3132 | + ATL2_WRITE_REG(hw, REG_MTU, |
3133 | + new_mtu + ENET_HEADER_SIZE + VLAN_SIZE + ETHERNET_FCS_SIZE); |
3134 | +// clear_bit(__ATL2_RESETTING, &adapter->flags); |
3135 | + } |
3136 | + |
3137 | + return 0; |
3138 | +} |
3139 | + |
3140 | +/** |
3141 | + * atl2_set_mac - Change the Ethernet Address of the NIC |
3142 | + * @netdev: network interface device structure |
3143 | + * @p: pointer to an address structure |
3144 | + * |
3145 | + * Returns 0 on success, negative on failure |
3146 | + **/ |
3147 | +static int |
3148 | +atl2_set_mac(struct net_device *netdev, void *p) |
3149 | +{ |
3150 | + struct atl2_adapter *adapter = netdev_priv(netdev); |
3151 | + struct sockaddr *addr = p; |
3152 | + |
3153 | + if (!is_valid_ether_addr(addr->sa_data)) |
3154 | + return -EADDRNOTAVAIL; |
3155 | + |
3156 | + if (netif_running(netdev)) |
3157 | + return -EBUSY; |
3158 | + |
3159 | + memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); |
3160 | + memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len); |
3161 | + |
3162 | + atl2_set_mac_addr(&adapter->hw); |
3163 | + |
3164 | + return 0; |
3165 | +} |
3166 | + |
3167 | +/** |
3168 | + * atl2_mii_ioctl - |
3169 | + * @netdev: |
3170 | + * @ifreq: |
3171 | + * @cmd: |
3172 | + **/ |
3173 | +static int |
3174 | +atl2_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) |
3175 | +{ |
3176 | + struct atl2_adapter *adapter = netdev_priv(netdev); |
3177 | + struct mii_ioctl_data *data = if_mii(ifr); |
3178 | + unsigned long flags; |
3179 | + |
3180 | + switch (cmd) { |
3181 | + case SIOCGMIIPHY: |
3182 | + data->phy_id = 0; |
3183 | + break; |
3184 | + case SIOCGMIIREG: |
3185 | + if (!capable(CAP_NET_ADMIN)) |
3186 | + return -EPERM; |
3187 | + spin_lock_irqsave(&adapter->stats_lock, flags); |
3188 | + if (atl2_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, &data->val_out)) { |
3189 | + spin_unlock_irqrestore(&adapter->stats_lock, flags); |
3190 | + return -EIO; |
3191 | + } |
3192 | + spin_unlock_irqrestore(&adapter->stats_lock, flags); |
3193 | + break; |
3194 | + case SIOCSMIIREG: |
3195 | + if (!capable(CAP_NET_ADMIN)) |
3196 | + return -EPERM; |
3197 | + if (data->reg_num & ~(0x1F)) |
3198 | + return -EFAULT; |
3199 | + spin_lock_irqsave(&adapter->stats_lock, flags); |
3200 | + if (atl2_write_phy_reg(&adapter->hw, data->reg_num, data->val_in)) { |
3201 | + spin_unlock_irqrestore(&adapter->stats_lock, flags); |
3202 | + return -EIO; |
3203 | + } |
3204 | + spin_unlock_irqrestore(&adapter->stats_lock, flags); |
3205 | + break; |
3206 | + default: |
3207 | + return -EOPNOTSUPP; |
3208 | + } |
3209 | + return ATL2_SUCCESS; |
3210 | +} |
3211 | + |
3212 | +/** |
3213 | + * atl2_ioctl - |
3214 | + * @netdev: |
3215 | + * @ifreq: |
3216 | + * @cmd: |
3217 | + **/ |
3218 | +static int |
3219 | +atl2_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) |
3220 | +{ |
3221 | + switch (cmd) { |
3222 | + case SIOCGMIIPHY: |
3223 | + case SIOCGMIIREG: |
3224 | + case SIOCSMIIREG: |
3225 | + return atl2_mii_ioctl(netdev, ifr, cmd); |
3226 | +#ifdef ETHTOOL_OPS_COMPAT |
3227 | + case SIOCETHTOOL: |
3228 | + return ethtool_ioctl(ifr); |
3229 | +#endif |
3230 | + default: |
3231 | + return -EOPNOTSUPP; |
3232 | + } |
3233 | +} |
3234 | + |
3235 | +/** |
3236 | + * atl2_tx_timeout - Respond to a Tx Hang |
3237 | + * @netdev: network interface device structure |
3238 | + **/ |
3239 | +static void |
3240 | +atl2_tx_timeout(struct net_device *netdev) |
3241 | +{ |
3242 | + struct atl2_adapter *adapter = netdev_priv(netdev); |
3243 | + |
3244 | + /* Do the reset outside of interrupt context */ |
3245 | + schedule_work(&adapter->reset_task); |
3246 | +} |
3247 | + |
3248 | +/** |
3249 | + * atl2_watchdog - Timer Call-back |
3250 | + * @data: pointer to netdev cast into an unsigned long |
3251 | + **/ |
3252 | +static void |
3253 | +atl2_watchdog(unsigned long data) |
3254 | +{ |
3255 | + struct atl2_adapter *adapter = (struct atl2_adapter *) data; |
3256 | + u32 drop_rxd, drop_rxs; |
3257 | + unsigned long flags; |
3258 | + |
3259 | + if (!test_bit(__ATL2_DOWN, &adapter->flags)) { |
3260 | + spin_lock_irqsave(&adapter->stats_lock, flags); |
3261 | + drop_rxd = ATL2_READ_REG(&adapter->hw, REG_STS_RXD_OV); |
3262 | + drop_rxs = ATL2_READ_REG(&adapter->hw, REG_STS_RXS_OV); |
3263 | + adapter->net_stats.rx_over_errors += (drop_rxd+drop_rxs); |
3264 | + spin_unlock_irqrestore(&adapter->stats_lock, flags); |
3265 | + |
3266 | + /* Reset the timer */ |
3267 | + mod_timer(&adapter->watchdog_timer, jiffies + 4 * HZ); |
3268 | + } |
3269 | +} |
3270 | + |
3271 | +/** |
3272 | + * atl2_phy_config - Timer Call-back |
3273 | + * @data: pointer to netdev cast into an unsigned long |
3274 | + **/ |
3275 | +static void |
3276 | +atl2_phy_config(unsigned long data) |
3277 | +{ |
3278 | + struct atl2_adapter *adapter = (struct atl2_adapter *) data; |
3279 | + struct atl2_hw *hw = &adapter->hw; |
3280 | + unsigned long flags; |
3281 | + |
3282 | + spin_lock_irqsave(&adapter->stats_lock, flags); |
3283 | + atl2_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg); |
3284 | + atl2_write_phy_reg(hw, MII_BMCR, MII_CR_RESET|MII_CR_AUTO_NEG_EN|MII_CR_RESTART_AUTO_NEG); |
3285 | + spin_unlock_irqrestore(&adapter->stats_lock, flags); |
3286 | + clear_bit(0, &adapter->cfg_phy); |
3287 | +} |
3288 | + |
3289 | +int |
3290 | +atl2_up(struct atl2_adapter *adapter) |
3291 | +{ |
3292 | + struct net_device *netdev = adapter->netdev; |
3293 | + int err = 0; |
3294 | + u32 val; |
3295 | + |
3296 | + /* hardware has been reset, we need to reload some things */ |
3297 | + |
3298 | + err = atl2_init_hw(&adapter->hw); |
3299 | + if (err) { |
3300 | + err = -EIO; |
3301 | + return err; |
3302 | + } |
3303 | + |
3304 | + atl2_set_multi(netdev); |
3305 | + init_ring_ptrs(adapter); |
3306 | + |
3307 | +#ifdef NETIF_F_HW_VLAN_TX |
3308 | + atl2_restore_vlan(adapter); |
3309 | +#endif |
3310 | + |
3311 | + if (atl2_configure(adapter)) { |
3312 | + err = -EIO; |
3313 | + goto err_up; |
3314 | + } |
3315 | + |
3316 | + clear_bit(__ATL2_DOWN, &adapter->flags); |
3317 | + |
3318 | + val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL); |
3319 | + ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, val | MASTER_CTRL_MANUAL_INT); |
3320 | + |
3321 | + atl2_irq_enable(adapter); |
3322 | + |
3323 | +err_up: |
3324 | + return err; |
3325 | +} |
3326 | + |
3327 | +void |
3328 | +atl2_reinit_locked(struct atl2_adapter *adapter) |
3329 | +{ |
3330 | + WARN_ON(in_interrupt()); |
3331 | + while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags)) |
3332 | + msleep(1); |
3333 | + atl2_down(adapter); |
3334 | + atl2_up(adapter); |
3335 | + clear_bit(__ATL2_RESETTING, &adapter->flags); |
3336 | +} |
3337 | + |
3338 | +static void |
3339 | +atl2_reset_task(struct work_struct *work) |
3340 | +{ |
3341 | + struct atl2_adapter *adapter; |
3342 | + adapter = container_of(work, struct atl2_adapter, reset_task); |
3343 | + |
3344 | + atl2_reinit_locked(adapter); |
3345 | +} |
3346 | + |
3347 | +static inline void |
3348 | +atl2_setup_mac_ctrl(struct atl2_adapter *adapter) |
3349 | +{ |
3350 | + u32 value; |
3351 | + struct atl2_hw* hw = &adapter->hw; |
3352 | + struct net_device* netdev = adapter->netdev; |
3353 | + |
3354 | + /* Config MAC CTRL Register */ |
3355 | + value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY; |
3356 | + |
3357 | + // duplex |
3358 | + if (FULL_DUPLEX == adapter->link_duplex) |
3359 | + value |= MAC_CTRL_DUPLX; |
3360 | + |
3361 | + // flow control |
3362 | + value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW); |
3363 | + |
3364 | + // PAD & CRC |
3365 | + value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD); |
3366 | + |
3367 | + // preamble length |
3368 | + value |= (((u32)adapter->hw.preamble_len & MAC_CTRL_PRMLEN_MASK) << |
3369 | + MAC_CTRL_PRMLEN_SHIFT); |
3370 | + |
3371 | + // vlan |
3372 | + if (adapter->vlgrp) |
3373 | + value |= MAC_CTRL_RMV_VLAN; |
3374 | + |
3375 | + // filter mode |
3376 | + value |= MAC_CTRL_BC_EN; |
3377 | + if (netdev->flags & IFF_PROMISC) |
3378 | + value |= MAC_CTRL_PROMIS_EN; |
3379 | + else if (netdev->flags & IFF_ALLMULTI) |
3380 | + value |= MAC_CTRL_MC_ALL_EN; |
3381 | + |
3382 | + // half retry buffer |
3383 | + value |= (((u32)(adapter->hw.retry_buf & MAC_CTRL_HALF_LEFT_BUF_MASK)) << |
3384 | + MAC_CTRL_HALF_LEFT_BUF_SHIFT); |
3385 | + |
3386 | + ATL2_WRITE_REG(hw, REG_MAC_CTRL, value); |
3387 | +} |
3388 | + |
3389 | +static int |
3390 | +atl2_check_link(struct atl2_adapter *adapter) |
3391 | +{ |
3392 | + struct atl2_hw *hw = &adapter->hw; |
3393 | + struct net_device * netdev = adapter->netdev; |
3394 | + int ret_val; |
3395 | + u16 speed, duplex, phy_data; |
3396 | + int reconfig = 0; |
3397 | + |
3398 | + // MII_BMSR must read twise |
3399 | + atl2_read_phy_reg(hw, MII_BMSR, &phy_data); |
3400 | + atl2_read_phy_reg(hw, MII_BMSR, &phy_data); |
3401 | + if (!(phy_data&BMSR_LSTATUS)) { // link down |
3402 | + if (netif_carrier_ok(netdev)) { // old link state: Up |
3403 | + u32 value; |
3404 | + //disable rx |
3405 | + value = ATL2_READ_REG(hw, REG_MAC_CTRL); |
3406 | + value &= ~MAC_CTRL_RX_EN; |
3407 | + ATL2_WRITE_REG(hw, REG_MAC_CTRL, value); |
3408 | + adapter->link_speed = SPEED_0; |
3409 | + netif_carrier_off(netdev); |
3410 | + netif_stop_queue(netdev); |
3411 | + } |
3412 | + return ATL2_SUCCESS; |
3413 | + } |
3414 | + |
3415 | + // Link Up |
3416 | + ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex); |
3417 | + if (ret_val) |
3418 | + return ret_val; |
3419 | + switch( hw->MediaType ) { |
3420 | + case MEDIA_TYPE_100M_FULL: |
3421 | + if (speed != SPEED_100 || duplex != FULL_DUPLEX) |
3422 | + reconfig = 1; |
3423 | + break; |
3424 | + case MEDIA_TYPE_100M_HALF: |
3425 | + if (speed != SPEED_100 || duplex != HALF_DUPLEX) |
3426 | + reconfig = 1; |
3427 | + break; |
3428 | + case MEDIA_TYPE_10M_FULL: |
3429 | + if (speed != SPEED_10 || duplex != FULL_DUPLEX) |
3430 | + reconfig = 1; |
3431 | + break; |
3432 | + case MEDIA_TYPE_10M_HALF: |
3433 | + if (speed != SPEED_10 || duplex != HALF_DUPLEX) |
3434 | + reconfig = 1; |
3435 | + break; |
3436 | + } |
3437 | + // link result is our setting |
3438 | + if (0 == reconfig) { |
3439 | + if (adapter->link_speed != speed || adapter->link_duplex != duplex ) { |
3440 | + adapter->link_speed = speed; |
3441 | + adapter->link_duplex = duplex; |
3442 | + atl2_setup_mac_ctrl(adapter); |
3443 | + printk(KERN_INFO "%s: %s NIC Link is Up<%d Mbps %s>\n", |
3444 | + atl2_driver_name, netdev->name, |
3445 | + adapter->link_speed, |
3446 | + adapter->link_duplex == FULL_DUPLEX ? |
3447 | + "Full Duplex" : "Half Duplex"); |
3448 | + } |
3449 | + |
3450 | + if (!netif_carrier_ok(netdev)) { // Link down -> Up |
3451 | + netif_carrier_on(netdev); |
3452 | + netif_wake_queue(netdev); |
3453 | + } |
3454 | + return ATL2_SUCCESS; |
3455 | + } |
3456 | + |
3457 | + // change orignal link status |
3458 | + if (netif_carrier_ok(netdev)) { |
3459 | + u32 value; |
3460 | + // disable rx |
3461 | + value = ATL2_READ_REG(hw, REG_MAC_CTRL); |
3462 | + value &= ~MAC_CTRL_RX_EN; |
3463 | + ATL2_WRITE_REG(hw, REG_MAC_CTRL, value); |
3464 | + |
3465 | + adapter->link_speed = SPEED_0; |
3466 | + netif_carrier_off(netdev); |
3467 | + netif_stop_queue(netdev); |
3468 | + } |
3469 | + |
3470 | + // auto-neg, insert timer to re-config phy (if interval smaller than 5 seconds, something strange) |
3471 | + if (!test_bit(__ATL2_DOWN, &adapter->flags)) { |
3472 | + if (!test_and_set_bit(0, &adapter->cfg_phy)) { |
3473 | + mod_timer(&adapter->phy_config_timer, jiffies + 5 * HZ); |
3474 | + } |
3475 | + } |
3476 | + |
3477 | + return ATL2_SUCCESS; |
3478 | +} |
3479 | + |
3480 | +/** |
3481 | + * atl2_link_chg_task - deal with link change event Out of interrupt context |
3482 | + * @netdev: network interface device structure |
3483 | + **/ |
3484 | +static void |
3485 | +atl2_link_chg_task(struct work_struct *work) |
3486 | +{ |
3487 | + struct atl2_adapter *adapter; |
3488 | + unsigned long flags; |
3489 | + |
3490 | + adapter = container_of(work, struct atl2_adapter, link_chg_task); |
3491 | + |
3492 | + spin_lock_irqsave(&adapter->stats_lock, flags); |
3493 | + atl2_check_link(adapter); |
3494 | + spin_unlock_irqrestore(&adapter->stats_lock, flags); |
3495 | +} |
3496 | + |
3497 | +static void |
3498 | +atl2_setup_pcicmd(struct pci_dev *pdev) |
3499 | +{ |
3500 | + u16 cmd; |
3501 | + |
3502 | + pci_read_config_word(pdev, PCI_COMMAND, &cmd); |
3503 | + |
3504 | + if (cmd & PCI_COMMAND_INTX_DISABLE) |
3505 | + cmd &= ~PCI_COMMAND_INTX_DISABLE; |
3506 | + if (cmd & PCI_COMMAND_IO) |
3507 | + cmd &= ~PCI_COMMAND_IO; |
3508 | + if (0 == (cmd & PCI_COMMAND_MEMORY)) |
3509 | + cmd |= PCI_COMMAND_MEMORY; |
3510 | + if (0 == (cmd & PCI_COMMAND_MASTER)) |
3511 | + cmd |= PCI_COMMAND_MASTER; |
3512 | + pci_write_config_word(pdev, PCI_COMMAND, cmd); |
3513 | + |
3514 | + /* |
3515 | + * some motherboards BIOS(PXE/EFI) driver may set PME |
3516 | + * while they transfer control to OS (Windows/Linux) |
3517 | + * so we should clear this bit before NIC work normally |
3518 | + */ |
3519 | + pci_write_config_dword(pdev, REG_PM_CTRLSTAT, 0); |
3520 | +} |
3521 | + |
3522 | +/** |
3523 | + * atl2_probe - Device Initialization Routine |
3524 | + * @pdev: PCI device information struct |
3525 | + * @ent: entry in atl2_pci_tbl |
3526 | + * |
3527 | + * Returns 0 on success, negative on failure |
3528 | + * |
3529 | + * atl2_probe initializes an adapter identified by a pci_dev structure. |
3530 | + * The OS initialization, configuring of the adapter private structure, |
3531 | + * and a hardware reset occur. |
3532 | + **/ |
3533 | +static int __devinit |
3534 | +atl2_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
3535 | +{ |
3536 | + struct net_device *netdev; |
3537 | + struct atl2_adapter *adapter; |
3538 | + static int cards_found = 0; |
3539 | + unsigned long mmio_start; |
3540 | + int mmio_len; |
3541 | + int err; |
3542 | + |
3543 | + if((err = pci_enable_device(pdev))) |
3544 | + return err; |
3545 | + |
3546 | + /* |
3547 | + * atl2 is a shared-high-32-bit device, so we're stuck with 32-bit DMA |
3548 | + * until the kernel has the proper infrastructure to support 64-bit DMA |
3549 | + * on these devices. |
3550 | + */ |
3551 | + if ((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) && |
3552 | + (err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))) { |
3553 | + printk(KERN_ERR "atl2: No usable DMA configuration, aborting\n"); |
3554 | + goto err_dma; |
3555 | + } |
3556 | + |
3557 | + // Mark all PCI regions associated with PCI device |
3558 | + // pdev as being reserved by owner atl2_driver_name |
3559 | + if((err = pci_request_regions(pdev, atl2_driver_name))) |
3560 | + goto err_pci_reg; |
3561 | + |
3562 | + // Enables bus-mastering on the device and calls |
3563 | + // pcibios_set_master to do the needed arch specific settings |
3564 | + pci_set_master(pdev); |
3565 | + |
3566 | + err = -ENOMEM; |
3567 | + netdev = alloc_etherdev(sizeof(struct atl2_adapter)); |
3568 | + if(!netdev) |
3569 | + goto err_alloc_etherdev; |
3570 | + |
3571 | + SET_NETDEV_DEV(netdev, &pdev->dev); |
3572 | + |
3573 | + pci_set_drvdata(pdev, netdev); |
3574 | + adapter = netdev_priv(netdev); |
3575 | + adapter->netdev = netdev; |
3576 | + adapter->pdev = pdev; |
3577 | + adapter->hw.back = adapter; |
3578 | + |
3579 | + mmio_start = pci_resource_start(pdev, 0x0); |
3580 | + mmio_len = pci_resource_len(pdev, 0x0); |
3581 | + |
3582 | + adapter->hw.mem_rang = (u32)mmio_len; |
3583 | + adapter->hw.hw_addr = ioremap(mmio_start, mmio_len); |
3584 | + if(!adapter->hw.hw_addr) { |
3585 | + err = -EIO; |
3586 | + goto err_ioremap; |
3587 | + } |
3588 | + |
3589 | + atl2_setup_pcicmd(pdev); |
3590 | + |
3591 | + netdev->open = &atl2_open; |
3592 | + netdev->stop = &atl2_close; |
3593 | + netdev->hard_start_xmit = &atl2_xmit_frame; |
3594 | + netdev->get_stats = &atl2_get_stats; |
3595 | + netdev->set_multicast_list = &atl2_set_multi; |
3596 | + netdev->set_mac_address = &atl2_set_mac; |
3597 | + netdev->change_mtu = &atl2_change_mtu; |
3598 | + netdev->do_ioctl = &atl2_ioctl; |
3599 | + atl2_set_ethtool_ops(netdev); |
3600 | + |
3601 | +#ifdef HAVE_TX_TIMEOUT |
3602 | + netdev->tx_timeout = &atl2_tx_timeout; |
3603 | + netdev->watchdog_timeo = 5 * HZ; //FIXME -- CHS |
3604 | +#endif |
3605 | +#ifdef NETIF_F_HW_VLAN_TX |
3606 | + netdev->vlan_rx_register = atl2_vlan_rx_register; |
3607 | +#endif |
3608 | + strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); |
3609 | + |
3610 | + netdev->mem_start = mmio_start; |
3611 | + netdev->mem_end = mmio_start + mmio_len; |
3612 | + //netdev->base_addr = adapter->io_base; |
3613 | + adapter->bd_number = cards_found; |
3614 | + adapter->pci_using_64 = false; |
3615 | + |
3616 | + /* setup the private structure */ |
3617 | + |
3618 | + if((err = atl2_sw_init(adapter))) |
3619 | + goto err_sw_init; |
3620 | + |
3621 | + err = -EIO; |
3622 | + |
3623 | +#ifdef NETIF_F_HW_VLAN_TX |
3624 | + netdev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX ); |
3625 | +#endif |
3626 | + |
3627 | +#ifdef NETIF_F_LLTX |
3628 | + netdev->features |= NETIF_F_LLTX; |
3629 | +#endif |
3630 | + |
3631 | + /* Init PHY as early as possible due to power saving issue */ |
3632 | + atl2_phy_init(&adapter->hw); |
3633 | + |
3634 | + /* reset the controller to |
3635 | + * put the device in a known good starting state */ |
3636 | + |
3637 | + if (atl2_reset_hw(&adapter->hw)) { |
3638 | + err = -EIO; |
3639 | + goto err_reset; |
3640 | + } |
3641 | + |
3642 | + /* copy the MAC address out of the EEPROM */ |
3643 | + atl2_read_mac_addr(&adapter->hw); |
3644 | + memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len); |
3645 | +//FIXME: do we still need this? |
3646 | +#ifdef ETHTOOL_GPERMADDR |
3647 | + memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len); |
3648 | + |
3649 | + if (!is_valid_ether_addr(netdev->perm_addr)) { |
3650 | +#else |
3651 | + if (!is_valid_ether_addr(netdev->dev_addr)) { |
3652 | +#endif |
3653 | + err = -EIO; |
3654 | + goto err_eeprom; |
3655 | + } |
3656 | + |
3657 | + atl2_check_options(adapter); |
3658 | + |
3659 | + init_timer(&adapter->watchdog_timer); |
3660 | + adapter->watchdog_timer.function = &atl2_watchdog; |
3661 | + adapter->watchdog_timer.data = (unsigned long) adapter; |
3662 | + |
3663 | + init_timer(&adapter->phy_config_timer); |
3664 | + adapter->phy_config_timer.function = &atl2_phy_config; |
3665 | + adapter->phy_config_timer.data = (unsigned long) adapter; |
3666 | + |
3667 | + INIT_WORK(&adapter->reset_task, atl2_reset_task); |
3668 | + INIT_WORK(&adapter->link_chg_task, atl2_link_chg_task); |
3669 | + |
3670 | + strcpy(netdev->name, "eth%d"); // ?? |
3671 | + if((err = register_netdev(netdev))) |
3672 | + goto err_register; |
3673 | + |
3674 | + /* assume we have no link for now */ |
3675 | + netif_carrier_off(netdev); |
3676 | + netif_stop_queue(netdev); |
3677 | + |
3678 | + cards_found++; |
3679 | + |
3680 | + return 0; |
3681 | + |
3682 | +//err_init_hw: |
3683 | +err_reset: |
3684 | +err_register: |
3685 | +err_sw_init: |
3686 | +err_eeprom: |
3687 | + iounmap(adapter->hw.hw_addr); |
3688 | +err_ioremap: |
3689 | + free_netdev(netdev); |
3690 | +err_alloc_etherdev: |
3691 | + pci_release_regions(pdev); |
3692 | +err_pci_reg: |
3693 | +err_dma: |
3694 | + pci_disable_device(pdev); |
3695 | + return err; |
3696 | +} |
3697 | + |
3698 | +/** |
3699 | + * atl2_remove - Device Removal Routine |
3700 | + * @pdev: PCI device information struct |
3701 | + * |
3702 | + * atl2_remove is called by the PCI subsystem to alert the driver |
3703 | + * that it should release a PCI device. The could be caused by a |
3704 | + * Hot-Plug event, or because the driver is going to be removed from |
3705 | + * memory. |
3706 | + **/ |
3707 | +/* FIXME: write the original MAC address back in case it was changed from a |
3708 | + * BIOS-set value, as in atl1 -- CHS */ |
3709 | +static void __devexit |
3710 | +atl2_remove(struct pci_dev *pdev) |
3711 | +{ |
3712 | + struct net_device *netdev = pci_get_drvdata(pdev); |
3713 | + struct atl2_adapter *adapter = netdev_priv(netdev); |
3714 | + |
3715 | + /* flush_scheduled work may reschedule our watchdog task, so |
3716 | + * explicitly disable watchdog tasks from being rescheduled */ |
3717 | + set_bit(__ATL2_DOWN, &adapter->flags); |
3718 | + |
3719 | + del_timer_sync(&adapter->watchdog_timer); |
3720 | + del_timer_sync(&adapter->phy_config_timer); |
3721 | + |
3722 | + flush_scheduled_work(); |
3723 | + |
3724 | + unregister_netdev(netdev); |
3725 | + |
3726 | + atl2_force_ps(&adapter->hw); |
3727 | + |
3728 | + iounmap(adapter->hw.hw_addr); |
3729 | + pci_release_regions(pdev); |
3730 | + |
3731 | + free_netdev(netdev); |
3732 | + |
3733 | + pci_disable_device(pdev); |
3734 | +} |
3735 | + |
3736 | +static int |
3737 | +atl2_suspend(struct pci_dev *pdev, pm_message_t state) |
3738 | +{ |
3739 | + struct net_device *netdev = pci_get_drvdata(pdev); |
3740 | + struct atl2_adapter *adapter = netdev_priv(netdev); |
3741 | + struct atl2_hw * hw = &adapter->hw; |
3742 | + u16 speed, duplex; |
3743 | + u32 ctrl = 0; |
3744 | + u32 wufc = adapter->wol; |
3745 | + |
3746 | +#ifdef CONFIG_PM |
3747 | + int retval = 0; |
3748 | +#endif |
3749 | + |
3750 | + netif_device_detach(netdev); |
3751 | + |
3752 | + if (netif_running(netdev)) { |
3753 | + WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags)); |
3754 | + atl2_down(adapter); |
3755 | + } |
3756 | + |
3757 | +#ifdef CONFIG_PM |
3758 | + retval = pci_save_state(pdev); |
3759 | + if (retval) |
3760 | + return retval; |
3761 | +#endif |
3762 | + |
3763 | + atl2_read_phy_reg(hw, MII_BMSR, (u16*)&ctrl); |
3764 | + atl2_read_phy_reg(hw, MII_BMSR, (u16*)&ctrl); |
3765 | + if(ctrl & BMSR_LSTATUS) |
3766 | + wufc &= ~ATL2_WUFC_LNKC; |
3767 | + |
3768 | + if (0 != (ctrl & BMSR_LSTATUS) && 0 != wufc) { |
3769 | + u32 ret_val; |
3770 | + /* get current link speed & duplex */ |
3771 | + ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex); |
3772 | + if (ret_val) { |
3773 | + printk(KERN_DEBUG "%s: get speed&duplex error while suspend\n", atl2_driver_name); |
3774 | + goto wol_dis; |
3775 | + } |
3776 | + |
3777 | + ctrl = 0; |
3778 | + |
3779 | + /* turn on magic packet wol */ |
3780 | + if (wufc & ATL2_WUFC_MAG) |
3781 | + ctrl |= (WOL_MAGIC_EN | WOL_MAGIC_PME_EN); |
3782 | + |
3783 | + /* ignore Link Chg event when Link is up */ |
3784 | + ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl); |
3785 | + |
3786 | + /* Config MAC CTRL Register */ |
3787 | + ctrl = MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY; |
3788 | + if (FULL_DUPLEX == adapter->link_duplex) |
3789 | + ctrl |= MAC_CTRL_DUPLX; |
3790 | + ctrl |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD); |
3791 | + ctrl |= (((u32)adapter->hw.preamble_len & |
3792 | + MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT); |
3793 | + ctrl |= (((u32)(adapter->hw.retry_buf & |
3794 | + MAC_CTRL_HALF_LEFT_BUF_MASK)) << |
3795 | + MAC_CTRL_HALF_LEFT_BUF_SHIFT); |
3796 | + if (wufc & ATL2_WUFC_MAG) { |
3797 | + /* magic packet maybe Broadcast&multicast&Unicast frame */ |
3798 | + ctrl |= MAC_CTRL_BC_EN; |
3799 | + } |
3800 | + |
3801 | + ATL2_WRITE_REG(hw, REG_MAC_CTRL, ctrl); |
3802 | + |
3803 | + /* pcie patch */ |
3804 | + ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC); |
3805 | + ctrl |= PCIE_PHYMISC_FORCE_RCV_DET; |
3806 | + ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl); |
3807 | + ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1); |
3808 | + ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK; |
3809 | + ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl); |
3810 | + |
3811 | + pci_enable_wake(pdev, pci_choose_state(pdev, state), 1); |
3812 | + goto suspend_exit; |
3813 | + } |
3814 | + |
3815 | + if (0 == (ctrl&BMSR_LSTATUS) && 0 != (wufc&ATL2_WUFC_LNKC)) { |
3816 | + /* link is down, so only LINK CHG WOL event enable */ |
3817 | + ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN); |
3818 | + ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl); |
3819 | + ATL2_WRITE_REG(hw, REG_MAC_CTRL, 0); |
3820 | + |
3821 | + /* pcie patch */ |
3822 | + ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC); |
3823 | + ctrl |= PCIE_PHYMISC_FORCE_RCV_DET; |
3824 | + ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl); |
3825 | + ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1); |
3826 | + ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK; |
3827 | + ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl); |
3828 | + |
3829 | + hw->phy_configured = false; /* re-init PHY when resume */ |
3830 | + |
3831 | + pci_enable_wake(pdev, pci_choose_state(pdev, state), 1); |
3832 | + |
3833 | + goto suspend_exit; |
3834 | + } |
3835 | + |
3836 | +wol_dis: |
3837 | + /* WOL disabled */ |
3838 | + ATL2_WRITE_REG(hw, REG_WOL_CTRL, 0); |
3839 | + |
3840 | + /* pcie patch */ |
3841 | + ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC); |
3842 | + ctrl |= PCIE_PHYMISC_FORCE_RCV_DET; |
3843 | + ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl); |
3844 | + ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1); |
3845 | + ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK; |
3846 | + ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl); |
3847 | + |
3848 | + atl2_force_ps(hw); |
3849 | + hw->phy_configured = false; /* re-init PHY when resume */ |
3850 | + |
3851 | + pci_enable_wake(pdev, pci_choose_state(pdev, state), 0); |
3852 | + |
3853 | +suspend_exit: |
3854 | + if (netif_running(netdev)) |
3855 | + atl2_free_irq(adapter); |
3856 | + |
3857 | + pci_disable_device(pdev); |
3858 | + |
3859 | + pci_set_power_state(pdev, pci_choose_state(pdev, state)); |
3860 | + |
3861 | + return 0; |
3862 | +} |
3863 | + |
3864 | +#ifdef CONFIG_PM |
3865 | +static int |
3866 | +atl2_resume(struct pci_dev *pdev) |
3867 | +{ |
3868 | + struct net_device *netdev = pci_get_drvdata(pdev); |
3869 | + struct atl2_adapter *adapter = netdev_priv(netdev); |
3870 | + u32 err; |
3871 | + |
3872 | + pci_set_power_state(pdev, PCI_D0); |
3873 | + pci_restore_state(pdev); |
3874 | + |
3875 | + if ((err = pci_enable_device(pdev))) { |
3876 | + printk(KERN_ERR "atl2: Cannot enable PCI device from suspend\n"); |
3877 | + return err; |
3878 | + } |
3879 | + |
3880 | + pci_set_master(pdev); |
3881 | + |
3882 | + ATL2_READ_REG(&adapter->hw, REG_WOL_CTRL); /* clear WOL status */ |
3883 | + |
3884 | + pci_enable_wake(pdev, PCI_D3hot, 0); |
3885 | + pci_enable_wake(pdev, PCI_D3cold, 0); |
3886 | + |
3887 | + ATL2_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0); |
3888 | + |
3889 | + if (netif_running(netdev) && (err = atl2_request_irq(adapter))) |
3890 | + return err; |
3891 | + |
3892 | + atl2_reset_hw(&adapter->hw); |
3893 | + |
3894 | + if(netif_running(netdev)) |
3895 | + atl2_up(adapter); |
3896 | + |
3897 | + netif_device_attach(netdev); |
3898 | + |
3899 | + return 0; |
3900 | +} |
3901 | +#endif |
3902 | + |
3903 | +static void |
3904 | +atl2_shutdown(struct pci_dev *pdev) |
3905 | +{ |
3906 | + atl2_suspend(pdev, PMSG_SUSPEND); |
3907 | +} |
3908 | + |
3909 | +static struct pci_driver atl2_driver = { |
3910 | + .name = atl2_driver_name, |
3911 | + .id_table = atl2_pci_tbl, |
3912 | + .probe = atl2_probe, |
3913 | + .remove = __devexit_p(atl2_remove), |
3914 | + /* Power Managment Hooks */ |
3915 | + .suspend = atl2_suspend, |
3916 | +#ifdef CONFIG_PM |
3917 | + .resume = atl2_resume, |
3918 | +#endif |
3919 | + .shutdown = atl2_shutdown, |
3920 | +}; |
3921 | + |
3922 | +/** |
3923 | + * atl2_init_module - Driver Registration Routine |
3924 | + * |
3925 | + * atl2_init_module is the first routine called when the driver is |
3926 | + * loaded. All it does is register with the PCI subsystem. |
3927 | + **/ |
3928 | +static int __init |
3929 | +atl2_init_module(void) |
3930 | +{ |
3931 | + int ret; |
3932 | + printk(KERN_INFO "%s - version %s\n", atl2_driver_string, atl2_driver_version); |
3933 | + printk(KERN_INFO "%s\n", atl2_copyright); |
3934 | + |
3935 | + ret = pci_register_driver(&atl2_driver); |
3936 | + if (copybreak != COPYBREAK_DEFAULT) { |
3937 | + if (copybreak == 0) |
3938 | + printk(KERN_INFO "atl2: copybreak disabled\n"); |
3939 | + else |
3940 | + printk(KERN_INFO "atl2: copybreak enabled for packets <= %u bytes\n", copybreak); |
3941 | + } |
3942 | + return ret; |
3943 | +} |
3944 | +module_init(atl2_init_module); |
3945 | + |
3946 | +/** |
3947 | + * atl2_exit_module - Driver Exit Cleanup Routine |
3948 | + * |
3949 | + * atl2_exit_module is called just before the driver is removed |
3950 | + * from memory. |
3951 | + **/ |
3952 | +static void __exit |
3953 | +atl2_exit_module(void) |
3954 | +{ |
3955 | + pci_unregister_driver(&atl2_driver); |
3956 | +} |
3957 | +module_exit(atl2_exit_module); |
3958 | + |
3959 | +void |
3960 | +atl2_read_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value) |
3961 | +{ |
3962 | + struct atl2_adapter *adapter = hw->back; |
3963 | + pci_read_config_word(adapter->pdev, reg, value); |
3964 | +} |
3965 | + |
3966 | +void |
3967 | +atl2_write_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value) |
3968 | +{ |
3969 | + struct atl2_adapter *adapter = hw->back; |
3970 | + pci_write_config_word(adapter->pdev, reg, *value); |
3971 | +} |
3972 | Index: linux-2.6.26.noarch/drivers/net/atl2/atl2_osdep.h |
3973 | =================================================================== |
3974 | --- /dev/null |
3975 | +++ linux-2.6.26.noarch/drivers/net/atl2/atl2_osdep.h |
3976 | @@ -0,0 +1,72 @@ |
3977 | +/* atl2_osdep.h -- atl2 compat cruft |
3978 | + * |
3979 | + * Copyright(c) 2007 Atheros Corporation. All rights reserved. |
3980 | + * Copyright(c) 2006 xiong huang <xiong.huang@atheros.com> |
3981 | + * Copyright(c) 2007 Chris Snook <csnook@redhat.com> |
3982 | + * |
3983 | + * Derived from Intel e1000 driver |
3984 | + * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. |
3985 | + * |
3986 | + * This program is free software; you can redistribute it and/or modify it |
3987 | + * under the terms of the GNU General Public License as published by the Free |
3988 | + * Software Foundation; either version 2 of the License, or (at your option) |
3989 | + * any later version. |
3990 | + * |
3991 | + * This program is distributed in the hope that it will be useful, but WITHOUT |
3992 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
3993 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
3994 | + * more details. |
3995 | + * |
3996 | + * You should have received a copy of the GNU General Public License along with |
3997 | + * this program; if not, write to the Free Software Foundation, Inc., 59 |
3998 | + * Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
3999 | + */ |
4000 | + |
4001 | +#ifndef _ATL2_OSDEP_H_ |
4002 | +#define _ATL2_OSDEP_H_ |
4003 | + |
4004 | +#include <linux/pci.h> |
4005 | +#include <linux/delay.h> |
4006 | +#include <linux/interrupt.h> |
4007 | +#include <linux/if_ether.h> |
4008 | + |
4009 | +#define usec_delay(x) udelay(x) |
4010 | +#ifndef msec_delay |
4011 | +#define msec_delay(x) do { \ |
4012 | + if(in_interrupt()) BUG(); \ |
4013 | + else msleep(x); \ |
4014 | + } while (0) |
4015 | + |
4016 | +/* Some workarounds require millisecond delays and are run during interrupt |
4017 | + * context. Most notably, when establishing link, the phy may need tweaking |
4018 | + * but cannot process phy register reads/writes faster than millisecond |
4019 | + * intervals...and we establish link due to a "link status change" interrupt. |
4020 | + */ |
4021 | +#define msec_delay_irq(x) mdelay(x) |
4022 | +#endif |
4023 | + |
4024 | +#define PCI_COMMAND_REGISTER PCI_COMMAND |
4025 | +#define CMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE |
4026 | +#define ETH_ADDR_LEN ETH_ALEN |
4027 | + |
4028 | +#define ATL2_WRITE_REG(a, reg, value) (writel((value), ((a)->hw_addr + reg))) |
4029 | + |
4030 | +#define ATL2_WRITE_FLUSH(a) (readl((a)->hw_addr)) |
4031 | + |
4032 | +#define ATL2_READ_REG(a, reg) (readl((a)->hw_addr + reg)) |
4033 | + |
4034 | +#define ATL2_WRITE_REGB(a, reg, value) (writeb((value), ((a)->hw_addr + reg))) |
4035 | + |
4036 | +#define ATL2_READ_REGB(a, reg) (readb((a)->hw_addr + reg)) |
4037 | + |
4038 | +#define ATL2_WRITE_REGW(a, reg, value) (writew((value), ((a)->hw_addr + reg))) |
4039 | + |
4040 | +#define ATL2_READ_REGW(a, reg) (readw((a)->hw_addr + reg)) |
4041 | + |
4042 | +#define ATL2_WRITE_REG_ARRAY(a, reg, offset, value) \ |
4043 | + (writel((value), (((a)->hw_addr + reg) + ((offset) << 2)))) |
4044 | + |
4045 | +#define ATL2_READ_REG_ARRAY(a, reg, offset) \ |
4046 | + (readl(((a)->hw_addr + reg) + ((offset) << 2))) |
4047 | + |
4048 | +#endif /* _ATL2_OSDEP_H_ */ |
4049 | Index: linux-2.6.26.noarch/drivers/net/atl2/atl2_param.c |
4050 | =================================================================== |
4051 | --- /dev/null |
4052 | +++ linux-2.6.26.noarch/drivers/net/atl2/atl2_param.c |
4053 | @@ -0,0 +1,317 @@ |
4054 | +/* atl2_param.c -- atl2 parameter processing |
4055 | + * |
4056 | + * Copyright(c) 2007 Atheros Corporation. All rights reserved. |
4057 | + * Copyright(c) 2006 xiong huang <xiong.huang@atheros.com> |
4058 | + * Copyright(c) 2007 Chris Snook <csnook@redhat.com> |
4059 | + * |
4060 | + * Derived from Intel e1000 driver |
4061 | + * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. |
4062 | + * |
4063 | + * This program is free software; you can redistribute it and/or modify it |
4064 | + * under the terms of the GNU General Public License as published by the Free |
4065 | + * Software Foundation; either version 2 of the License, or (at your option) |
4066 | + * any later version. |
4067 | + * |
4068 | + * This program is distributed in the hope that it will be useful, but WITHOUT |
4069 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
4070 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
4071 | + * more details. |
4072 | + * |
4073 | + * You should have received a copy of the GNU General Public License along with |
4074 | + * this program; if not, write to the Free Software Foundation, Inc., 59 |
4075 | + * Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
4076 | + */ |
4077 | + |
4078 | +#include <linux/netdevice.h> |
4079 | +#include "atl2.h" |
4080 | + |
4081 | +/* This is the only thing that needs to be changed to adjust the |
4082 | + * maximum number of ports that the driver can manage. |
4083 | + */ |
4084 | +#define ATL2_MAX_NIC 4 |
4085 | + |
4086 | +#define OPTION_UNSET -1 |
4087 | +#define OPTION_DISABLED 0 |
4088 | +#define OPTION_ENABLED 1 |
4089 | + |
4090 | +/* All parameters are treated the same, as an integer array of values. |
4091 | + * This macro just reduces the need to repeat the same declaration code |
4092 | + * over and over (plus this helps to avoid typo bugs). |
4093 | + */ |
4094 | +#define ATL2_PARAM_INIT { [0 ... ATL2_MAX_NIC] = OPTION_UNSET } |
4095 | +#ifndef module_param_array |
4096 | +/* Module Parameters are always initialized to -1, so that the driver |
4097 | + * can tell the difference between no user specified value or the |
4098 | + * user asking for the default value. |
4099 | + * The true default values are loaded in when atl2_check_options is called. |
4100 | + * |
4101 | + * This is a GCC extension to ANSI C. |
4102 | + * See the item "Labeled Elements in Initializers" in the section |
4103 | + * "Extensions to the C Language Family" of the GCC documentation. |
4104 | + */ |
4105 | + |
4106 | +#define ATL2_PARAM(X, desc) \ |
4107 | + static const int __devinitdata X[ATL2_MAX_NIC + 1] = ATL2_PARAM_INIT; \ |
4108 | + MODULE_PARM(X, "1-" __MODULE_STRING(ATL2_MAX_NIC) "i"); \ |
4109 | + MODULE_PARM_DESC(X, desc); |
4110 | +#else |
4111 | +#define ATL2_PARAM(X, desc) \ |
4112 | + static int __devinitdata X[ATL2_MAX_NIC+1] = ATL2_PARAM_INIT; \ |
4113 | + static int num_##X = 0; \ |
4114 | + module_param_array_named(X, X, int, &num_##X, 0); \ |
4115 | + MODULE_PARM_DESC(X, desc); |
4116 | +#endif |
4117 | + |
4118 | +/* Transmit Memory Size |
4119 | + * |
4120 | + * Valid Range: 64-2048 |
4121 | + * |
4122 | + * Default Value: 128 |
4123 | + */ |
4124 | +#define ATL2_MIN_TX_MEMSIZE 4 // 4KB |
4125 | +#define ATL2_MAX_TX_MEMSIZE 64 // 64KB |
4126 | +#define ATL2_DEFAULT_TX_MEMSIZE 8 // 8KB |
4127 | +ATL2_PARAM(TxMemSize, "Bytes of Transmit Memory"); |
4128 | + |
4129 | +/* Receive Memory Block Count |
4130 | + * |
4131 | + * Valid Range: 16-512 |
4132 | + * |
4133 | + * Default Value: 128 |
4134 | + */ |
4135 | +#define ATL2_MIN_RXD_COUNT 16 |
4136 | +#define ATL2_MAX_RXD_COUNT 512 |
4137 | +#define ATL2_DEFAULT_RXD_COUNT 64 |
4138 | +ATL2_PARAM(RxMemBlock, "Number of receive memory block"); |
4139 | + |
4140 | +/* User Specified MediaType Override |
4141 | + * |
4142 | + * Valid Range: 0-5 |
4143 | + * - 0 - auto-negotiate at all supported speeds |
4144 | + * - 1 - only link at 1000Mbps Full Duplex |
4145 | + * - 2 - only link at 100Mbps Full Duplex |
4146 | + * - 3 - only link at 100Mbps Half Duplex |
4147 | + * - 4 - only link at 10Mbps Full Duplex |
4148 | + * - 5 - only link at 10Mbps Half Duplex |
4149 | + * Default Value: 0 |
4150 | + */ |
4151 | +ATL2_PARAM(MediaType, "MediaType Select"); |
4152 | + |
4153 | +/* Interrupt Moderate Timer in units of 2 us |
4154 | + * |
4155 | + * Valid Range: 10-65535 |
4156 | + * |
4157 | + * Default Value: 45000(90ms) |
4158 | + */ |
4159 | +#define INT_MOD_DEFAULT_CNT 100 // 200us |
4160 | +#define INT_MOD_MAX_CNT 65000 |
4161 | +#define INT_MOD_MIN_CNT 50 |
4162 | +ATL2_PARAM(IntModTimer, "Interrupt Moderator Timer"); |
4163 | + |
4164 | +/* FlashVendor |
4165 | + * Valid Range: 0-2 |
4166 | + * 0 - Atmel |
4167 | + * 1 - SST |
4168 | + * 2 - ST |
4169 | + */ |
4170 | +ATL2_PARAM(FlashVendor, "SPI Flash Vendor"); |
4171 | + |
4172 | +#define AUTONEG_ADV_DEFAULT 0x2F |
4173 | +#define AUTONEG_ADV_MASK 0x2F |
4174 | +#define FLOW_CONTROL_DEFAULT FLOW_CONTROL_FULL |
4175 | + |
4176 | +#define FLASH_VENDOR_DEFAULT 0 |
4177 | +#define FLASH_VENDOR_MIN 0 |
4178 | +#define FLASH_VENDOR_MAX 2 |
4179 | + |
4180 | +struct atl2_option { |
4181 | + enum { enable_option, range_option, list_option } type; |
4182 | + char *name; |
4183 | + char *err; |
4184 | + int def; |
4185 | + union { |
4186 | + struct { /* range_option info */ |
4187 | + int min; |
4188 | + int max; |
4189 | + } r; |
4190 | + struct { /* list_option info */ |
4191 | + int nr; |
4192 | + struct atl2_opt_list { int i; char *str; } *p; |
4193 | + } l; |
4194 | + } arg; |
4195 | +}; |
4196 | + |
4197 | +static int __devinit |
4198 | +atl2_validate_option(int *value, struct atl2_option *opt) |
4199 | +{ |
4200 | + int i; |
4201 | + struct atl2_opt_list *ent; |
4202 | + |
4203 | + if(*value == OPTION_UNSET) { |
4204 | + *value = opt->def; |
4205 | + return 0; |
4206 | + } |
4207 | + |
4208 | + switch (opt->type) { |
4209 | + case enable_option: |
4210 | + switch (*value) { |
4211 | + case OPTION_ENABLED: |
4212 | + printk(KERN_INFO "%s Enabled\n", opt->name); |
4213 | + return 0; |
4214 | + break; |
4215 | + case OPTION_DISABLED: |
4216 | + printk(KERN_INFO "%s Disabled\n", opt->name); |
4217 | + return 0; |
4218 | + break; |
4219 | + } |
4220 | + break; |
4221 | + case range_option: |
4222 | + if(*value >= opt->arg.r.min && *value <= opt->arg.r.max) { |
4223 | + printk(KERN_INFO "%s set to %i\n", opt->name, *value); |
4224 | + return 0; |
4225 | + } |
4226 | + break; |
4227 | + case list_option: |
4228 | + for(i = 0; i < opt->arg.l.nr; i++) { |
4229 | + ent = &opt->arg.l.p[i]; |
4230 | + if(*value == ent->i) { |
4231 | + if(ent->str[0] != '\0') |
4232 | + printk(KERN_INFO "%s\n", ent->str); |
4233 | + return 0; |
4234 | + } |
4235 | + } |
4236 | + break; |
4237 | + default: |
4238 | + BUG(); |
4239 | + } |
4240 | + |
4241 | + printk(KERN_INFO "Invalid %s specified (%i) %s\n", |
4242 | + opt->name, *value, opt->err); |
4243 | + *value = opt->def; |
4244 | + return -1; |
4245 | +} |
4246 | + |
4247 | +/** |
4248 | + * atl2_check_options - Range Checking for Command Line Parameters |
4249 | + * @adapter: board private structure |
4250 | + * |
4251 | + * This routine checks all command line parameters for valid user |
4252 | + * input. If an invalid value is given, or if no user specified |
4253 | + * value exists, a default value is used. The final value is stored |
4254 | + * in a variable in the adapter structure. |
4255 | + **/ |
4256 | +void __devinit |
4257 | +atl2_check_options(struct atl2_adapter *adapter) |
4258 | +{ |
4259 | + int val; |
4260 | + struct atl2_option opt; |
4261 | + int bd = adapter->bd_number; |
4262 | + if(bd >= ATL2_MAX_NIC) { |
4263 | + printk(KERN_NOTICE "Warning: no configuration for board #%i\n", bd); |
4264 | + printk(KERN_NOTICE "Using defaults for all values\n"); |
4265 | +#ifndef module_param_array |
4266 | + bd = ATL2_MAX_NIC; |
4267 | +#endif |
4268 | + } |
4269 | + |
4270 | + /* Bytes of Transmit Memory */ |
4271 | + opt.type = range_option; |
4272 | + opt.name = "Bytes of Transmit Memory"; |
4273 | + opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_TX_MEMSIZE); |
4274 | + opt.def = ATL2_DEFAULT_TX_MEMSIZE; |
4275 | + opt.arg.r.min = ATL2_MIN_TX_MEMSIZE; |
4276 | + opt.arg.r.max = ATL2_MAX_TX_MEMSIZE; |
4277 | +#ifdef module_param_array |
4278 | + if(num_TxMemSize > bd) { |
4279 | +#endif |
4280 | + val = TxMemSize[bd]; |
4281 | + atl2_validate_option(&val, &opt); |
4282 | + adapter->txd_ring_size = ((u32) val) * 1024; |
4283 | +#ifdef module_param_array |
4284 | + } else { |
4285 | + adapter->txd_ring_size = ((u32)opt.def) * 1024; |
4286 | + } |
4287 | +#endif |
4288 | + // txs ring size: |
4289 | + adapter->txs_ring_size = adapter->txd_ring_size / 128; |
4290 | + if (adapter->txs_ring_size > 160) |
4291 | + adapter->txs_ring_size = 160; |
4292 | + |
4293 | + /* Receive Memory Block Count */ |
4294 | + opt.type = range_option; |
4295 | + opt.name = "Number of receive memory block"; |
4296 | + opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_RXD_COUNT); |
4297 | + opt.def = ATL2_DEFAULT_RXD_COUNT; |
4298 | + opt.arg.r.min = ATL2_MIN_RXD_COUNT; |
4299 | + opt.arg.r.max = ATL2_MAX_RXD_COUNT; |
4300 | +#ifdef module_param_array |
4301 | + if(num_RxMemBlock > bd) { |
4302 | +#endif |
4303 | + val = RxMemBlock[bd]; |
4304 | + atl2_validate_option(&val, &opt); |
4305 | + adapter->rxd_ring_size = (u32)val; //((u16)val)&~1; // even number |
4306 | +#ifdef module_param_array |
4307 | + } else { |
4308 | + adapter->rxd_ring_size = (u32)opt.def; |
4309 | + } |
4310 | +#endif |
4311 | + // init RXD Flow control value |
4312 | + adapter->hw.fc_rxd_hi = (adapter->rxd_ring_size/8)*7; |
4313 | + adapter->hw.fc_rxd_lo = (ATL2_MIN_RXD_COUNT/8) > (adapter->rxd_ring_size/12) ? |
4314 | + (ATL2_MIN_RXD_COUNT/8) : (adapter->rxd_ring_size/12); |
4315 | + |
4316 | + /* Interrupt Moderate Timer */ |
4317 | + opt.type = range_option; |
4318 | + opt.name = "Interrupt Moderate Timer"; |
4319 | + opt.err = "using default of " __MODULE_STRING(INT_MOD_DEFAULT_CNT); |
4320 | + opt.def = INT_MOD_DEFAULT_CNT; |
4321 | + opt.arg.r.min = INT_MOD_MIN_CNT; |
4322 | + opt.arg.r.max = INT_MOD_MAX_CNT; |
4323 | +#ifdef module_param_array |
4324 | + if(num_IntModTimer > bd) { |
4325 | +#endif |
4326 | + val = IntModTimer[bd]; |
4327 | + atl2_validate_option(&val, &opt); |
4328 | + adapter->imt = (u16) val; |
4329 | +#ifdef module_param_array |
4330 | + } else { |
4331 | + adapter->imt = (u16)(opt.def); |
4332 | + } |
4333 | +#endif |
4334 | + /* Flash Vendor */ |
4335 | + opt.type = range_option; |
4336 | + opt.name = "SPI Flash Vendor"; |
4337 | + opt.err = "using default of " __MODULE_STRING(FLASH_VENDOR_DEFAULT); |
4338 | + opt.def = FLASH_VENDOR_DEFAULT; |
4339 | + opt.arg.r.min = FLASH_VENDOR_MIN; |
4340 | + opt.arg.r.max = FLASH_VENDOR_MAX; |
4341 | +#ifdef module_param_array |
4342 | + if(num_FlashVendor > bd) { |
4343 | +#endif |
4344 | + val = FlashVendor[bd]; |
4345 | + atl2_validate_option(&val, &opt); |
4346 | + adapter->hw.flash_vendor = (u8) val; |
4347 | +#ifdef module_param_array |
4348 | + } else { |
4349 | + adapter->hw.flash_vendor = (u8)(opt.def); |
4350 | + } |
4351 | +#endif |
4352 | + /* MediaType */ |
4353 | + opt.type = range_option; |
4354 | + opt.name = "Speed/Duplex Selection"; |
4355 | + opt.err = "using default of " __MODULE_STRING(MEDIA_TYPE_AUTO_SENSOR); |
4356 | + opt.def = MEDIA_TYPE_AUTO_SENSOR; |
4357 | + opt.arg.r.min = MEDIA_TYPE_AUTO_SENSOR; |
4358 | + opt.arg.r.max = MEDIA_TYPE_10M_HALF; |
4359 | +#ifdef module_param_array |
4360 | + if(num_MediaType > bd) { |
4361 | +#endif |
4362 | + val = MediaType[bd]; |
4363 | + atl2_validate_option(&val, &opt); |
4364 | + adapter->hw.MediaType = (u16) val; |
4365 | +#ifdef module_param_array |
4366 | + } else { |
4367 | + adapter->hw.MediaType = (u16)(opt.def); |
4368 | + } |
4369 | +#endif |
4370 | +} |