Annotation of /trunk/kernel26-magellan-server/patches-2.6.25-r5/0161-2.6.25-atl2-2.0.4.patch
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Revision 677 -
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Wed Sep 10 21:27:27 2008 UTC (16 years, 1 month ago) by niro
File size: 135658 byte(s)
Wed Sep 10 21:27:27 2008 UTC (16 years, 1 month ago) by niro
File size: 135658 byte(s)
2.6.25-magellan-r5: - updated to linux-2.6.25.17
1 | niro | 677 | diff -Nurp a/drivers/net/atl2/atl2_ethtool.c b/drivers/net/atl2/atl2_ethtool.c |
2 | --- a/drivers/net/atl2/atl2_ethtool.c 1969-12-31 19:00:00.000000000 -0500 | ||
3 | +++ b/drivers/net/atl2/atl2_ethtool.c 2007-12-10 12:45:39.000000000 -0500 | ||
4 | @@ -0,0 +1,416 @@ | ||
5 | +/* atl2_ethtool.c -- atl2 ethtool support | ||
6 | + * | ||
7 | + * Copyright(c) 2007 Atheros Corporation. All rights reserved. | ||
8 | + * Copyright(c) 2006 xiong huang <xiong.huang@atheros.com> | ||
9 | + * Copyright(c) 2007 Chris Snook <csnook@redhat.com> | ||
10 | + * | ||
11 | + * Derived from Intel e1000 driver | ||
12 | + * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. | ||
13 | + * | ||
14 | + * This program is free software; you can redistribute it and/or modify it | ||
15 | + * under the terms of the GNU General Public License as published by the Free | ||
16 | + * Software Foundation; either version 2 of the License, or (at your option) | ||
17 | + * any later version. | ||
18 | + * | ||
19 | + * This program is distributed in the hope that it will be useful, but WITHOUT | ||
20 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
21 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
22 | + * more details. | ||
23 | + * | ||
24 | + * You should have received a copy of the GNU General Public License along with | ||
25 | + * this program; if not, write to the Free Software Foundation, Inc., 59 | ||
26 | + * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
27 | + */ | ||
28 | + | ||
29 | +#include <linux/bitops.h> | ||
30 | +#include <linux/ethtool.h> | ||
31 | +#include <linux/mii.h> | ||
32 | +#include <linux/netdevice.h> | ||
33 | +#include <linux/slab.h> | ||
34 | +#include <linux/string.h> | ||
35 | +#include <linux/types.h> | ||
36 | + | ||
37 | +#include "atl2.h" | ||
38 | +#include "atl2_hw.h" | ||
39 | + | ||
40 | +extern char atl2_driver_name[]; | ||
41 | +extern char atl2_driver_version[]; | ||
42 | + | ||
43 | +extern int atl2_up(struct atl2_adapter *adapter); | ||
44 | +extern void atl2_down(struct atl2_adapter *adapter); | ||
45 | +extern void atl2_reinit_locked(struct atl2_adapter *adapter); | ||
46 | +extern s32 atl2_reset_hw(struct atl2_hw *hw); | ||
47 | + | ||
48 | +static int | ||
49 | +atl2_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd) | ||
50 | +{ | ||
51 | + struct atl2_adapter *adapter = netdev_priv(netdev); | ||
52 | + struct atl2_hw *hw = &adapter->hw; | ||
53 | + | ||
54 | + ecmd->supported = (SUPPORTED_10baseT_Half | | ||
55 | + SUPPORTED_10baseT_Full | | ||
56 | + SUPPORTED_100baseT_Half | | ||
57 | + SUPPORTED_100baseT_Full | | ||
58 | + SUPPORTED_Autoneg | | ||
59 | + SUPPORTED_TP); | ||
60 | + ecmd->advertising = ADVERTISED_TP; | ||
61 | + | ||
62 | + ecmd->advertising |= ADVERTISED_Autoneg; | ||
63 | + ecmd->advertising |= hw->autoneg_advertised; | ||
64 | + | ||
65 | + ecmd->port = PORT_TP; | ||
66 | + ecmd->phy_address = 0; | ||
67 | + ecmd->transceiver = XCVR_INTERNAL; | ||
68 | + | ||
69 | + if (adapter->link_speed != SPEED_0) { | ||
70 | + ecmd->speed = adapter->link_speed; | ||
71 | + if (adapter->link_duplex == FULL_DUPLEX) | ||
72 | + ecmd->duplex = DUPLEX_FULL; | ||
73 | + else | ||
74 | + ecmd->duplex = DUPLEX_HALF; | ||
75 | + } else { | ||
76 | + ecmd->speed = -1; | ||
77 | + ecmd->duplex = -1; | ||
78 | + } | ||
79 | + | ||
80 | + ecmd->autoneg = AUTONEG_ENABLE; | ||
81 | + return 0; | ||
82 | +} | ||
83 | + | ||
84 | +static int | ||
85 | +atl2_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd) | ||
86 | +{ | ||
87 | + struct atl2_adapter *adapter = netdev_priv(netdev); | ||
88 | + struct atl2_hw *hw = &adapter->hw; | ||
89 | + | ||
90 | + while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags)) | ||
91 | + msleep(1); | ||
92 | + | ||
93 | + if (ecmd->autoneg == AUTONEG_ENABLE) { | ||
94 | +#define MY_ADV_MASK (ADVERTISE_10_HALF| \ | ||
95 | + ADVERTISE_10_FULL| \ | ||
96 | + ADVERTISE_100_HALF| \ | ||
97 | + ADVERTISE_100_FULL) | ||
98 | + | ||
99 | + if ((ecmd->advertising&MY_ADV_MASK) == MY_ADV_MASK) { | ||
100 | + hw->MediaType = MEDIA_TYPE_AUTO_SENSOR; | ||
101 | + hw->autoneg_advertised = MY_ADV_MASK; | ||
102 | + } else if ((ecmd->advertising&MY_ADV_MASK) == ADVERTISE_100_FULL) { | ||
103 | + hw->MediaType = MEDIA_TYPE_100M_FULL; | ||
104 | + hw->autoneg_advertised = ADVERTISE_100_FULL; | ||
105 | + } else if ((ecmd->advertising&MY_ADV_MASK) == ADVERTISE_100_HALF) { | ||
106 | + hw->MediaType = MEDIA_TYPE_100M_HALF; | ||
107 | + hw->autoneg_advertised = ADVERTISE_100_HALF; | ||
108 | + } else if ((ecmd->advertising&MY_ADV_MASK) == ADVERTISE_10_FULL) { | ||
109 | + hw->MediaType = MEDIA_TYPE_10M_FULL; | ||
110 | + hw->autoneg_advertised = ADVERTISE_10_FULL; | ||
111 | + } else if ((ecmd->advertising&MY_ADV_MASK) == ADVERTISE_10_HALF) { | ||
112 | + hw->MediaType = MEDIA_TYPE_10M_HALF; | ||
113 | + hw->autoneg_advertised = ADVERTISE_10_HALF; | ||
114 | + } else { | ||
115 | + clear_bit(__ATL2_RESETTING, &adapter->flags); | ||
116 | + return -EINVAL; | ||
117 | + } | ||
118 | + ecmd->advertising = hw->autoneg_advertised | | ||
119 | + ADVERTISED_TP | ADVERTISED_Autoneg; | ||
120 | + } else { | ||
121 | + clear_bit(__ATL2_RESETTING, &adapter->flags); | ||
122 | + return -EINVAL; | ||
123 | + } | ||
124 | + | ||
125 | + /* reset the link */ | ||
126 | + if (netif_running(adapter->netdev)) { | ||
127 | + atl2_down(adapter); | ||
128 | + atl2_up(adapter); | ||
129 | + } else | ||
130 | + atl2_reset_hw(&adapter->hw); | ||
131 | + | ||
132 | + clear_bit(__ATL2_RESETTING, &adapter->flags); | ||
133 | + return 0; | ||
134 | +} | ||
135 | + | ||
136 | +static u32 | ||
137 | +atl2_get_tx_csum(struct net_device *netdev) | ||
138 | +{ | ||
139 | + return (netdev->features & NETIF_F_HW_CSUM) != 0; | ||
140 | +} | ||
141 | + | ||
142 | +static u32 | ||
143 | +atl2_get_msglevel(struct net_device *netdev) | ||
144 | +{ | ||
145 | + return 0; | ||
146 | +} | ||
147 | + | ||
148 | +/* | ||
149 | + * It's sane for this to be empty, but we might want to take advantage of this. | ||
150 | + */ | ||
151 | +static void | ||
152 | +atl2_set_msglevel(struct net_device *netdev, u32 data) | ||
153 | +{ | ||
154 | +} | ||
155 | + | ||
156 | +static int | ||
157 | +atl2_get_regs_len(struct net_device *netdev) | ||
158 | +{ | ||
159 | +#define ATL2_REGS_LEN 42 | ||
160 | + return ATL2_REGS_LEN * sizeof(u32); | ||
161 | +} | ||
162 | + | ||
163 | +static void | ||
164 | +atl2_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p) | ||
165 | +{ | ||
166 | + struct atl2_adapter *adapter = netdev_priv(netdev); | ||
167 | + struct atl2_hw *hw = &adapter->hw; | ||
168 | + u32 *regs_buff = p; | ||
169 | + u16 phy_data; | ||
170 | + | ||
171 | + memset(p, 0, ATL2_REGS_LEN * sizeof(u32)); | ||
172 | + | ||
173 | + regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id; | ||
174 | + | ||
175 | + regs_buff[0] = ATL2_READ_REG(hw, REG_VPD_CAP); | ||
176 | + regs_buff[1] = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL); | ||
177 | + regs_buff[2] = ATL2_READ_REG(hw, REG_SPI_FLASH_CONFIG); | ||
178 | + regs_buff[3] = ATL2_READ_REG(hw, REG_TWSI_CTRL); | ||
179 | + regs_buff[4] = ATL2_READ_REG(hw, REG_PCIE_DEV_MISC_CTRL); | ||
180 | + regs_buff[5] = ATL2_READ_REG(hw, REG_MASTER_CTRL); | ||
181 | + regs_buff[6] = ATL2_READ_REG(hw, REG_MANUAL_TIMER_INIT); | ||
182 | + regs_buff[7] = ATL2_READ_REG(hw, REG_IRQ_MODU_TIMER_INIT); | ||
183 | + regs_buff[8] = ATL2_READ_REG(hw, REG_PHY_ENABLE); | ||
184 | + regs_buff[9] = ATL2_READ_REG(hw, REG_CMBDISDMA_TIMER); | ||
185 | + regs_buff[10] = ATL2_READ_REG(hw, REG_IDLE_STATUS); | ||
186 | + regs_buff[11] = ATL2_READ_REG(hw, REG_MDIO_CTRL); | ||
187 | + regs_buff[12] = ATL2_READ_REG(hw, REG_SERDES_LOCK); | ||
188 | + regs_buff[13] = ATL2_READ_REG(hw, REG_MAC_CTRL); | ||
189 | + regs_buff[14] = ATL2_READ_REG(hw, REG_MAC_IPG_IFG); | ||
190 | + regs_buff[15] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR); | ||
191 | + regs_buff[16] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR+4); | ||
192 | + regs_buff[17] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE); | ||
193 | + regs_buff[18] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE+4); | ||
194 | + regs_buff[19] = ATL2_READ_REG(hw, REG_MAC_HALF_DUPLX_CTRL); | ||
195 | + regs_buff[20] = ATL2_READ_REG(hw, REG_MTU); | ||
196 | + regs_buff[21] = ATL2_READ_REG(hw, REG_WOL_CTRL); | ||
197 | + regs_buff[22] = ATL2_READ_REG(hw, REG_SRAM_TXRAM_END); | ||
198 | + regs_buff[23] = ATL2_READ_REG(hw, REG_DESC_BASE_ADDR_HI); | ||
199 | + regs_buff[24] = ATL2_READ_REG(hw, REG_TXD_BASE_ADDR_LO); | ||
200 | + regs_buff[25] = ATL2_READ_REG(hw, REG_TXD_MEM_SIZE); | ||
201 | + regs_buff[26] = ATL2_READ_REG(hw, REG_TXS_BASE_ADDR_LO); | ||
202 | + regs_buff[27] = ATL2_READ_REG(hw, REG_TXS_MEM_SIZE); | ||
203 | + regs_buff[28] = ATL2_READ_REG(hw, REG_RXD_BASE_ADDR_LO); | ||
204 | + regs_buff[29] = ATL2_READ_REG(hw, REG_RXD_BUF_NUM); | ||
205 | + regs_buff[30] = ATL2_READ_REG(hw, REG_DMAR); | ||
206 | + regs_buff[31] = ATL2_READ_REG(hw, REG_TX_CUT_THRESH); | ||
207 | + regs_buff[32] = ATL2_READ_REG(hw, REG_DMAW); | ||
208 | + regs_buff[33] = ATL2_READ_REG(hw, REG_PAUSE_ON_TH); | ||
209 | + regs_buff[34] = ATL2_READ_REG(hw, REG_PAUSE_OFF_TH); | ||
210 | + regs_buff[35] = ATL2_READ_REG(hw, REG_MB_TXD_WR_IDX); | ||
211 | + regs_buff[36] = ATL2_READ_REG(hw, REG_MB_RXD_RD_IDX); | ||
212 | + regs_buff[38] = ATL2_READ_REG(hw, REG_ISR); | ||
213 | + regs_buff[39] = ATL2_READ_REG(hw, REG_IMR); | ||
214 | + | ||
215 | + atl2_read_phy_reg(hw, MII_BMCR, &phy_data); | ||
216 | + regs_buff[40] = (u32)phy_data; | ||
217 | + atl2_read_phy_reg(hw, MII_BMSR, &phy_data); | ||
218 | + regs_buff[41] = (u32)phy_data; | ||
219 | +} | ||
220 | + | ||
221 | +static int | ||
222 | +atl2_get_eeprom_len(struct net_device *netdev) | ||
223 | +{ | ||
224 | + struct atl2_adapter *adapter = netdev_priv(netdev); | ||
225 | + | ||
226 | + if (!atl2_check_eeprom_exist(&adapter->hw)) { | ||
227 | + return 512; | ||
228 | + } else | ||
229 | + return 0; | ||
230 | +} | ||
231 | + | ||
232 | +static int | ||
233 | +atl2_get_eeprom(struct net_device *netdev, struct ethtool_eeprom *eeprom, u8 *bytes) | ||
234 | +{ | ||
235 | + struct atl2_adapter *adapter = netdev_priv(netdev); | ||
236 | + struct atl2_hw *hw = &adapter->hw; | ||
237 | + u32 *eeprom_buff; | ||
238 | + int first_dword, last_dword; | ||
239 | + int ret_val = 0; | ||
240 | + int i; | ||
241 | + | ||
242 | + if (eeprom->len == 0) | ||
243 | + return -EINVAL; | ||
244 | + | ||
245 | + if (atl2_check_eeprom_exist(hw)) { | ||
246 | + return -EINVAL; | ||
247 | + } | ||
248 | + | ||
249 | + eeprom->magic = hw->vendor_id | (hw->device_id << 16); | ||
250 | + | ||
251 | + first_dword = eeprom->offset >> 2; | ||
252 | + last_dword = (eeprom->offset + eeprom->len - 1) >> 2; | ||
253 | + | ||
254 | + eeprom_buff = kmalloc(sizeof(u32) * (last_dword - first_dword + 1), GFP_KERNEL); | ||
255 | + if (!eeprom_buff) | ||
256 | + return -ENOMEM; | ||
257 | + | ||
258 | + for (i=first_dword; i < last_dword; i++) { | ||
259 | + if (!atl2_read_eeprom(hw, i*4, &(eeprom_buff[i-first_dword]))) | ||
260 | + return -EIO; | ||
261 | + } | ||
262 | + | ||
263 | + memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 3), | ||
264 | + eeprom->len); | ||
265 | + kfree(eeprom_buff); | ||
266 | + | ||
267 | + return ret_val; | ||
268 | +} | ||
269 | + | ||
270 | +static int | ||
271 | +atl2_set_eeprom(struct net_device *netdev, struct ethtool_eeprom *eeprom, u8 *bytes) | ||
272 | +{ | ||
273 | + struct atl2_adapter *adapter = netdev_priv(netdev); | ||
274 | + struct atl2_hw *hw = &adapter->hw; | ||
275 | + u32 *eeprom_buff; | ||
276 | + u32 *ptr; | ||
277 | + int max_len, first_dword, last_dword, ret_val = 0; | ||
278 | + int i; | ||
279 | + | ||
280 | + if (eeprom->len == 0) | ||
281 | + return -EOPNOTSUPP; | ||
282 | + | ||
283 | + if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16))) | ||
284 | + return -EFAULT; | ||
285 | + | ||
286 | + max_len = 512; | ||
287 | + | ||
288 | + first_dword = eeprom->offset >> 2; | ||
289 | + last_dword = (eeprom->offset + eeprom->len - 1) >> 2; | ||
290 | + eeprom_buff = kmalloc(max_len, GFP_KERNEL); | ||
291 | + if (!eeprom_buff) | ||
292 | + return -ENOMEM; | ||
293 | + | ||
294 | + ptr = (u32 *)eeprom_buff; | ||
295 | + | ||
296 | + if (eeprom->offset & 3) { | ||
297 | + /* need read/modify/write of first changed EEPROM word */ | ||
298 | + /* only the second byte of the word is being modified */ | ||
299 | + if (!atl2_read_eeprom(hw, first_dword*4, &(eeprom_buff[0]))) | ||
300 | + return -EIO; | ||
301 | + ptr++; | ||
302 | + } | ||
303 | + if (((eeprom->offset + eeprom->len) & 3) ) { | ||
304 | + /* need read/modify/write of last changed EEPROM word */ | ||
305 | + /* only the first byte of the word is being modified */ | ||
306 | + | ||
307 | + if (!atl2_read_eeprom(hw, last_dword*4, &(eeprom_buff[last_dword - first_dword]))) | ||
308 | + return -EIO; | ||
309 | + } | ||
310 | + | ||
311 | + /* Device's eeprom is always little-endian, word addressable */ | ||
312 | + memcpy(ptr, bytes, eeprom->len); | ||
313 | + | ||
314 | + for (i = 0; i < last_dword - first_dword + 1; i++) { | ||
315 | + if (!atl2_write_eeprom(hw, ((first_dword+i)*4), eeprom_buff[i])) | ||
316 | + return -EIO; | ||
317 | + } | ||
318 | + | ||
319 | + kfree(eeprom_buff); | ||
320 | + return ret_val; | ||
321 | +} | ||
322 | + | ||
323 | +static void | ||
324 | +atl2_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *drvinfo) | ||
325 | +{ | ||
326 | + struct atl2_adapter *adapter = netdev_priv(netdev); | ||
327 | + | ||
328 | + strncpy(drvinfo->driver, atl2_driver_name, 32); | ||
329 | + strncpy(drvinfo->version, atl2_driver_version, 32); | ||
330 | + strncpy(drvinfo->fw_version, "L2", 32); | ||
331 | + strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32); | ||
332 | + drvinfo->n_stats = 0; | ||
333 | + drvinfo->testinfo_len = 0; | ||
334 | + drvinfo->regdump_len = atl2_get_regs_len(netdev); | ||
335 | + drvinfo->eedump_len = atl2_get_eeprom_len(netdev); | ||
336 | +} | ||
337 | + | ||
338 | +static void | ||
339 | +atl2_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) | ||
340 | +{ | ||
341 | + struct atl2_adapter *adapter = netdev_priv(netdev); | ||
342 | + | ||
343 | + wol->supported = WAKE_MAGIC; | ||
344 | + wol->wolopts = 0; | ||
345 | + | ||
346 | + if (adapter->wol & ATL2_WUFC_EX) | ||
347 | + wol->wolopts |= WAKE_UCAST; | ||
348 | + if (adapter->wol & ATL2_WUFC_MC) | ||
349 | + wol->wolopts |= WAKE_MCAST; | ||
350 | + if (adapter->wol & ATL2_WUFC_BC) | ||
351 | + wol->wolopts |= WAKE_BCAST; | ||
352 | + if (adapter->wol & ATL2_WUFC_MAG) | ||
353 | + wol->wolopts |= WAKE_MAGIC; | ||
354 | + if (adapter->wol & ATL2_WUFC_LNKC) | ||
355 | + wol->wolopts |= WAKE_PHY; | ||
356 | +} | ||
357 | + | ||
358 | +static int | ||
359 | +atl2_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) | ||
360 | +{ | ||
361 | + struct atl2_adapter *adapter = netdev_priv(netdev); | ||
362 | + | ||
363 | + if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE)) | ||
364 | + return -EOPNOTSUPP; | ||
365 | + | ||
366 | + if (wol->wolopts & (WAKE_MCAST|WAKE_BCAST|WAKE_MCAST)) | ||
367 | + return -EOPNOTSUPP; | ||
368 | + | ||
369 | + /* these settings will always override what we currently have */ | ||
370 | + adapter->wol = 0; | ||
371 | + | ||
372 | + if (wol->wolopts & WAKE_MAGIC) | ||
373 | + adapter->wol |= ATL2_WUFC_MAG; | ||
374 | + if (wol->wolopts & WAKE_PHY) | ||
375 | + adapter->wol |= ATL2_WUFC_LNKC; | ||
376 | + | ||
377 | + return 0; | ||
378 | +} | ||
379 | + | ||
380 | +static int | ||
381 | +atl2_nway_reset(struct net_device *netdev) | ||
382 | +{ | ||
383 | + struct atl2_adapter *adapter = netdev_priv(netdev); | ||
384 | + if (netif_running(netdev)) | ||
385 | + atl2_reinit_locked(adapter); | ||
386 | + return 0; | ||
387 | +} | ||
388 | + | ||
389 | +static struct ethtool_ops atl2_ethtool_ops = { | ||
390 | + .get_settings = atl2_get_settings, | ||
391 | + .set_settings = atl2_set_settings, | ||
392 | + .get_drvinfo = atl2_get_drvinfo, | ||
393 | + .get_regs_len = atl2_get_regs_len, | ||
394 | + .get_regs = atl2_get_regs, | ||
395 | + .get_wol = atl2_get_wol, | ||
396 | + .set_wol = atl2_set_wol, | ||
397 | + .get_msglevel = atl2_get_msglevel, | ||
398 | + .set_msglevel = atl2_set_msglevel, | ||
399 | + .nway_reset = atl2_nway_reset, | ||
400 | + .get_link = ethtool_op_get_link, | ||
401 | + .get_eeprom_len = atl2_get_eeprom_len, | ||
402 | + .get_eeprom = atl2_get_eeprom, | ||
403 | + .set_eeprom = atl2_set_eeprom, | ||
404 | + .get_tx_csum = atl2_get_tx_csum, | ||
405 | + .get_sg = ethtool_op_get_sg, | ||
406 | + .set_sg = ethtool_op_set_sg, | ||
407 | +#ifdef NETIF_F_TSO | ||
408 | + .get_tso = ethtool_op_get_tso, | ||
409 | +#endif | ||
410 | +#if 0 //FIXME: not implemented? | ||
411 | +//#ifdef ETHTOOL_GPERMADDR | ||
412 | + .get_perm_addr = ethtool_op_get_perm_addr, | ||
413 | +#endif | ||
414 | +}; | ||
415 | + | ||
416 | +void | ||
417 | +atl2_set_ethtool_ops(struct net_device *netdev) | ||
418 | +{ | ||
419 | + SET_ETHTOOL_OPS(netdev, &atl2_ethtool_ops); | ||
420 | +} | ||
421 | diff -Nurp a/drivers/net/atl2/atl2.h b/drivers/net/atl2/atl2.h | ||
422 | --- a/drivers/net/atl2/atl2.h 1969-12-31 19:00:00.000000000 -0500 | ||
423 | +++ b/drivers/net/atl2/atl2.h 2007-12-10 10:54:33.000000000 -0500 | ||
424 | @@ -0,0 +1,120 @@ | ||
425 | +/* atl2.h -- atl2 driver definitions | ||
426 | + * | ||
427 | + * Copyright(c) 2007 Atheros Corporation. All rights reserved. | ||
428 | + * Copyright(c) 2006 xiong huang <xiong.huang@atheros.com> | ||
429 | + * Copyright(c) 2007 Chris Snook <csnook@redhat.com> | ||
430 | + * | ||
431 | + * Derived from Intel e1000 driver | ||
432 | + * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. | ||
433 | + * | ||
434 | + * This program is free software; you can redistribute it and/or modify it | ||
435 | + * under the terms of the GNU General Public License as published by the Free | ||
436 | + * Software Foundation; either version 2 of the License, or (at your option) | ||
437 | + * any later version. | ||
438 | + * | ||
439 | + * This program is distributed in the hope that it will be useful, but WITHOUT | ||
440 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
441 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
442 | + * more details. | ||
443 | + * | ||
444 | + * You should have received a copy of the GNU General Public License along with | ||
445 | + * this program; if not, write to the Free Software Foundation, Inc., 59 | ||
446 | + * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
447 | + */ | ||
448 | + | ||
449 | +#ifndef _ATL2_H_ | ||
450 | +#define _ATL2_H_ | ||
451 | + | ||
452 | +#include <asm/atomic.h> | ||
453 | +#include <linux/netdevice.h> | ||
454 | + | ||
455 | +#include "atl2_hw.h" | ||
456 | + | ||
457 | +struct atl2_ring_header { | ||
458 | + /* pointer to the descriptor ring memory */ | ||
459 | + void *desc; | ||
460 | + /* physical adress of the descriptor ring */ | ||
461 | + dma_addr_t dma; | ||
462 | + /* length of descriptor ring in bytes */ | ||
463 | + unsigned int size; | ||
464 | +}; | ||
465 | + | ||
466 | +/* board specific private data structure */ | ||
467 | +struct atl2_adapter { | ||
468 | + /* OS defined structs */ | ||
469 | + struct net_device *netdev; | ||
470 | + struct pci_dev *pdev; | ||
471 | + struct net_device_stats net_stats; | ||
472 | +#ifdef NETIF_F_HW_VLAN_TX | ||
473 | + struct vlan_group *vlgrp; | ||
474 | +#endif | ||
475 | + u32 wol; | ||
476 | + u16 link_speed; | ||
477 | + u16 link_duplex; | ||
478 | + | ||
479 | + spinlock_t stats_lock; | ||
480 | + spinlock_t tx_lock; | ||
481 | + | ||
482 | + struct work_struct reset_task; | ||
483 | + struct work_struct link_chg_task; | ||
484 | + struct timer_list watchdog_timer; | ||
485 | + struct timer_list phy_config_timer; | ||
486 | + | ||
487 | + unsigned long cfg_phy; | ||
488 | + bool mac_disabled; | ||
489 | + | ||
490 | + /* All Descriptor memory */ | ||
491 | + dma_addr_t ring_dma; | ||
492 | + void *ring_vir_addr; | ||
493 | + int ring_size; | ||
494 | + | ||
495 | + tx_pkt_header_t *txd_ring; | ||
496 | + dma_addr_t txd_dma; | ||
497 | + | ||
498 | + tx_pkt_status_t *txs_ring; | ||
499 | + dma_addr_t txs_dma; | ||
500 | + | ||
501 | + rx_desc_t *rxd_ring; | ||
502 | + dma_addr_t rxd_dma; | ||
503 | + | ||
504 | + u32 txd_ring_size; // bytes per unit | ||
505 | + u32 txs_ring_size; // dwords per unit | ||
506 | + u32 rxd_ring_size; // 1536bytes per unit | ||
507 | + | ||
508 | + // read /write ptr: | ||
509 | + // host | ||
510 | + u32 txd_write_ptr; | ||
511 | + u32 txs_next_clear; | ||
512 | + u32 rxd_read_ptr; | ||
513 | + | ||
514 | + // nic | ||
515 | + atomic_t txd_read_ptr; | ||
516 | + atomic_t txs_write_ptr; | ||
517 | + u32 rxd_write_ptr; | ||
518 | + | ||
519 | + /* Interrupt Moderator timer ( 2us resolution) */ | ||
520 | + u16 imt; | ||
521 | + /* Interrupt Clear timer (2us resolution) */ | ||
522 | + u16 ict; | ||
523 | + | ||
524 | + unsigned long flags; | ||
525 | + /* structs defined in atl2_hw.h */ | ||
526 | + u32 bd_number; // board number; | ||
527 | + bool pci_using_64; | ||
528 | + bool have_msi; | ||
529 | + struct atl2_hw hw; | ||
530 | + | ||
531 | + u32 usr_cmd; | ||
532 | +// u32 regs_buff[ATL2_REGS_LEN]; | ||
533 | + u32 pci_state[16]; | ||
534 | + | ||
535 | + u32 *config_space; | ||
536 | +}; | ||
537 | + | ||
538 | +enum atl2_state_t { | ||
539 | + __ATL2_TESTING, | ||
540 | + __ATL2_RESETTING, | ||
541 | + __ATL2_DOWN | ||
542 | +}; | ||
543 | + | ||
544 | +#endif /* _ATL2_H_ */ | ||
545 | diff -Nurp a/drivers/net/atl2/atl2_hw.c b/drivers/net/atl2/atl2_hw.c | ||
546 | --- a/drivers/net/atl2/atl2_hw.c 1969-12-31 19:00:00.000000000 -0500 | ||
547 | +++ b/drivers/net/atl2/atl2_hw.c 2007-12-10 11:21:08.000000000 -0500 | ||
548 | @@ -0,0 +1,760 @@ | ||
549 | +/* atl2_hw.c -- atl2 hardware control functions | ||
550 | + * | ||
551 | + * Copyright(c) 2007 Atheros Corporation. All rights reserved. | ||
552 | + * Copyright(c) 2006 xiong huang <xiong.huang@atheros.com> | ||
553 | + * Copyright(c) 2007 Chris Snook <csnook@redhat.com> | ||
554 | + * | ||
555 | + * Derived from Intel e1000 driver | ||
556 | + * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. | ||
557 | + * | ||
558 | + * This program is free software; you can redistribute it and/or modify it | ||
559 | + * under the terms of the GNU General Public License as published by the Free | ||
560 | + * Software Foundation; either version 2 of the License, or (at your option) | ||
561 | + * any later version. | ||
562 | + * | ||
563 | + * This program is distributed in the hope that it will be useful, but WITHOUT | ||
564 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
565 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
566 | + * more details. | ||
567 | + * | ||
568 | + * You should have received a copy of the GNU General Public License along with | ||
569 | + * this program; if not, write to the Free Software Foundation, Inc., 59 | ||
570 | + * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
571 | + */ | ||
572 | + | ||
573 | +#include <asm/processor.h> | ||
574 | +#include <linux/crc32.h> | ||
575 | +#include <linux/etherdevice.h> | ||
576 | +#include <linux/mii.h> | ||
577 | +#include <linux/string.h> | ||
578 | + | ||
579 | +#include "atl2.h" | ||
580 | +#include "atl2_hw.h" | ||
581 | + | ||
582 | +#define LBYTESWAP( a ) ( ( ( (a) & 0x00ff00ff ) << 8 ) | ( ( (a) & 0xff00ff00 ) >> 8 ) ) | ||
583 | +#define LONGSWAP( a ) ( ( LBYTESWAP( a ) << 16 ) | ( LBYTESWAP( a ) >> 16 ) ) | ||
584 | +#define SHORTSWAP( a ) ( ( (a) << 8 ) | ( (a) >> 8 ) ) | ||
585 | + | ||
586 | +/* | ||
587 | + * Reset the transmit and receive units; mask and clear all interrupts. | ||
588 | + * | ||
589 | + * hw - Struct containing variables accessed by shared code | ||
590 | + * return : ATL2_SUCCESS or idle status (if error) | ||
591 | + */ | ||
592 | +s32 | ||
593 | +atl2_reset_hw(struct atl2_hw *hw) | ||
594 | +{ | ||
595 | + u32 icr; | ||
596 | + u16 pci_cfg_cmd_word; | ||
597 | + int i; | ||
598 | + | ||
599 | + /* Workaround for PCI problem when BIOS sets MMRBC incorrectly. */ | ||
600 | + atl2_read_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word); | ||
601 | + if ((pci_cfg_cmd_word & | ||
602 | + (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) != | ||
603 | + (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) { | ||
604 | + pci_cfg_cmd_word |= | ||
605 | + (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER); | ||
606 | + atl2_write_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word); | ||
607 | + } | ||
608 | + | ||
609 | + /* Clear Interrupt mask to stop board from generating | ||
610 | + * interrupts & Clear any pending interrupt events | ||
611 | + */ | ||
612 | +// ATL2_WRITE_REG(hw, REG_IMR, 0); | ||
613 | +// ATL2_WRITE_REG(hw, REG_ISR, 0xffffffff); | ||
614 | + | ||
615 | + /* Issue Soft Reset to the MAC. This will reset the chip's | ||
616 | + * transmit, receive, DMA. It will not effect | ||
617 | + * the current PCI configuration. The global reset bit is self- | ||
618 | + * clearing, and should clear within a microsecond. | ||
619 | + */ | ||
620 | + ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_SOFT_RST); | ||
621 | + wmb(); | ||
622 | + msec_delay(1); // delay about 1ms | ||
623 | + | ||
624 | + /* Wait at least 10ms for All module to be Idle */ | ||
625 | + for (i=0; i < 10; i++) { | ||
626 | + icr = ATL2_READ_REG(hw, REG_IDLE_STATUS); | ||
627 | + if (!icr) | ||
628 | + break; | ||
629 | + msec_delay(1); // delay 1 ms | ||
630 | + cpu_relax(); | ||
631 | + } | ||
632 | + | ||
633 | + if (icr) | ||
634 | + return icr; | ||
635 | + | ||
636 | + return ATL2_SUCCESS; | ||
637 | +} | ||
638 | + | ||
639 | +#define CUSTOM_SPI_CS_SETUP 2 | ||
640 | +#define CUSTOM_SPI_CLK_HI 2 | ||
641 | +#define CUSTOM_SPI_CLK_LO 2 | ||
642 | +#define CUSTOM_SPI_CS_HOLD 2 | ||
643 | +#define CUSTOM_SPI_CS_HI 3 | ||
644 | + | ||
645 | +static struct atl2_spi_flash_dev flash_table[] = | ||
646 | +{ | ||
647 | +/* manu_name WRSR READ PROGRAM WREN WRDI RDSR RDID SECTOR_ERASE CHIP_ERASE */ | ||
648 | + {"Atmel", 0x0, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62 }, | ||
649 | + {"SST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60 }, | ||
650 | + {"ST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xAB, 0xD8, 0xC7 }, | ||
651 | +}; | ||
652 | + | ||
653 | +static bool | ||
654 | +atl2_spi_read(struct atl2_hw* hw, u32 addr, u32* buf) | ||
655 | +{ | ||
656 | + int i; | ||
657 | + u32 value; | ||
658 | + | ||
659 | + ATL2_WRITE_REG(hw, REG_SPI_DATA, 0); | ||
660 | + ATL2_WRITE_REG(hw, REG_SPI_ADDR, addr); | ||
661 | + | ||
662 | + value = SPI_FLASH_CTRL_WAIT_READY | | ||
663 | + (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) << SPI_FLASH_CTRL_CS_SETUP_SHIFT | | ||
664 | + (CUSTOM_SPI_CLK_HI & SPI_FLASH_CTRL_CLK_HI_MASK) << SPI_FLASH_CTRL_CLK_HI_SHIFT | | ||
665 | + (CUSTOM_SPI_CLK_LO & SPI_FLASH_CTRL_CLK_LO_MASK) << SPI_FLASH_CTRL_CLK_LO_SHIFT | | ||
666 | + (CUSTOM_SPI_CS_HOLD & SPI_FLASH_CTRL_CS_HOLD_MASK) << SPI_FLASH_CTRL_CS_HOLD_SHIFT | | ||
667 | + (CUSTOM_SPI_CS_HI & SPI_FLASH_CTRL_CS_HI_MASK) << SPI_FLASH_CTRL_CS_HI_SHIFT | | ||
668 | + (0x1 & SPI_FLASH_CTRL_INS_MASK) << SPI_FLASH_CTRL_INS_SHIFT; | ||
669 | + | ||
670 | + ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value); | ||
671 | + | ||
672 | + value |= SPI_FLASH_CTRL_START; | ||
673 | + | ||
674 | + ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value); | ||
675 | + | ||
676 | + for (i = 0; i < 10; i++) | ||
677 | + { | ||
678 | + msec_delay(1); // 1ms | ||
679 | + value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL); | ||
680 | + if (!(value & SPI_FLASH_CTRL_START)) | ||
681 | + break; | ||
682 | + } | ||
683 | + | ||
684 | + if (value & SPI_FLASH_CTRL_START) | ||
685 | + return false; | ||
686 | + | ||
687 | + *buf = ATL2_READ_REG(hw, REG_SPI_DATA); | ||
688 | + | ||
689 | + return true; | ||
690 | +} | ||
691 | + | ||
692 | +/* | ||
693 | + * get_permanent_address | ||
694 | + * return 0 if get valid mac address, | ||
695 | + */ | ||
696 | +static int | ||
697 | +get_permanent_address(struct atl2_hw *hw) | ||
698 | +{ | ||
699 | + u32 Addr[2]; | ||
700 | + u32 i, Control; | ||
701 | + u16 Register; | ||
702 | + u8 EthAddr[NODE_ADDRESS_SIZE]; | ||
703 | + bool KeyValid; | ||
704 | + | ||
705 | + if (is_valid_ether_addr(hw->perm_mac_addr)) | ||
706 | + return 0; | ||
707 | + | ||
708 | + Addr[0] = 0; | ||
709 | + Addr[1] = 0; | ||
710 | + | ||
711 | + if (!atl2_check_eeprom_exist(hw)) { /* eeprom exists */ | ||
712 | + Register = 0; | ||
713 | + KeyValid = false; | ||
714 | + | ||
715 | + /* Read out all EEPROM content */ | ||
716 | + i = 0; | ||
717 | + while (1) { | ||
718 | + if (atl2_read_eeprom(hw, i + 0x100, &Control)) { | ||
719 | + if (KeyValid) { | ||
720 | + if (Register == REG_MAC_STA_ADDR) | ||
721 | + Addr[0] = Control; | ||
722 | + else if (Register == (REG_MAC_STA_ADDR + 4)) | ||
723 | + Addr[1] = Control; | ||
724 | + KeyValid = false; | ||
725 | + } else if ((Control & 0xff) == 0x5A) { | ||
726 | + KeyValid = true; | ||
727 | + Register = (u16) (Control >> 16); | ||
728 | + } else { | ||
729 | + break; /* assume data end while encount an invalid KEYWORD */ | ||
730 | + } | ||
731 | + } else { | ||
732 | + break; /* read error */ | ||
733 | + } | ||
734 | + i += 4; | ||
735 | + } | ||
736 | + | ||
737 | + *(u32*) &EthAddr[2] = LONGSWAP(Addr[0]); | ||
738 | + *(u16*) &EthAddr[0] = SHORTSWAP(*(u16*)&Addr[1]); | ||
739 | + | ||
740 | + if (is_valid_ether_addr(EthAddr)) { | ||
741 | + memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE); | ||
742 | + return 0; | ||
743 | + } | ||
744 | + return 1; | ||
745 | + } | ||
746 | + | ||
747 | + // see if SPI FLAHS exist ? | ||
748 | + Addr[0] = 0; | ||
749 | + Addr[1] = 0; | ||
750 | + Register = 0; | ||
751 | + KeyValid = false; | ||
752 | + i = 0; | ||
753 | + while (1) { | ||
754 | + if (atl2_spi_read(hw, i + 0x1f000, &Control)) { | ||
755 | + if (KeyValid) { | ||
756 | + if (Register == REG_MAC_STA_ADDR) | ||
757 | + Addr[0] = Control; | ||
758 | + else if (Register == (REG_MAC_STA_ADDR + 4)) | ||
759 | + Addr[1] = Control; | ||
760 | + KeyValid = false; | ||
761 | + } else if ((Control & 0xff) == 0x5A) { | ||
762 | + KeyValid = true; | ||
763 | + Register = (u16) (Control >> 16); | ||
764 | + } else { | ||
765 | + break; /* data end */ | ||
766 | + } | ||
767 | + } else { | ||
768 | + break; /* read error */ | ||
769 | + } | ||
770 | + i += 4; | ||
771 | + } | ||
772 | + | ||
773 | + *(u32*) &EthAddr[2] = LONGSWAP(Addr[0]); | ||
774 | + *(u16*) &EthAddr[0] = SHORTSWAP(*(u16*)&Addr[1]); | ||
775 | + if (is_valid_ether_addr(EthAddr)) { | ||
776 | + memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE); | ||
777 | + return 0; | ||
778 | + } | ||
779 | + /* maybe MAC-address is from BIOS */ | ||
780 | + Addr[0] = ATL2_READ_REG(hw,REG_MAC_STA_ADDR); | ||
781 | + Addr[1] = ATL2_READ_REG(hw,REG_MAC_STA_ADDR+4); | ||
782 | + *(u32*) &EthAddr[2] = LONGSWAP(Addr[0]); | ||
783 | + *(u16*) &EthAddr[0] = SHORTSWAP(*(u16*)&Addr[1]); | ||
784 | + | ||
785 | + if (is_valid_ether_addr(EthAddr)) { | ||
786 | + memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE); | ||
787 | + return 0; | ||
788 | + } | ||
789 | + | ||
790 | + return 1; | ||
791 | +} | ||
792 | + | ||
793 | +/* | ||
794 | + * Reads the adapter's MAC address from the EEPROM | ||
795 | + * | ||
796 | + * hw - Struct containing variables accessed by shared code | ||
797 | + */ | ||
798 | +s32 | ||
799 | +atl2_read_mac_addr(struct atl2_hw *hw) | ||
800 | +{ | ||
801 | + u16 i; | ||
802 | + | ||
803 | + if (get_permanent_address(hw)) { | ||
804 | + // for test | ||
805 | + hw->perm_mac_addr[0] = 0x00; | ||
806 | + hw->perm_mac_addr[1] = 0x13; | ||
807 | + hw->perm_mac_addr[2] = 0x74; | ||
808 | + hw->perm_mac_addr[3] = 0x00; | ||
809 | + hw->perm_mac_addr[4] = 0x5c; | ||
810 | + hw->perm_mac_addr[5] = 0x38; | ||
811 | + } | ||
812 | + | ||
813 | + for(i = 0; i < NODE_ADDRESS_SIZE; i++) | ||
814 | + hw->mac_addr[i] = hw->perm_mac_addr[i]; | ||
815 | + | ||
816 | + return ATL2_SUCCESS; | ||
817 | +} | ||
818 | + | ||
819 | +/* | ||
820 | + * Hashes an address to determine its location in the multicast table | ||
821 | + * | ||
822 | + * hw - Struct containing variables accessed by shared code | ||
823 | + * mc_addr - the multicast address to hash | ||
824 | + * | ||
825 | + * atl2_hash_mc_addr | ||
826 | + * purpose | ||
827 | + * set hash value for a multicast address | ||
828 | + * hash calcu processing : | ||
829 | + * 1. calcu 32bit CRC for multicast address | ||
830 | + * 2. reverse crc with MSB to LSB | ||
831 | + */ | ||
832 | +u32 | ||
833 | +atl2_hash_mc_addr(struct atl2_hw *hw, u8 *mc_addr) | ||
834 | +{ | ||
835 | + u32 crc32, value=0; | ||
836 | + int i; | ||
837 | + | ||
838 | + crc32 = ether_crc_le(6, mc_addr); | ||
839 | + | ||
840 | + for (i=0; i<32; i++) | ||
841 | + value |= (((crc32>>i)&1)<<(31-i)); | ||
842 | + | ||
843 | + return value; | ||
844 | +} | ||
845 | + | ||
846 | +/* | ||
847 | + * Sets the bit in the multicast table corresponding to the hash value. | ||
848 | + * | ||
849 | + * hw - Struct containing variables accessed by shared code | ||
850 | + * hash_value - Multicast address hash value | ||
851 | + */ | ||
852 | +void | ||
853 | +atl2_hash_set(struct atl2_hw *hw, u32 hash_value) | ||
854 | +{ | ||
855 | + u32 hash_bit, hash_reg; | ||
856 | + u32 mta; | ||
857 | + | ||
858 | + /* The HASH Table is a register array of 2 32-bit registers. | ||
859 | + * It is treated like an array of 64 bits. We want to set | ||
860 | + * bit BitArray[hash_value]. So we figure out what register | ||
861 | + * the bit is in, read it, OR in the new bit, then write | ||
862 | + * back the new value. The register is determined by the | ||
863 | + * upper 7 bits of the hash value and the bit within that | ||
864 | + * register are determined by the lower 5 bits of the value. | ||
865 | + */ | ||
866 | + hash_reg = (hash_value >> 31) & 0x1; | ||
867 | + hash_bit = (hash_value >> 26) & 0x1F; | ||
868 | + | ||
869 | + mta = ATL2_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg); | ||
870 | + | ||
871 | + mta |= (1 << hash_bit); | ||
872 | + | ||
873 | + ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta); | ||
874 | +} | ||
875 | + | ||
876 | +/* | ||
877 | + * atl2_init_pcie - init PCIE module | ||
878 | + */ | ||
879 | +static void | ||
880 | +atl2_init_pcie(struct atl2_hw *hw) | ||
881 | +{ | ||
882 | + u32 value; | ||
883 | + value = LTSSM_TEST_MODE_DEF; | ||
884 | + ATL2_WRITE_REG(hw, REG_LTSSM_TEST_MODE, value); | ||
885 | + | ||
886 | + value = PCIE_DLL_TX_CTRL1_DEF; | ||
887 | + ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, value); | ||
888 | +} | ||
889 | + | ||
890 | +void | ||
891 | +atl2_init_flash_opcode(struct atl2_hw *hw) | ||
892 | +{ | ||
893 | + if (hw->flash_vendor >= ARRAY_SIZE(flash_table)) { | ||
894 | + hw->flash_vendor = 0; // ATMEL | ||
895 | + } | ||
896 | + // Init OP table | ||
897 | + ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_PROGRAM, flash_table[hw->flash_vendor].cmdPROGRAM); | ||
898 | + ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_SC_ERASE, flash_table[hw->flash_vendor].cmdSECTOR_ERASE); | ||
899 | + ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_CHIP_ERASE, flash_table[hw->flash_vendor].cmdCHIP_ERASE); | ||
900 | + ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDID, flash_table[hw->flash_vendor].cmdRDID); | ||
901 | + ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WREN, flash_table[hw->flash_vendor].cmdWREN); | ||
902 | + ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDSR, flash_table[hw->flash_vendor].cmdRDSR); | ||
903 | + ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WRSR, flash_table[hw->flash_vendor].cmdWRSR); | ||
904 | + ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_READ, flash_table[hw->flash_vendor].cmdREAD); | ||
905 | +} | ||
906 | + | ||
907 | +/******************************************************************** | ||
908 | +* Performs basic configuration of the adapter. | ||
909 | +* | ||
910 | +* hw - Struct containing variables accessed by shared code | ||
911 | +* Assumes that the controller has previously been reset and is in a | ||
912 | +* post-reset uninitialized state. Initializes multicast table, | ||
913 | +* and Calls routines to setup link | ||
914 | +* Leaves the transmit and receive units disabled and uninitialized. | ||
915 | +********************************************************************/ | ||
916 | +s32 | ||
917 | +atl2_init_hw(struct atl2_hw *hw) | ||
918 | +{ | ||
919 | + u32 ret_val = 0; | ||
920 | + | ||
921 | + atl2_init_pcie(hw); | ||
922 | + | ||
923 | + /* Zero out the Multicast HASH table */ | ||
924 | + /* clear the old settings from the multicast hash table */ | ||
925 | + ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0); | ||
926 | + ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0); | ||
927 | + | ||
928 | + atl2_init_flash_opcode(hw); | ||
929 | + | ||
930 | + ret_val = atl2_phy_init(hw); | ||
931 | + | ||
932 | + return ret_val; | ||
933 | +} | ||
934 | + | ||
935 | +/* | ||
936 | + * Detects the current speed and duplex settings of the hardware. | ||
937 | + * | ||
938 | + * hw - Struct containing variables accessed by shared code | ||
939 | + * speed - Speed of the connection | ||
940 | + * duplex - Duplex setting of the connection | ||
941 | + */ | ||
942 | +s32 | ||
943 | +atl2_get_speed_and_duplex(struct atl2_hw *hw, u16 *speed, u16 *duplex) | ||
944 | +{ | ||
945 | + s32 ret_val; | ||
946 | + u16 phy_data; | ||
947 | + | ||
948 | + // ; --- Read PHY Specific Status Register (17) | ||
949 | + ret_val = atl2_read_phy_reg(hw, MII_AT001_PSSR, &phy_data); | ||
950 | + if (ret_val) | ||
951 | + return ret_val; | ||
952 | + | ||
953 | + if (!(phy_data & MII_AT001_PSSR_SPD_DPLX_RESOLVED)) | ||
954 | + return ATL2_ERR_PHY_RES; | ||
955 | + | ||
956 | + switch(phy_data & MII_AT001_PSSR_SPEED) { | ||
957 | + case MII_AT001_PSSR_100MBS: | ||
958 | + *speed = SPEED_100; | ||
959 | + break; | ||
960 | + case MII_AT001_PSSR_10MBS: | ||
961 | + *speed = SPEED_10; | ||
962 | + break; | ||
963 | + default: | ||
964 | + return ATL2_ERR_PHY_SPEED; | ||
965 | + break; | ||
966 | + } | ||
967 | + | ||
968 | + if (phy_data & MII_AT001_PSSR_DPLX) { | ||
969 | + *duplex = FULL_DUPLEX; | ||
970 | + } else { | ||
971 | + *duplex = HALF_DUPLEX; | ||
972 | + } | ||
973 | + | ||
974 | + return ATL2_SUCCESS; | ||
975 | +} | ||
976 | + | ||
977 | +/* | ||
978 | + * Reads the value from a PHY register | ||
979 | + * hw - Struct containing variables accessed by shared code | ||
980 | + * reg_addr - address of the PHY register to read | ||
981 | + */ | ||
982 | +s32 | ||
983 | +atl2_read_phy_reg(struct atl2_hw *hw, u16 reg_addr, u16 *phy_data) | ||
984 | +{ | ||
985 | + u32 val; | ||
986 | + int i; | ||
987 | + | ||
988 | + val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT | | ||
989 | + MDIO_START | | ||
990 | + MDIO_SUP_PREAMBLE | | ||
991 | + MDIO_RW | | ||
992 | + MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT; | ||
993 | + ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val); | ||
994 | + | ||
995 | + wmb(); | ||
996 | + | ||
997 | + for (i=0; i<MDIO_WAIT_TIMES; i++) { | ||
998 | + usec_delay(2); | ||
999 | + val = ATL2_READ_REG(hw, REG_MDIO_CTRL); | ||
1000 | + if (!(val & (MDIO_START | MDIO_BUSY))) { | ||
1001 | + break; | ||
1002 | + } | ||
1003 | + wmb(); | ||
1004 | + } | ||
1005 | + if (!(val & (MDIO_START | MDIO_BUSY))) { | ||
1006 | + *phy_data = (u16)val; | ||
1007 | + return ATL2_SUCCESS; | ||
1008 | + } | ||
1009 | + | ||
1010 | + return ATL2_ERR_PHY; | ||
1011 | +} | ||
1012 | + | ||
1013 | +/* | ||
1014 | + * Writes a value to a PHY register | ||
1015 | + * hw - Struct containing variables accessed by shared code | ||
1016 | + * reg_addr - address of the PHY register to write | ||
1017 | + * data - data to write to the PHY | ||
1018 | + */ | ||
1019 | +s32 | ||
1020 | +atl2_write_phy_reg(struct atl2_hw *hw, u32 reg_addr, u16 phy_data) | ||
1021 | +{ | ||
1022 | + int i; | ||
1023 | + u32 val; | ||
1024 | + | ||
1025 | + val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT | | ||
1026 | + (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT | | ||
1027 | + MDIO_SUP_PREAMBLE | | ||
1028 | + MDIO_START | | ||
1029 | + MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT; | ||
1030 | + ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val); | ||
1031 | + | ||
1032 | + wmb(); | ||
1033 | + | ||
1034 | + for (i=0; i<MDIO_WAIT_TIMES; i++) { | ||
1035 | + usec_delay(2); | ||
1036 | + val = ATL2_READ_REG(hw, REG_MDIO_CTRL); | ||
1037 | + if (!(val & (MDIO_START | MDIO_BUSY))) { | ||
1038 | + break; | ||
1039 | + } | ||
1040 | + wmb(); | ||
1041 | + } | ||
1042 | + | ||
1043 | + if (!(val & (MDIO_START | MDIO_BUSY))) | ||
1044 | + return ATL2_SUCCESS; | ||
1045 | + | ||
1046 | + return ATL2_ERR_PHY; | ||
1047 | +} | ||
1048 | + | ||
1049 | +/* | ||
1050 | + * Configures PHY autoneg and flow control advertisement settings | ||
1051 | + * | ||
1052 | + * hw - Struct containing variables accessed by shared code | ||
1053 | + */ | ||
1054 | +static s32 | ||
1055 | +atl2_phy_setup_autoneg_adv(struct atl2_hw *hw) | ||
1056 | +{ | ||
1057 | + s32 ret_val; | ||
1058 | + s16 mii_autoneg_adv_reg; | ||
1059 | + | ||
1060 | + /* Read the MII Auto-Neg Advertisement Register (Address 4). */ | ||
1061 | + mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK; | ||
1062 | + | ||
1063 | + /* Need to parse autoneg_advertised and set up | ||
1064 | + * the appropriate PHY registers. First we will parse for | ||
1065 | + * autoneg_advertised software override. Since we can advertise | ||
1066 | + * a plethora of combinations, we need to check each bit | ||
1067 | + * individually. | ||
1068 | + */ | ||
1069 | + | ||
1070 | + /* First we clear all the 10/100 mb speed bits in the Auto-Neg | ||
1071 | + * Advertisement Register (Address 4) and the 1000 mb speed bits in | ||
1072 | + * the 1000Base-T Control Register (Address 9). | ||
1073 | + */ | ||
1074 | + mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK; | ||
1075 | + | ||
1076 | + /* Need to parse MediaType and setup the | ||
1077 | + * appropriate PHY registers. | ||
1078 | + */ | ||
1079 | + switch (hw->MediaType) { | ||
1080 | + case MEDIA_TYPE_AUTO_SENSOR: | ||
1081 | + mii_autoneg_adv_reg |= | ||
1082 | + (MII_AR_10T_HD_CAPS | | ||
1083 | + MII_AR_10T_FD_CAPS | | ||
1084 | + MII_AR_100TX_HD_CAPS | | ||
1085 | + MII_AR_100TX_FD_CAPS); | ||
1086 | + hw->autoneg_advertised = | ||
1087 | + ADVERTISE_10_HALF | | ||
1088 | + ADVERTISE_10_FULL | | ||
1089 | + ADVERTISE_100_HALF | | ||
1090 | + ADVERTISE_100_FULL; | ||
1091 | + break; | ||
1092 | + case MEDIA_TYPE_100M_FULL: | ||
1093 | + mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS; | ||
1094 | + hw->autoneg_advertised = ADVERTISE_100_FULL; | ||
1095 | + break; | ||
1096 | + case MEDIA_TYPE_100M_HALF: | ||
1097 | + mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS; | ||
1098 | + hw->autoneg_advertised = ADVERTISE_100_HALF; | ||
1099 | + break; | ||
1100 | + case MEDIA_TYPE_10M_FULL: | ||
1101 | + mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS; | ||
1102 | + hw->autoneg_advertised = ADVERTISE_10_FULL; | ||
1103 | + break; | ||
1104 | + default: | ||
1105 | + mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS; | ||
1106 | + hw->autoneg_advertised = ADVERTISE_10_HALF; | ||
1107 | + break; | ||
1108 | + } | ||
1109 | + | ||
1110 | + /* flow control fixed to enable all */ | ||
1111 | + mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE); | ||
1112 | + | ||
1113 | + hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg; | ||
1114 | + | ||
1115 | + ret_val = atl2_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg); | ||
1116 | + | ||
1117 | + if(ret_val) | ||
1118 | + return ret_val; | ||
1119 | + | ||
1120 | + return ATL2_SUCCESS; | ||
1121 | +} | ||
1122 | + | ||
1123 | +/* | ||
1124 | + * Resets the PHY and make all config validate | ||
1125 | + * | ||
1126 | + * hw - Struct containing variables accessed by shared code | ||
1127 | + * | ||
1128 | + * Sets bit 15 and 12 of the MII Control regiser (for F001 bug) | ||
1129 | + */ | ||
1130 | +static s32 | ||
1131 | +atl2_phy_commit(struct atl2_hw *hw) | ||
1132 | +{ | ||
1133 | + s32 ret_val; | ||
1134 | + u16 phy_data; | ||
1135 | + | ||
1136 | +/* FIXME: use or remove -- CHS | ||
1137 | + if (hw->MediaType == MEDIA_TYPE_AUTO_SENSOR) { | ||
1138 | + phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN; | ||
1139 | + } else { | ||
1140 | + switch (hw->MediaType) | ||
1141 | + { | ||
1142 | + case MEDIA_TYPE_100M_FULL: | ||
1143 | + phy_data = MII_CR_FULL_DUPLEX|MII_CR_SPEED_100|MII_CR_RESET; | ||
1144 | + break; | ||
1145 | + case MEDIA_TYPE_100M_HALF: | ||
1146 | + phy_data = MII_CR_SPEED_100|MII_CR_RESET; | ||
1147 | + break; | ||
1148 | + case MEDIA_TYPE_10M_FULL: | ||
1149 | + phy_data = MII_CR_FULL_DUPLEX|MII_CR_SPEED_10|MII_CR_RESET; | ||
1150 | + break; | ||
1151 | + default: // MEDIA_TYPE_10M_HALF: | ||
1152 | + phy_data = MII_CR_SPEED_10|MII_CR_RESET; | ||
1153 | + break; | ||
1154 | + } | ||
1155 | + } | ||
1156 | +*/ | ||
1157 | + phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG; | ||
1158 | + ret_val = atl2_write_phy_reg(hw, MII_BMCR, phy_data); | ||
1159 | + if (ret_val) { // bug fixed | ||
1160 | + u32 val; | ||
1161 | + int i; | ||
1162 | + /* pcie serdes link may be down ! */ | ||
1163 | + for (i=0; i < 25; i++) { | ||
1164 | + msec_delay(1); | ||
1165 | + val = ATL2_READ_REG(hw, REG_MDIO_CTRL); | ||
1166 | + if (!(val & (MDIO_START | MDIO_BUSY))) | ||
1167 | + break; | ||
1168 | + } | ||
1169 | + | ||
1170 | + if (0 != (val & (MDIO_START | MDIO_BUSY))) { | ||
1171 | + printk(KERN_ERR "atl2: PCIe link down for at least 25ms !\n"); | ||
1172 | + return ret_val; | ||
1173 | + } | ||
1174 | + } | ||
1175 | + return ATL2_SUCCESS; | ||
1176 | +} | ||
1177 | + | ||
1178 | +s32 | ||
1179 | +atl2_phy_init(struct atl2_hw *hw) | ||
1180 | +{ | ||
1181 | + s32 ret_val; | ||
1182 | + u16 phy_val; | ||
1183 | + | ||
1184 | + if (hw->phy_configured) | ||
1185 | + return 0; | ||
1186 | + | ||
1187 | + /* Enable PHY */ | ||
1188 | + ATL2_WRITE_REGW(hw, REG_PHY_ENABLE, 1); | ||
1189 | + ATL2_WRITE_FLUSH(hw); | ||
1190 | + msec_delay(1); | ||
1191 | + | ||
1192 | + /* check if the PHY is in powersaving mode */ | ||
1193 | + atl2_write_phy_reg(hw, MII_DBG_ADDR, 0); | ||
1194 | + atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val); | ||
1195 | + | ||
1196 | + /* 024E / 124E 0r 0274 / 1274 ? */ | ||
1197 | + if (phy_val & 0x1000) { | ||
1198 | + phy_val &= ~0x1000; | ||
1199 | + atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val); | ||
1200 | + } | ||
1201 | + | ||
1202 | + msec_delay(1); | ||
1203 | + | ||
1204 | + | ||
1205 | + /*Enable PHY LinkChange Interrupt */ | ||
1206 | + ret_val = atl2_write_phy_reg(hw, 18, 0xC00); | ||
1207 | + if (ret_val) | ||
1208 | + return ret_val; | ||
1209 | + | ||
1210 | + /* setup AutoNeg parameters */ | ||
1211 | + ret_val = atl2_phy_setup_autoneg_adv(hw); | ||
1212 | + if(ret_val) | ||
1213 | + return ret_val; | ||
1214 | + | ||
1215 | + /* SW.Reset & En-Auto-Neg to restart Auto-Neg */ | ||
1216 | + ret_val = atl2_phy_commit(hw); | ||
1217 | + if (ret_val) | ||
1218 | + return ret_val; | ||
1219 | + | ||
1220 | + hw->phy_configured = true; | ||
1221 | + | ||
1222 | + return ret_val; | ||
1223 | +} | ||
1224 | + | ||
1225 | +void | ||
1226 | +atl2_set_mac_addr(struct atl2_hw *hw) | ||
1227 | +{ | ||
1228 | + u32 value; | ||
1229 | + // 00-0B-6A-F6-00-DC | ||
1230 | + // 0: 6AF600DC 1: 000B | ||
1231 | + // low dword | ||
1232 | + value = (((u32)hw->mac_addr[2]) << 24) | | ||
1233 | + (((u32)hw->mac_addr[3]) << 16) | | ||
1234 | + (((u32)hw->mac_addr[4]) << 8 ) | | ||
1235 | + (((u32)hw->mac_addr[5]) ) ; | ||
1236 | + ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value); | ||
1237 | + // hight dword | ||
1238 | + value = (((u32)hw->mac_addr[0]) << 8 ) | | ||
1239 | + (((u32)hw->mac_addr[1]) ) ; | ||
1240 | + ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value); | ||
1241 | +} | ||
1242 | + | ||
1243 | +/* | ||
1244 | + * check_eeprom_exist | ||
1245 | + * return 0 if eeprom exist | ||
1246 | + */ | ||
1247 | +int | ||
1248 | +atl2_check_eeprom_exist(struct atl2_hw *hw) | ||
1249 | +{ | ||
1250 | + u32 value; | ||
1251 | + | ||
1252 | + value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL); | ||
1253 | + if (value & SPI_FLASH_CTRL_EN_VPD) { | ||
1254 | + value &= ~SPI_FLASH_CTRL_EN_VPD; | ||
1255 | + ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value); | ||
1256 | + } | ||
1257 | + value = ATL2_READ_REGW(hw, REG_PCIE_CAP_LIST); | ||
1258 | + return ((value & 0xFF00) == 0x6C00) ? 0 : 1; | ||
1259 | +} | ||
1260 | + | ||
1261 | +// FIXME: This doesn't look right. -- CHS | ||
1262 | +bool | ||
1263 | +atl2_write_eeprom(struct atl2_hw *hw, u32 offset, u32 value) | ||
1264 | +{ | ||
1265 | + return true; | ||
1266 | +} | ||
1267 | + | ||
1268 | +bool | ||
1269 | +atl2_read_eeprom(struct atl2_hw *hw, u32 Offset, u32 *pValue) | ||
1270 | +{ | ||
1271 | + int i; | ||
1272 | + u32 Control; | ||
1273 | + | ||
1274 | + if (Offset & 0x3) | ||
1275 | + return false; /* address do not align */ | ||
1276 | + | ||
1277 | + ATL2_WRITE_REG(hw, REG_VPD_DATA, 0); | ||
1278 | + Control = (Offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT; | ||
1279 | + ATL2_WRITE_REG(hw, REG_VPD_CAP, Control); | ||
1280 | + | ||
1281 | + for (i = 0; i < 10; i++) { | ||
1282 | + msec_delay(2); | ||
1283 | + Control = ATL2_READ_REG(hw, REG_VPD_CAP); | ||
1284 | + if (Control & VPD_CAP_VPD_FLAG) | ||
1285 | + break; | ||
1286 | + } | ||
1287 | + | ||
1288 | + if (Control & VPD_CAP_VPD_FLAG) { | ||
1289 | + *pValue = ATL2_READ_REG(hw, REG_VPD_DATA); | ||
1290 | + return true; | ||
1291 | + } | ||
1292 | + return false; /* timeout */ | ||
1293 | +} | ||
1294 | + | ||
1295 | +void | ||
1296 | +atl2_force_ps(struct atl2_hw *hw) | ||
1297 | +{ | ||
1298 | + u16 phy_val; | ||
1299 | + | ||
1300 | + atl2_write_phy_reg(hw, MII_DBG_ADDR, 0); | ||
1301 | + atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val); | ||
1302 | + atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val | 0x1000); | ||
1303 | + | ||
1304 | + atl2_write_phy_reg(hw, MII_DBG_ADDR, 2); | ||
1305 | + atl2_write_phy_reg(hw, MII_DBG_DATA, 0x3000); | ||
1306 | + atl2_write_phy_reg(hw, MII_DBG_ADDR, 3); | ||
1307 | + atl2_write_phy_reg(hw, MII_DBG_DATA, 0); | ||
1308 | +} | ||
1309 | diff -Nurp a/drivers/net/atl2/atl2_hw.h b/drivers/net/atl2/atl2_hw.h | ||
1310 | --- a/drivers/net/atl2/atl2_hw.h 1969-12-31 19:00:00.000000000 -0500 | ||
1311 | +++ b/drivers/net/atl2/atl2_hw.h 2007-12-10 12:45:11.000000000 -0500 | ||
1312 | @@ -0,0 +1,758 @@ | ||
1313 | +/* atl2_hw.h -- atl2 hardware definitions | ||
1314 | + * | ||
1315 | + * Copyright(c) 2007 Atheros Corporation. All rights reserved. | ||
1316 | + * Copyright(c) 2006 xiong huang <xiong.huang@atheros.com> | ||
1317 | + * Copyright(c) 2007 Chris Snook <csnook@redhat.com> | ||
1318 | + * | ||
1319 | + * Derived from Intel e1000 driver | ||
1320 | + * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. | ||
1321 | + * | ||
1322 | + * This program is free software; you can redistribute it and/or modify it | ||
1323 | + * under the terms of the GNU General Public License as published by the Free | ||
1324 | + * Software Foundation; either version 2 of the License, or (at your option) | ||
1325 | + * any later version. | ||
1326 | + * | ||
1327 | + * This program is distributed in the hope that it will be useful, but WITHOUT | ||
1328 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
1329 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
1330 | + * more details. | ||
1331 | + * | ||
1332 | + * You should have received a copy of the GNU General Public License along with | ||
1333 | + * this program; if not, write to the Free Software Foundation, Inc., 59 | ||
1334 | + * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
1335 | + * | ||
1336 | + * Some of these defines are unused for various reasons. Some describe | ||
1337 | + * hardware features we don't yet use. Some are specific to the cousin atl1 | ||
1338 | + * hardware, which we may merge this driver with in the future. Please | ||
1339 | + * remember this is a surrogate for hardware specs, and don't unnecessarily | ||
1340 | + * abuse the content or formatting. -- CHS | ||
1341 | + */ | ||
1342 | + | ||
1343 | +#ifndef _ATL2_HW_H_ | ||
1344 | +#define _ATL2_HW_H_ | ||
1345 | + | ||
1346 | +#include "atl2_osdep.h" | ||
1347 | + | ||
1348 | +struct atl2_adapter; | ||
1349 | +struct atl2_hw; | ||
1350 | + | ||
1351 | +/* function prototype */ | ||
1352 | +s32 atl2_reset_hw(struct atl2_hw *hw); | ||
1353 | +s32 atl2_read_mac_addr(struct atl2_hw *hw); | ||
1354 | +s32 atl2_init_hw(struct atl2_hw *hw); | ||
1355 | +s32 atl2_get_speed_and_duplex(struct atl2_hw *hw, u16 *speed, u16 *duplex); | ||
1356 | +u32 atl2_auto_get_fc(struct atl2_adapter *adapter, u16 duplex); | ||
1357 | +u32 atl2_hash_mc_addr(struct atl2_hw *hw, u8 *mc_addr); | ||
1358 | +void atl2_hash_set(struct atl2_hw *hw, u32 hash_value); | ||
1359 | +s32 atl2_read_phy_reg(struct atl2_hw *hw, u16 reg_addr, u16 *phy_data); | ||
1360 | +s32 atl2_write_phy_reg(struct atl2_hw *hw, u32 reg_addr, u16 phy_data); | ||
1361 | +void atl2_read_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value); | ||
1362 | +void atl2_write_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value); | ||
1363 | +s32 atl2_validate_mdi_setting(struct atl2_hw *hw); | ||
1364 | +void atl2_set_mac_addr(struct atl2_hw *hw); | ||
1365 | +bool atl2_read_eeprom(struct atl2_hw *hw, u32 Offset, u32 *pValue); | ||
1366 | +bool atl2_write_eeprom(struct atl2_hw *hw, u32 offset, u32 value); | ||
1367 | +s32 atl2_phy_init(struct atl2_hw *hw); | ||
1368 | +int atl2_check_eeprom_exist(struct atl2_hw *hw); | ||
1369 | +void atl2_force_ps(struct atl2_hw *hw); | ||
1370 | + | ||
1371 | +/* register definition */ | ||
1372 | +#define REG_PM_CTRLSTAT 0x44 | ||
1373 | + | ||
1374 | +#define REG_PCIE_CAP_LIST 0x58 | ||
1375 | + | ||
1376 | +#define REG_VPD_CAP 0x6C | ||
1377 | +#define VPD_CAP_ID_MASK 0xff | ||
1378 | +#define VPD_CAP_ID_SHIFT 0 | ||
1379 | +#define VPD_CAP_NEXT_PTR_MASK 0xFF | ||
1380 | +#define VPD_CAP_NEXT_PTR_SHIFT 8 | ||
1381 | +#define VPD_CAP_VPD_ADDR_MASK 0x7FFF | ||
1382 | +#define VPD_CAP_VPD_ADDR_SHIFT 16 | ||
1383 | +#define VPD_CAP_VPD_FLAG 0x80000000 | ||
1384 | + | ||
1385 | +#define REG_VPD_DATA 0x70 | ||
1386 | + | ||
1387 | +#define REG_SPI_FLASH_CTRL 0x200 | ||
1388 | +#define SPI_FLASH_CTRL_STS_NON_RDY 0x1 | ||
1389 | +#define SPI_FLASH_CTRL_STS_WEN 0x2 | ||
1390 | +#define SPI_FLASH_CTRL_STS_WPEN 0x80 | ||
1391 | +#define SPI_FLASH_CTRL_DEV_STS_MASK 0xFF | ||
1392 | +#define SPI_FLASH_CTRL_DEV_STS_SHIFT 0 | ||
1393 | +#define SPI_FLASH_CTRL_INS_MASK 0x7 | ||
1394 | +#define SPI_FLASH_CTRL_INS_SHIFT 8 | ||
1395 | +#define SPI_FLASH_CTRL_START 0x800 | ||
1396 | +#define SPI_FLASH_CTRL_EN_VPD 0x2000 | ||
1397 | +#define SPI_FLASH_CTRL_LDSTART 0x8000 | ||
1398 | +#define SPI_FLASH_CTRL_CS_HI_MASK 0x3 | ||
1399 | +#define SPI_FLASH_CTRL_CS_HI_SHIFT 16 | ||
1400 | +#define SPI_FLASH_CTRL_CS_HOLD_MASK 0x3 | ||
1401 | +#define SPI_FLASH_CTRL_CS_HOLD_SHIFT 18 | ||
1402 | +#define SPI_FLASH_CTRL_CLK_LO_MASK 0x3 | ||
1403 | +#define SPI_FLASH_CTRL_CLK_LO_SHIFT 20 | ||
1404 | +#define SPI_FLASH_CTRL_CLK_HI_MASK 0x3 | ||
1405 | +#define SPI_FLASH_CTRL_CLK_HI_SHIFT 22 | ||
1406 | +#define SPI_FLASH_CTRL_CS_SETUP_MASK 0x3 | ||
1407 | +#define SPI_FLASH_CTRL_CS_SETUP_SHIFT 24 | ||
1408 | +#define SPI_FLASH_CTRL_EROM_PGSZ_MASK 0x3 | ||
1409 | +#define SPI_FLASH_CTRL_EROM_PGSZ_SHIFT 26 | ||
1410 | +#define SPI_FLASH_CTRL_WAIT_READY 0x10000000 | ||
1411 | + | ||
1412 | +#define REG_SPI_ADDR 0x204 | ||
1413 | + | ||
1414 | +#define REG_SPI_DATA 0x208 | ||
1415 | + | ||
1416 | +#define REG_SPI_FLASH_CONFIG 0x20C | ||
1417 | +#define SPI_FLASH_CONFIG_LD_ADDR_MASK 0xFFFFFF | ||
1418 | +#define SPI_FLASH_CONFIG_LD_ADDR_SHIFT 0 | ||
1419 | +#define SPI_FLASH_CONFIG_VPD_ADDR_MASK 0x3 | ||
1420 | +#define SPI_FLASH_CONFIG_VPD_ADDR_SHIFT 24 | ||
1421 | +#define SPI_FLASH_CONFIG_LD_EXIST 0x4000000 | ||
1422 | + | ||
1423 | +#define REG_SPI_FLASH_OP_PROGRAM 0x210 | ||
1424 | +#define REG_SPI_FLASH_OP_SC_ERASE 0x211 | ||
1425 | +#define REG_SPI_FLASH_OP_CHIP_ERASE 0x212 | ||
1426 | +#define REG_SPI_FLASH_OP_RDID 0x213 | ||
1427 | +#define REG_SPI_FLASH_OP_WREN 0x214 | ||
1428 | +#define REG_SPI_FLASH_OP_RDSR 0x215 | ||
1429 | +#define REG_SPI_FLASH_OP_WRSR 0x216 | ||
1430 | +#define REG_SPI_FLASH_OP_READ 0x217 | ||
1431 | + | ||
1432 | +#define REG_TWSI_CTRL 0x218 | ||
1433 | +#define TWSI_CTRL_LD_OFFSET_MASK 0xFF | ||
1434 | +#define TWSI_CTRL_LD_OFFSET_SHIFT 0 | ||
1435 | +#define TWSI_CTRL_LD_SLV_ADDR_MASK 0x7 | ||
1436 | +#define TWSI_CTRL_LD_SLV_ADDR_SHIFT 8 | ||
1437 | +#define TWSI_CTRL_SW_LDSTART 0x800 | ||
1438 | +#define TWSI_CTRL_HW_LDSTART 0x1000 | ||
1439 | +#define TWSI_CTRL_SMB_SLV_ADDR_MASK 0x0x7F | ||
1440 | +#define TWSI_CTRL_SMB_SLV_ADDR_SHIFT 15 | ||
1441 | +#define TWSI_CTRL_LD_EXIST 0x400000 | ||
1442 | +#define TWSI_CTRL_READ_FREQ_SEL_MASK 0x3 | ||
1443 | +#define TWSI_CTRL_READ_FREQ_SEL_SHIFT 23 | ||
1444 | +#define TWSI_CTRL_FREQ_SEL_100K 0 | ||
1445 | +#define TWSI_CTRL_FREQ_SEL_200K 1 | ||
1446 | +#define TWSI_CTRL_FREQ_SEL_300K 2 | ||
1447 | +#define TWSI_CTRL_FREQ_SEL_400K 3 | ||
1448 | +#define TWSI_CTRL_SMB_SLV_ADDR | ||
1449 | +#define TWSI_CTRL_WRITE_FREQ_SEL_MASK 0x3 | ||
1450 | +#define TWSI_CTRL_WRITE_FREQ_SEL_SHIFT 24 | ||
1451 | + | ||
1452 | +#define REG_PCIE_DEV_MISC_CTRL 0x21C | ||
1453 | +#define PCIE_DEV_MISC_CTRL_EXT_PIPE 0x2 | ||
1454 | +#define PCIE_DEV_MISC_CTRL_RETRY_BUFDIS 0x1 | ||
1455 | +#define PCIE_DEV_MISC_CTRL_SPIROM_EXIST 0x4 | ||
1456 | +#define PCIE_DEV_MISC_CTRL_SERDES_ENDIAN 0x8 | ||
1457 | +#define PCIE_DEV_MISC_CTRL_SERDES_SEL_DIN 0x10 | ||
1458 | + | ||
1459 | +#define REG_PCIE_PHYMISC 0x1000 | ||
1460 | +#define PCIE_PHYMISC_FORCE_RCV_DET 0x4 | ||
1461 | + | ||
1462 | +#define REG_PCIE_DLL_TX_CTRL1 0x1104 | ||
1463 | +#define PCIE_DLL_TX_CTRL1_SEL_NOR_CLK 0x0400 | ||
1464 | +#define PCIE_DLL_TX_CTRL1_DEF 0x0568 | ||
1465 | + | ||
1466 | +#define REG_LTSSM_TEST_MODE 0x12FC | ||
1467 | +#define LTSSM_TEST_MODE_DEF 0x6500 | ||
1468 | + | ||
1469 | +/* Master Control Register */ | ||
1470 | +#define REG_MASTER_CTRL 0x1400 | ||
1471 | +#define MASTER_CTRL_SOFT_RST 0x1 | ||
1472 | +#define MASTER_CTRL_MTIMER_EN 0x2 | ||
1473 | +#define MASTER_CTRL_ITIMER_EN 0x4 | ||
1474 | +#define MASTER_CTRL_MANUAL_INT 0x8 | ||
1475 | +#define MASTER_CTRL_REV_NUM_SHIFT 16 | ||
1476 | +#define MASTER_CTRL_REV_NUM_MASK 0xff | ||
1477 | +#define MASTER_CTRL_DEV_ID_SHIFT 24 | ||
1478 | +#define MASTER_CTRL_DEV_ID_MASK 0xff | ||
1479 | + | ||
1480 | +/* Timer Initial Value Register */ | ||
1481 | +#define REG_MANUAL_TIMER_INIT 0x1404 | ||
1482 | + | ||
1483 | +/* IRQ ModeratorTimer Initial Value Register */ | ||
1484 | +#define REG_IRQ_MODU_TIMER_INIT 0x1408 | ||
1485 | + | ||
1486 | +#define REG_PHY_ENABLE 0x140C | ||
1487 | +// IRQ Anti-Lost Timer Initial Value Register | ||
1488 | +//#define REG_IRQ_CLR_TIMER 0x140c // Maximum allowance for software to clear the interrupt. | ||
1489 | +// IRQ Anti-Lost Timer Initial Value Register | ||
1490 | +#define REG_CMBDISDMA_TIMER 0x140E | ||
1491 | + | ||
1492 | +/* Block IDLE Status Register */ | ||
1493 | +#define REG_IDLE_STATUS 0x1410 | ||
1494 | +#define IDLE_STATUS_RXMAC 1 /* 1: RXMAC state machine is in non-IDLE state. 0: RXMAC is idling */ | ||
1495 | +#define IDLE_STATUS_TXMAC 2 /* 1: TXMAC state machine is in non-IDLE state. 0: TXMAC is idling */ | ||
1496 | +#define IDLE_STATUS_DMAR 8 /* 1: DMAR state machine is in non-IDLE state. 0: DMAR is idling */ | ||
1497 | +#define IDLE_STATUS_DMAW 4 /* 1: DMAW state machine is in non-IDLE state. 0: DMAW is idling */ | ||
1498 | + | ||
1499 | +/* MDIO Control Register */ | ||
1500 | +#define REG_MDIO_CTRL 0x1414 | ||
1501 | +#define MDIO_DATA_MASK 0xffff /* On MDIO write, the 16-bit control data to write to PHY MII management register */ | ||
1502 | +#define MDIO_DATA_SHIFT 0 /* On MDIO read, the 16-bit status data that was read from the PHY MII management register. */ | ||
1503 | +#define MDIO_REG_ADDR_MASK 0x1f /* MDIO register address */ | ||
1504 | +#define MDIO_REG_ADDR_SHIFT 16 | ||
1505 | +#define MDIO_RW 0x200000 /* 1: read, 0: write */ | ||
1506 | +#define MDIO_SUP_PREAMBLE 0x400000 /* Suppress preamble */ | ||
1507 | +#define MDIO_START 0x800000 /* Write 1 to initiate the MDIO master. And this bit is self cleared after one cycle. */ | ||
1508 | +#define MDIO_CLK_SEL_SHIFT 24 | ||
1509 | +#define MDIO_CLK_25_4 0 | ||
1510 | +#define MDIO_CLK_25_6 2 | ||
1511 | +#define MDIO_CLK_25_8 3 | ||
1512 | +#define MDIO_CLK_25_10 4 | ||
1513 | +#define MDIO_CLK_25_14 5 | ||
1514 | +#define MDIO_CLK_25_20 6 | ||
1515 | +#define MDIO_CLK_25_28 7 | ||
1516 | +#define MDIO_BUSY 0x8000000 | ||
1517 | +#define MDIO_WAIT_TIMES 10 | ||
1518 | + | ||
1519 | +/* SerDes Lock Detect Control and Status Register */ | ||
1520 | +#define REG_SERDES_LOCK 0x1424 | ||
1521 | +#define SERDES_LOCK_DETECT 1 /* 1: SerDes lock detected. This signal comes from Analog SerDes. */ | ||
1522 | +#define SERDES_LOCK_DETECT_EN 2 /* 1: Enable SerDes Lock detect function. */ | ||
1523 | + | ||
1524 | +/* MAC Control Register */ | ||
1525 | +#define REG_MAC_CTRL 0x1480 | ||
1526 | +#define MAC_CTRL_TX_EN 1 /* 1: Transmit Enable */ | ||
1527 | +#define MAC_CTRL_RX_EN 2 /* 1: Receive Enable */ | ||
1528 | +#define MAC_CTRL_TX_FLOW 4 /* 1: Transmit Flow Control Enable */ | ||
1529 | +#define MAC_CTRL_RX_FLOW 8 /* 1: Receive Flow Control Enable */ | ||
1530 | +#define MAC_CTRL_LOOPBACK 0x10 /* 1: Loop back at G/MII Interface */ | ||
1531 | +#define MAC_CTRL_DUPLX 0x20 /* 1: Full-duplex mode 0: Half-duplex mode */ | ||
1532 | +#define MAC_CTRL_ADD_CRC 0x40 /* 1: Instruct MAC to attach CRC on all egress Ethernet frames */ | ||
1533 | +#define MAC_CTRL_PAD 0x80 /* 1: Instruct MAC to pad short frames to 60-bytes, and then attach CRC. This bit has higher priority over CRC_EN */ | ||
1534 | +#define MAC_CTRL_PRMLEN_SHIFT 10 /* Preamble length, it's 0x07 by standard */ | ||
1535 | +#define MAC_CTRL_PRMLEN_MASK 0xf | ||
1536 | +#define MAC_CTRL_RMV_VLAN 0x4000 /* 1: to remove VLAN Tag automatically from all receive packets */ | ||
1537 | +#define MAC_CTRL_PROMIS_EN 0x8000 /* 1: Promiscuous Mode Enable */ | ||
1538 | +#define MAC_CTRL_DBG_TX_BKPRESURE 0x100000 /* 1: transmit maximum backoff (half-duplex test bit) */ | ||
1539 | +#define MAC_CTRL_MC_ALL_EN 0x2000000 /* 1: upload all multicast frame without error to system */ | ||
1540 | +#define MAC_CTRL_BC_EN 0x4000000 /* 1: upload all broadcast frame without error to system */ | ||
1541 | +#define MAC_CTRL_MACLP_CLK_PHY 0x8000000 /* 1: MAC-LoopBack clock from phy, 0:from sys_25M */ | ||
1542 | +#define MAC_CTRL_HALF_LEFT_BUF_SHIFT 28 | ||
1543 | +#define MAC_CTRL_HALF_LEFT_BUF_MASK 0xF /* When half-duplex mode, should hold some bytes for mac retry . (8*4bytes unit) */ | ||
1544 | + | ||
1545 | +/* MAC IPG/IFG Control Register */ | ||
1546 | +#define REG_MAC_IPG_IFG 0x1484 | ||
1547 | +#define MAC_IPG_IFG_IPGT_SHIFT 0 /* Desired back to back inter-packet gap. The default is 96-bit time. */ | ||
1548 | +#define MAC_IPG_IFG_IPGT_MASK 0x7f | ||
1549 | +#define MAC_IPG_IFG_MIFG_SHIFT 8 /* Minimum number of IFG to enforce in between RX frames. */ | ||
1550 | +#define MAC_IPG_IFG_MIFG_MASK 0xff /* Frame gap below such IFP is dropped. */ | ||
1551 | +#define MAC_IPG_IFG_IPGR1_SHIFT 16 /* 64bit Carrier-Sense window */ | ||
1552 | +#define MAC_IPG_IFG_IPGR1_MASK 0x7f | ||
1553 | +#define MAC_IPG_IFG_IPGR2_SHIFT 24 /* 96-bit IPG window */ | ||
1554 | +#define MAC_IPG_IFG_IPGR2_MASK 0x7f | ||
1555 | + | ||
1556 | +/* MAC STATION ADDRESS */ | ||
1557 | +#define REG_MAC_STA_ADDR 0x1488 | ||
1558 | + | ||
1559 | +/* Hash table for multicast address */ | ||
1560 | +#define REG_RX_HASH_TABLE 0x1490 | ||
1561 | + | ||
1562 | +/* MAC Half-Duplex Control Register */ | ||
1563 | +#define REG_MAC_HALF_DUPLX_CTRL 0x1498 | ||
1564 | +#define MAC_HALF_DUPLX_CTRL_LCOL_SHIFT 0 /* Collision Window. */ | ||
1565 | +#define MAC_HALF_DUPLX_CTRL_LCOL_MASK 0x3ff | ||
1566 | +#define MAC_HALF_DUPLX_CTRL_RETRY_SHIFT 12 /* Retransmission maximum, afterwards the packet will be discarded. */ | ||
1567 | +#define MAC_HALF_DUPLX_CTRL_RETRY_MASK 0xf | ||
1568 | +#define MAC_HALF_DUPLX_CTRL_EXC_DEF_EN 0x10000 /* 1: Allow the transmission of a packet which has been excessively deferred */ | ||
1569 | +#define MAC_HALF_DUPLX_CTRL_NO_BACK_C 0x20000 /* 1: No back-off on collision, immediately start the retransmission. */ | ||
1570 | +#define MAC_HALF_DUPLX_CTRL_NO_BACK_P 0x40000 /* 1: No back-off on backpressure, immediately start the transmission after back pressure */ | ||
1571 | +#define MAC_HALF_DUPLX_CTRL_ABEBE 0x80000 /* 1: Alternative Binary Exponential Back-off Enabled */ | ||
1572 | +#define MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT 20 /* Maximum binary exponential number. */ | ||
1573 | +#define MAC_HALF_DUPLX_CTRL_ABEBT_MASK 0xf | ||
1574 | +#define MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT 24 /* IPG to start JAM for collision based flow control in half-duplex */ | ||
1575 | +#define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK 0xf /* mode. In unit of 8-bit time. */ | ||
1576 | + | ||
1577 | +/* Maximum Frame Length Control Register */ | ||
1578 | +#define REG_MTU 0x149c | ||
1579 | + | ||
1580 | +/* Wake-On-Lan control register */ | ||
1581 | +#define REG_WOL_CTRL 0x14a0 | ||
1582 | +#define WOL_PATTERN_EN 0x00000001 | ||
1583 | +#define WOL_PATTERN_PME_EN 0x00000002 | ||
1584 | +#define WOL_MAGIC_EN 0x00000004 | ||
1585 | +#define WOL_MAGIC_PME_EN 0x00000008 | ||
1586 | +#define WOL_LINK_CHG_EN 0x00000010 | ||
1587 | +#define WOL_LINK_CHG_PME_EN 0x00000020 | ||
1588 | +#define WOL_PATTERN_ST 0x00000100 | ||
1589 | +#define WOL_MAGIC_ST 0x00000200 | ||
1590 | +#define WOL_LINKCHG_ST 0x00000400 | ||
1591 | +#define WOL_PT0_EN 0x00010000 | ||
1592 | +#define WOL_PT1_EN 0x00020000 | ||
1593 | +#define WOL_PT2_EN 0x00040000 | ||
1594 | +#define WOL_PT3_EN 0x00080000 | ||
1595 | +#define WOL_PT4_EN 0x00100000 | ||
1596 | +#define WOL_PT0_MATCH 0x01000000 | ||
1597 | +#define WOL_PT1_MATCH 0x02000000 | ||
1598 | +#define WOL_PT2_MATCH 0x04000000 | ||
1599 | +#define WOL_PT3_MATCH 0x08000000 | ||
1600 | +#define WOL_PT4_MATCH 0x10000000 | ||
1601 | + | ||
1602 | +/* Internal SRAM Partition Register */ | ||
1603 | +#define REG_SRAM_TXRAM_END 0x1500 /* Internal tail address of TXRAM default: 2byte*1024 */ | ||
1604 | +#define REG_SRAM_RXRAM_END 0x1502 /* Internal tail address of RXRAM default: 2byte*1024 */ | ||
1605 | + | ||
1606 | +/* | ||
1607 | +#define REG_SRAM_TCPH_PATH_ADDR (REG_SRAM_RFD_ADDR+48) | ||
1608 | +#define SRAM_TCPH_ADDR_MASK 0x0fff | ||
1609 | +#define SRAM_TCPH_ADDR_SHIFT 0 | ||
1610 | +#define SRAM_PATH_ADDR_MASK 0x0fff | ||
1611 | +#define SRAM_PATH_ADDR_SHIFT 16 | ||
1612 | +*/ | ||
1613 | + | ||
1614 | +/* Descriptor Control register */ | ||
1615 | +#define REG_DESC_BASE_ADDR_HI 0x1540 | ||
1616 | +#define REG_TXD_BASE_ADDR_LO 0x1544 /* The base address of the Transmit Data Memory low 32-bit(dword align) */ | ||
1617 | +#define REG_TXD_MEM_SIZE 0x1548 /* Transmit Data Memory size(by double word , max 256KB) */ | ||
1618 | +#define REG_TXS_BASE_ADDR_LO 0x154C /* The base address of the Transmit Status Memory low 32-bit(dword word align) */ | ||
1619 | +#define REG_TXS_MEM_SIZE 0x1550 /* double word unit, max 4*2047 bytes. */ | ||
1620 | +#define REG_RXD_BASE_ADDR_LO 0x1554 /* The base address of the Transmit Status Memory low 32-bit(unit 8 bytes) */ | ||
1621 | +#define REG_RXD_BUF_NUM 0x1558 /* Receive Data & Status Memory buffer number (unit 1536bytes, max 1536*2047) */ | ||
1622 | + | ||
1623 | +/* DMAR Control Register */ | ||
1624 | +#define REG_DMAR 0x1580 | ||
1625 | +#define DMAR_EN 0x1 /* 1: Enable DMAR */ | ||
1626 | + | ||
1627 | +/* TX Cur-Through (early tx threshold) Control Register */ | ||
1628 | +#define REG_TX_CUT_THRESH 0x1590 /* TxMac begin transmit packet threshold(unit word) */ | ||
1629 | + | ||
1630 | +/* DMAW Control Register */ | ||
1631 | +#define REG_DMAW 0x15A0 | ||
1632 | +#define DMAW_EN 0x1 | ||
1633 | + | ||
1634 | +/* Flow control register */ | ||
1635 | +#define REG_PAUSE_ON_TH 0x15A8 /* RXD high watermark of overflow threshold configuration register */ | ||
1636 | +#define REG_PAUSE_OFF_TH 0x15AA /* RXD lower watermark of overflow threshold configuration register */ | ||
1637 | + | ||
1638 | +/* Mailbox Register */ | ||
1639 | +#define REG_MB_TXD_WR_IDX 0x15f0 /* double word align */ | ||
1640 | +#define REG_MB_RXD_RD_IDX 0x15F4 /* RXD Read index (unit: 1536byets) */ | ||
1641 | + | ||
1642 | +/* Interrupt Status Register */ | ||
1643 | +#define REG_ISR 0x1600 | ||
1644 | +#define ISR_TIMER 1 /* Interrupt when Timer is counted down to zero */ | ||
1645 | +#define ISR_MANUAL 2 /* Software manual interrupt, for debug. Set when SW_MAN_INT_EN is set in Table 51 Selene Master Control Register (Offset 0x1400). */ | ||
1646 | +#define ISR_RXF_OV 4 /* RXF overflow interrupt */ | ||
1647 | +#define ISR_TXF_UR 8 /* TXF underrun interrupt */ | ||
1648 | +#define ISR_TXS_OV 0x10 /* Internal transmit status buffer full interrupt */ | ||
1649 | +#define ISR_RXS_OV 0x20 /* Internal receive status buffer ful interrupt */ | ||
1650 | +#define ISR_LINK_CHG 0x40 /* Link Status Change Interrupt */ | ||
1651 | +#define ISR_HOST_TXD_UR 0x80 | ||
1652 | +#define ISR_HOST_RXD_OV 0x100 /* Host rx data memory full , one pulse */ | ||
1653 | +//#define ISR_HOST_TXS_OV 0x200 /* Host tx status memory full , one pulse */ | ||
1654 | +#define ISR_DMAR_TO_RST 0x200 /* DMAR op timeout interrupt. SW should do Reset */ | ||
1655 | +#define ISR_DMAW_TO_RST 0x400 | ||
1656 | +#define ISR_PHY 0x800 /* phy interrupt */ | ||
1657 | +#define ISR_TS_UPDATE 0x10000 /* interrupt after new tx pkt status written to host */ | ||
1658 | +#define ISR_RS_UPDATE 0x20000 /* interrupt ater new rx pkt status written to host. */ | ||
1659 | +#define ISR_TX_EARLY 0x40000 /* interrupt when txmac begin transmit one packet */ | ||
1660 | +#define ISR_UR_DETECTED 0x1000000 | ||
1661 | +#define ISR_FERR_DETECTED 0x2000000 | ||
1662 | +#define ISR_NFERR_DETECTED 0x4000000 | ||
1663 | +#define ISR_CERR_DETECTED 0x8000000 | ||
1664 | +#define ISR_PHY_LINKDOWN 0x10000000 | ||
1665 | +#define ISR_DIS_INT 0x80000000 | ||
1666 | + | ||
1667 | +#define ISR_TX_EVENT (ISR_TXF_UR|ISR_TXS_OV|ISR_HOST_TXD_UR|ISR_TS_UPDATE|ISR_TX_EARLY) | ||
1668 | +#define ISR_RX_EVENT (ISR_RXF_OV|ISR_RXS_OV|ISR_HOST_RXD_OV|ISR_RS_UPDATE) | ||
1669 | + | ||
1670 | +/* Interrupt Mask Register */ | ||
1671 | +#define REG_IMR 0x1604 | ||
1672 | + | ||
1673 | +#define IMR_NORMAL_MASK (\ | ||
1674 | + /*ISR_LINK_CHG |*/\ | ||
1675 | + ISR_MANUAL |\ | ||
1676 | + ISR_DMAR_TO_RST |\ | ||
1677 | + ISR_DMAW_TO_RST |\ | ||
1678 | + ISR_PHY |\ | ||
1679 | + ISR_PHY_LINKDOWN |\ | ||
1680 | + ISR_TS_UPDATE |\ | ||
1681 | + ISR_RS_UPDATE ) | ||
1682 | + | ||
1683 | +/* Receive MAC Statistics Registers */ | ||
1684 | +#define REG_STS_RX_PAUSE 0x1700 /* The number of Pause packet received */ | ||
1685 | +#define REG_STS_RXD_OV 0x1704 /* The number of frame dropped due to occurrence of RX FIFO overflow */ | ||
1686 | +#define REG_STS_RXS_OV 0x1708 /* The number of frame dropped due to occerrence of RX Status Buffer Overflow */ | ||
1687 | +#define REG_STS_RX_FILTER 0x170C /* The number of packet dropped due to address filtering */ | ||
1688 | + | ||
1689 | +/* MII definitions */ | ||
1690 | + | ||
1691 | +/* PHY Common Register */ | ||
1692 | +#define MII_AT001_CR 0x09 | ||
1693 | +#define MII_AT001_SR 0x0A | ||
1694 | +#define MII_AT001_ESR 0x0F | ||
1695 | +#define MII_AT001_PSCR 0x10 | ||
1696 | +#define MII_AT001_PSSR 0x11 | ||
1697 | +#define MII_SMARTSPEED 0x14 | ||
1698 | +#define MII_DBG_ADDR 0x1D | ||
1699 | +#define MII_DBG_DATA 0x1E | ||
1700 | + | ||
1701 | +/* PHY Control Register */ | ||
1702 | +#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */ | ||
1703 | +#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ | ||
1704 | +#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ | ||
1705 | +#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ | ||
1706 | +#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */ | ||
1707 | +#define MII_CR_POWER_DOWN 0x0800 /* Power down */ | ||
1708 | +#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ | ||
1709 | +#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */ | ||
1710 | +#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ | ||
1711 | +#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ | ||
1712 | +#define MII_CR_SPEED_MASK 0x2040 | ||
1713 | +#define MII_CR_SPEED_1000 0x0040 | ||
1714 | +#define MII_CR_SPEED_100 0x2000 | ||
1715 | +#define MII_CR_SPEED_10 0x0000 | ||
1716 | + | ||
1717 | +/* PHY Status Register */ | ||
1718 | +#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */ | ||
1719 | +#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ | ||
1720 | +#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ | ||
1721 | +#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ | ||
1722 | +#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ | ||
1723 | +#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ | ||
1724 | +#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ | ||
1725 | +#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */ | ||
1726 | +#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ | ||
1727 | +#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ | ||
1728 | +#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ | ||
1729 | +#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ | ||
1730 | +#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ | ||
1731 | +#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ | ||
1732 | +#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ | ||
1733 | + | ||
1734 | +/* Link partner ability register. */ | ||
1735 | +#define MII_LPA_SLCT 0x001f /* Same as advertise selector */ | ||
1736 | +#define MII_LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */ | ||
1737 | +#define MII_LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */ | ||
1738 | +#define MII_LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */ | ||
1739 | +#define MII_LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */ | ||
1740 | +#define MII_LPA_100BASE4 0x0200 /* 100BASE-T4 */ | ||
1741 | +#define MII_LPA_PAUSE 0x0400 /* PAUSE */ | ||
1742 | +#define MII_LPA_ASYPAUSE 0x0800 /* Asymmetrical PAUSE */ | ||
1743 | +#define MII_LPA_RFAULT 0x2000 /* Link partner faulted */ | ||
1744 | +#define MII_LPA_LPACK 0x4000 /* Link partner acked us */ | ||
1745 | +#define MII_LPA_NPAGE 0x8000 /* Next page bit */ | ||
1746 | + | ||
1747 | +/* Autoneg Advertisement Register */ | ||
1748 | +#define MII_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */ | ||
1749 | +#define MII_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ | ||
1750 | +#define MII_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ | ||
1751 | +#define MII_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ | ||
1752 | +#define MII_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ | ||
1753 | +#define MII_AR_100T4_CAPS 0x0200 /* 100T4 Capable */ | ||
1754 | +#define MII_AR_PAUSE 0x0400 /* Pause operation desired */ | ||
1755 | +#define MII_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ | ||
1756 | +#define MII_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */ | ||
1757 | +#define MII_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */ | ||
1758 | +#define MII_AR_SPEED_MASK 0x01E0 | ||
1759 | +#define MII_AR_DEFAULT_CAP_MASK 0x0DE0 | ||
1760 | + | ||
1761 | +/* 1000BASE-T Control Register */ | ||
1762 | +#define MII_AT001_CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ | ||
1763 | +#define MII_AT001_CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ | ||
1764 | +#define MII_AT001_CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port, 0=DTE device */ | ||
1765 | +#define MII_AT001_CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master, 0=Configure PHY as Slave */ | ||
1766 | +#define MII_AT001_CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value, 0=Automatic Master/Slave config */ | ||
1767 | +#define MII_AT001_CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */ | ||
1768 | +#define MII_AT001_CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */ | ||
1769 | +#define MII_AT001_CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */ | ||
1770 | +#define MII_AT001_CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */ | ||
1771 | +#define MII_AT001_CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */ | ||
1772 | +#define MII_AT001_CR_1000T_SPEED_MASK 0x0300 | ||
1773 | +#define MII_AT001_CR_1000T_DEFAULT_CAP_MASK 0x0300 | ||
1774 | + | ||
1775 | +/* 1000BASE-T Status Register */ | ||
1776 | +#define MII_AT001_SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */ | ||
1777 | +#define MII_AT001_SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */ | ||
1778 | +#define MII_AT001_SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ | ||
1779 | +#define MII_AT001_SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ | ||
1780 | +#define MII_AT001_SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */ | ||
1781 | +#define MII_AT001_SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */ | ||
1782 | +#define MII_AT001_SR_1000T_REMOTE_RX_STATUS_SHIFT 12 | ||
1783 | +#define MII_AT001_SR_1000T_LOCAL_RX_STATUS_SHIFT 13 | ||
1784 | + | ||
1785 | +/* Extended Status Register */ | ||
1786 | +#define MII_AT001_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */ | ||
1787 | +#define MII_AT001_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */ | ||
1788 | +#define MII_AT001_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */ | ||
1789 | +#define MII_AT001_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */ | ||
1790 | + | ||
1791 | +/* AT001 PHY Specific Control Register */ | ||
1792 | +#define MII_AT001_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */ | ||
1793 | +#define MII_AT001_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */ | ||
1794 | +#define MII_AT001_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled *// | ||
1795 | +#define MII_AT001_PSCR_MAC_POWERDOWN 0x0008 | ||
1796 | +#define MII_AT001_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low, 0=CLK125 toggling */ | ||
1797 | +#define MII_AT001_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5, Manual MDI configuration */ | ||
1798 | +#define MII_AT001_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ | ||
1799 | +#define MII_AT001_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */ | ||
1800 | +#define MII_AT001_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled all speeds. */ | ||
1801 | +#define MII_AT001_PSCR_10BT_EXT_DIST_ENABLE 0x0080 /* 1=Enable Extended 10BASE-T distance (Lower 10BASE-T RX Threshold), 0=Normal 10BASE-T RX Threshold */ | ||
1802 | +#define MII_AT001_PSCR_MII_5BIT_ENABLE 0x0100 /* 1=5-Bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */ | ||
1803 | +#define MII_AT001_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */ | ||
1804 | +#define MII_AT001_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */ | ||
1805 | +#define MII_AT001_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ | ||
1806 | +#define MII_AT001_PSCR_POLARITY_REVERSAL_SHIFT 1 | ||
1807 | +#define MII_AT001_PSCR_AUTO_X_MODE_SHIFT 5 | ||
1808 | +#define MII_AT001_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7 | ||
1809 | + | ||
1810 | +/* AT001 PHY Specific Status Register */ | ||
1811 | +#define MII_AT001_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */ | ||
1812 | +#define MII_AT001_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */ | ||
1813 | +#define MII_AT001_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ | ||
1814 | +#define MII_AT001_PSSR_10MBS 0x0000 /* 00=10Mbs */ | ||
1815 | +#define MII_AT001_PSSR_100MBS 0x4000 /* 01=100Mbs */ | ||
1816 | +#define MII_AT001_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ | ||
1817 | + | ||
1818 | +/* PCI Command Register Bit Definitions */ | ||
1819 | +#define PCI_REG_COMMAND 0x04 | ||
1820 | +#define CMD_IO_SPACE 0x0001 | ||
1821 | +#define CMD_MEMORY_SPACE 0x0002 | ||
1822 | +#define CMD_BUS_MASTER 0x0004 | ||
1823 | + | ||
1824 | +/* Wake Up Filter Control */ | ||
1825 | +#define ATL2_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ | ||
1826 | +#define ATL2_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ | ||
1827 | +#define ATL2_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ | ||
1828 | +#define ATL2_WUFC_MC 0x00000008 /* Multicast Wakeup Enable */ | ||
1829 | +#define ATL2_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ | ||
1830 | + | ||
1831 | +/* Error Codes */ | ||
1832 | +#define ATL2_SUCCESS 0 | ||
1833 | +#define ATL2_ERR_EEPROM 1 | ||
1834 | +#define ATL2_ERR_PHY 2 | ||
1835 | +#define ATL2_ERR_CONFIG 3 | ||
1836 | +#define ATL2_ERR_PARAM 4 | ||
1837 | +#define ATL2_ERR_MAC_TYPE 5 | ||
1838 | +#define ATL2_ERR_PHY_TYPE 6 | ||
1839 | +#define ATL2_ERR_PHY_SPEED 7 | ||
1840 | +#define ATL2_ERR_PHY_RES 8 | ||
1841 | + | ||
1842 | +#define SPEED_0 0xffff | ||
1843 | +#define SPEED_10 10 | ||
1844 | +#define SPEED_100 100 | ||
1845 | +#define HALF_DUPLEX 1 | ||
1846 | +#define FULL_DUPLEX 2 | ||
1847 | + | ||
1848 | +#define MEDIA_TYPE_AUTO_SENSOR 0 | ||
1849 | +#define MEDIA_TYPE_100M_FULL 1 | ||
1850 | +#define MEDIA_TYPE_100M_HALF 2 | ||
1851 | +#define MEDIA_TYPE_10M_FULL 3 | ||
1852 | +#define MEDIA_TYPE_10M_HALF 4 | ||
1853 | + | ||
1854 | +#define ADVERTISE_10_HALF 0x0001 | ||
1855 | +#define ADVERTISE_10_FULL 0x0002 | ||
1856 | +#define ADVERTISE_100_HALF 0x0004 | ||
1857 | +#define ADVERTISE_100_FULL 0x0008 | ||
1858 | +#define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */ | ||
1859 | +#define ADVERTISE_1000_FULL 0x0020 | ||
1860 | + | ||
1861 | +#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x000F /* Everything */ | ||
1862 | +#define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds*/ | ||
1863 | +#define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds*/ | ||
1864 | + | ||
1865 | +/* The size (in bytes) of a ethernet packet */ | ||
1866 | +#define ENET_HEADER_SIZE 14 | ||
1867 | +#define MAXIMUM_ETHERNET_FRAME_SIZE 1518 /* with FCS */ | ||
1868 | +#define MINIMUM_ETHERNET_FRAME_SIZE 64 /* with FCS */ | ||
1869 | +#define ETHERNET_FCS_SIZE 4 | ||
1870 | +#define MAX_JUMBO_FRAME_SIZE 0x2000 | ||
1871 | +#define VLAN_SIZE 4 | ||
1872 | + | ||
1873 | +#define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */ | ||
1874 | +#define PHY_FORCE_TIME 20 /* 2.0 Seconds */ | ||
1875 | + | ||
1876 | +/* For checksumming , the sum of all words in the EEPROM should equal 0xBABA */ | ||
1877 | +#define EEPROM_SUM 0xBABA | ||
1878 | +#define NODE_ADDRESS_SIZE 6 | ||
1879 | + | ||
1880 | +typedef struct _tx_pkt_header { | ||
1881 | + unsigned pkt_size : 11; | ||
1882 | + unsigned : 4; // reserved | ||
1883 | + unsigned ins_vlan : 1; // txmac should insert vlan | ||
1884 | + unsigned short vlan ; // vlan tag | ||
1885 | +} tx_pkt_header_t; | ||
1886 | +/* FIXME: replace above bitfields with MASK/SHIFT defines below */ | ||
1887 | +#define TX_PKT_HEADER_SIZE_MASK 0x7FF | ||
1888 | +#define TX_PKT_HEADER_SIZE_SHIFT 0 | ||
1889 | +#define TX_PKT_HEADER_INS_VLAN_MASK 0x1 | ||
1890 | +#define TX_PKT_HEADER_INS_VLAN_SHIFT 15 | ||
1891 | +#define TX_PKT_HEADER_VLAN_TAG_MASK 0xFFFF | ||
1892 | +#define TX_PKT_HEADER_VLAN_TAG_SHIFT 16 | ||
1893 | + | ||
1894 | +typedef struct _tx_pkt_status { | ||
1895 | + unsigned pkt_size : 11; | ||
1896 | + unsigned : 5; // reserved | ||
1897 | + unsigned ok : 1; // current packet is transmitted ok without error | ||
1898 | + unsigned bcast : 1; // current packet is broadcast | ||
1899 | + unsigned mcast : 1; // current packet is multicast | ||
1900 | + unsigned pause : 1; // transmiited a pause frame | ||
1901 | + unsigned ctrl : 1; | ||
1902 | + unsigned defer : 1; // current packet is xmitted with defer. | ||
1903 | + unsigned exc_defer : 1; | ||
1904 | + unsigned single_col : 1; | ||
1905 | + unsigned multi_col : 1; | ||
1906 | + unsigned late_col : 1; | ||
1907 | + unsigned abort_col : 1; | ||
1908 | + unsigned underun : 1; // current packet is abort due to txram underrun. | ||
1909 | + unsigned : 3; // reserved | ||
1910 | + unsigned update : 1; // always 1'b1 in tx_status_buf. | ||
1911 | +} tx_pkt_status_t; | ||
1912 | +/* FIXME: replace above bitfields with MASK/SHIFT defines below */ | ||
1913 | +#define TX_PKT_STATUS_SIZE_MASK 0x7FF | ||
1914 | +#define TX_PKT_STATUS_SIZE_SHIFT 0 | ||
1915 | +#define TX_PKT_STATUS_OK_MASK 0x1 | ||
1916 | +#define TX_PKT_STATUS_OK_SHIFT 16 | ||
1917 | +#define TX_PKT_STATUS_BCAST_MASK 0x1 | ||
1918 | +#define TX_PKT_STATUS_BCAST_SHIFT 17 | ||
1919 | +#define TX_PKT_STATUS_MCAST_MASK 0x1 | ||
1920 | +#define TX_PKT_STATUS_MCAST_SHIFT 18 | ||
1921 | +#define TX_PKT_STATUS_PAUSE_MASK 0x1 | ||
1922 | +#define TX_PKT_STATUS_PAUSE_SHIFT 19 | ||
1923 | +#define TX_PKT_STATUS_CTRL_MASK 0x1 | ||
1924 | +#define TX_PKT_STATUS_CTRL_SHIFT 20 | ||
1925 | +#define TX_PKT_STATUS_DEFER_MASK 0x1 | ||
1926 | +#define TX_PKT_STATUS_DEFER_SHIFT 21 | ||
1927 | +#define TX_PKT_STATUS_EXC_DEFER_MASK 0x1 | ||
1928 | +#define TX_PKT_STATUS_EXC_DEFER_SHIFT 22 | ||
1929 | +#define TX_PKT_STATUS_SINGLE_COL_MASK 0x1 | ||
1930 | +#define TX_PKT_STATUS_SINGLE_COL_SHIFT 23 | ||
1931 | +#define TX_PKT_STATUS_MULTI_COL_MASK 0x1 | ||
1932 | +#define TX_PKT_STATUS_MULTI_COL_SHIFT 24 | ||
1933 | +#define TX_PKT_STATUS_LATE_COL_MASK 0x1 | ||
1934 | +#define TX_PKT_STATUS_LATE_COL_SHIFT 25 | ||
1935 | +#define TX_PKT_STATUS_ABORT_COL_MASK 0x1 | ||
1936 | +#define TX_PKT_STATUS_ABORT_COL_SHIFT 26 | ||
1937 | +#define TX_PKT_STATUS_UNDERRUN_MASK 0x1 | ||
1938 | +#define TX_PKT_STATUS_UNDERRUN_SHIFT 27 | ||
1939 | +#define TX_PKT_STATUS_UPDATE_MASK 0x1 | ||
1940 | +#define TX_PKT_STATUS_UPDATE_SHIFT 31 | ||
1941 | + | ||
1942 | +typedef struct _rx_pkt_status { | ||
1943 | + unsigned pkt_size : 11; // packet size, max 2047bytes | ||
1944 | + unsigned : 5; // reserved | ||
1945 | + unsigned ok : 1; // current packet is received ok without error. | ||
1946 | + unsigned bcast : 1; // current packet is broadcast. | ||
1947 | + unsigned mcast : 1; // current packet is multicast. | ||
1948 | + unsigned pause : 1; | ||
1949 | + unsigned ctrl : 1; | ||
1950 | + unsigned crc : 1; // received a packet with crc error. | ||
1951 | + unsigned code : 1; // received a packet with code error. | ||
1952 | + unsigned runt : 1; // received a packet less than 64bytes with good crc | ||
1953 | + unsigned frag : 1; // ....................................with bad crc | ||
1954 | + unsigned trunc : 1; // current frame is cutted due to rxram full. | ||
1955 | + unsigned align : 1; // this packet is alignment error. | ||
1956 | + unsigned vlan : 1; // this packet has vlan | ||
1957 | + unsigned : 3; // reserved | ||
1958 | + unsigned update : 1; | ||
1959 | + unsigned short vtag ; // vlan tag | ||
1960 | + unsigned : 16; | ||
1961 | +} rx_pkt_status_t; | ||
1962 | +/* FIXME: replace above bitfields with MASK/SHIFT defines below */ | ||
1963 | +#define RX_PKT_STATUS_SIZE_MASK 0x7FF | ||
1964 | +#define RX_PKT_STATUS_SIZE_SHIFT 0 | ||
1965 | +#define RX_PKT_STATUS_OK_MASK 0x1 | ||
1966 | +#define RX_PKT_STATUS_OK_SHIFT 16 | ||
1967 | +#define RX_PKT_STATUS_BCAST_MASK 0x1 | ||
1968 | +#define RX_PKT_STATUS_BCAST_SHIFT 17 | ||
1969 | +#define RX_PKT_STATUS_MCAST_MASK 0x1 | ||
1970 | +#define RX_PKT_STATUS_MCAST_SHIFT 18 | ||
1971 | +#define RX_PKT_STATUS_PAUSE_MASK 0x1 | ||
1972 | +#define RX_PKT_STATUS_PAUSE_SHIFT 19 | ||
1973 | +#define RX_PKT_STATUS_CTRL_MASK 0x1 | ||
1974 | +#define RX_PKT_STATUS_CTRL_SHIFT 20 | ||
1975 | +#define RX_PKT_STATUS_CRC_MASK 0x1 | ||
1976 | +#define RX_PKT_STATUS_CRC_SHIFT 21 | ||
1977 | +#define RX_PKT_STATUS_CODE_MASK 0x1 | ||
1978 | +#define RX_PKT_STATUS_CODE_SHIFT 22 | ||
1979 | +#define RX_PKT_STATUS_RUNT_MASK 0x1 | ||
1980 | +#define RX_PKT_STATUS_RUNT_SHIFT 23 | ||
1981 | +#define RX_PKT_STATUS_FRAG_MASK 0x1 | ||
1982 | +#define RX_PKT_STATUS_FRAG_SHIFT 24 | ||
1983 | +#define RX_PKT_STATUS_TRUNK_MASK 0x1 | ||
1984 | +#define RX_PKT_STATUS_TRUNK_SHIFT 25 | ||
1985 | +#define RX_PKT_STATUS_ALIGN_MASK 0x1 | ||
1986 | +#define RX_PKT_STATUS_ALIGN_SHIFT 26 | ||
1987 | +#define RX_PKT_STATUS_VLAN_MASK 0x1 | ||
1988 | +#define RX_PKT_STATUS_VLAN_SHIFT 27 | ||
1989 | +#define RX_PKT_STATUS_UPDATE_MASK 0x1 | ||
1990 | +#define RX_PKT_STATUS_UPDATE_SHIFT 31 | ||
1991 | +#define RX_PKT_STATUS_VLAN_TAG_MASK 0xFFFF | ||
1992 | +#define RX_PKT_STATUS_VLAN_TAG_SHIFT 32 | ||
1993 | + | ||
1994 | +typedef struct _rx_desc { | ||
1995 | + rx_pkt_status_t status; | ||
1996 | + unsigned char packet[1536-sizeof(rx_pkt_status_t)]; | ||
1997 | +} rx_desc_t; | ||
1998 | + | ||
1999 | +typedef enum { | ||
2000 | + atl2_10_half = 0, | ||
2001 | + atl2_10_full = 1, | ||
2002 | + atl2_100_half = 2, | ||
2003 | + atl2_100_full = 3 | ||
2004 | +} atl2_speed_duplex_type; | ||
2005 | + | ||
2006 | +struct atl2_spi_flash_dev { | ||
2007 | + const char *manu_name; /* manufacturer id */ | ||
2008 | + /* op-code */ | ||
2009 | + u8 cmdWRSR; | ||
2010 | + u8 cmdREAD; | ||
2011 | + u8 cmdPROGRAM; | ||
2012 | + u8 cmdWREN; | ||
2013 | + u8 cmdWRDI; | ||
2014 | + u8 cmdRDSR; | ||
2015 | + u8 cmdRDID; | ||
2016 | + u8 cmdSECTOR_ERASE; | ||
2017 | + u8 cmdCHIP_ERASE; | ||
2018 | +}; | ||
2019 | + | ||
2020 | +/* Structure containing variables used by the shared code (atl2_hw.c) */ | ||
2021 | +struct atl2_hw { | ||
2022 | + u8 *hw_addr; | ||
2023 | + void *back; | ||
2024 | + | ||
2025 | + u8 preamble_len; | ||
2026 | + u8 max_retry; // Retransmission maximum , afterwards the packet will be discarded. | ||
2027 | + u8 jam_ipg; // IPG to start JAM for collision based flow control in half-duplex mode. In unit of 8-bit time. | ||
2028 | + u8 ipgt; // Desired back to back inter-packet gap. The default is 96-bit time. | ||
2029 | + u8 min_ifg; // Minimum number of IFG to enforce in between RX frames. Frame gap below such IFP is dropped. | ||
2030 | + u8 ipgr1; // 64bit Carrier-Sense window | ||
2031 | + u8 ipgr2; // 96-bit IPG window | ||
2032 | + u8 retry_buf; // When half-duplex mode, should hold some bytes for mac retry . (8*4bytes unit) | ||
2033 | + | ||
2034 | + u16 fc_rxd_hi; | ||
2035 | + u16 fc_rxd_lo; | ||
2036 | + u16 lcol; // Collision Window | ||
2037 | + u16 max_frame_size; | ||
2038 | + | ||
2039 | + u16 MediaType; | ||
2040 | + u16 autoneg_advertised; | ||
2041 | + u16 pci_cmd_word; | ||
2042 | + | ||
2043 | + u16 mii_autoneg_adv_reg; | ||
2044 | + | ||
2045 | + u32 mem_rang; | ||
2046 | + u32 txcw; | ||
2047 | + u32 mc_filter_type; | ||
2048 | + u32 num_mc_addrs; | ||
2049 | + u32 collision_delta; | ||
2050 | + u32 tx_packet_delta; | ||
2051 | + u16 phy_spd_default; | ||
2052 | + | ||
2053 | + u16 device_id; | ||
2054 | + u16 vendor_id; | ||
2055 | + u16 subsystem_id; | ||
2056 | + u16 subsystem_vendor_id; | ||
2057 | + u8 revision_id; | ||
2058 | + | ||
2059 | + // spi flash | ||
2060 | + u8 flash_vendor; | ||
2061 | + | ||
2062 | + u8 dma_fairness; | ||
2063 | + u8 mac_addr[NODE_ADDRESS_SIZE]; | ||
2064 | + u8 perm_mac_addr[NODE_ADDRESS_SIZE]; | ||
2065 | + | ||
2066 | + // bool phy_preamble_sup; | ||
2067 | + bool phy_configured; | ||
2068 | +}; | ||
2069 | + | ||
2070 | +#endif /* _ATL2_HW_H_ */ | ||
2071 | diff -Nurp a/drivers/net/atl2/atl2_main.c b/drivers/net/atl2/atl2_main.c | ||
2072 | --- a/drivers/net/atl2/atl2_main.c 1969-12-31 19:00:00.000000000 -0500 | ||
2073 | +++ b/drivers/net/atl2/atl2_main.c 2008-01-28 17:16:38.000000000 -0500 | ||
2074 | @@ -0,0 +1,1851 @@ | ||
2075 | +/* atl2_main.c -- atl2 driver main functions | ||
2076 | + * | ||
2077 | + * Copyright(c) 2007 Atheros Corporation. All rights reserved. | ||
2078 | + * Copyright(c) 2006 xiong huang <xiong.huang@atheros.com> | ||
2079 | + * Copyright(c) 2007 Chris Snook <csnook@redhat.com> | ||
2080 | + * | ||
2081 | + * Derived from Intel e1000 driver | ||
2082 | + * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. | ||
2083 | + * | ||
2084 | + * This program is free software; you can redistribute it and/or modify it | ||
2085 | + * under the terms of the GNU General Public License as published by the Free | ||
2086 | + * Software Foundation; either version 2 of the License, or (at your option) | ||
2087 | + * any later version. | ||
2088 | + * | ||
2089 | + * This program is distributed in the hope that it will be useful, but WITHOUT | ||
2090 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
2091 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
2092 | + * more details. | ||
2093 | + * | ||
2094 | + * You should have received a copy of the GNU General Public License along with | ||
2095 | + * this program; if not, write to the Free Software Foundation, Inc., 59 | ||
2096 | + * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
2097 | + */ | ||
2098 | + | ||
2099 | +#include <asm/atomic.h> | ||
2100 | +#include <linux/dma-mapping.h> | ||
2101 | +#include <linux/etherdevice.h> | ||
2102 | +#include <linux/hardirq.h> | ||
2103 | +#include <linux/if_vlan.h> | ||
2104 | +#include <linux/in.h> | ||
2105 | +#include <linux/interrupt.h> | ||
2106 | +#include <linux/ip.h> | ||
2107 | +#include <linux/irqflags.h> | ||
2108 | +#include <linux/irqreturn.h> | ||
2109 | +#include <linux/mii.h> | ||
2110 | +#include <linux/net.h> | ||
2111 | +#include <linux/netdevice.h> | ||
2112 | +#include <linux/pci.h> | ||
2113 | +#include <linux/pci_ids.h> | ||
2114 | +#include <linux/pm.h> | ||
2115 | +#include <linux/skbuff.h> | ||
2116 | +#include <linux/spinlock.h> | ||
2117 | +#include <linux/string.h> | ||
2118 | +#include <linux/tcp.h> | ||
2119 | +#include <linux/timer.h> | ||
2120 | +#include <linux/types.h> | ||
2121 | +#include <linux/workqueue.h> | ||
2122 | + | ||
2123 | +#include "atl2.h" | ||
2124 | + | ||
2125 | +#define ATL2_DRV_VERSION "2.0.4" | ||
2126 | + | ||
2127 | +char atl2_driver_name[] = "atl2"; | ||
2128 | +static const char atl2_driver_string[] = "Atheros(R) L2 Ethernet Driver"; | ||
2129 | +static char atl2_copyright[] = "Copyright (c) 2007 Atheros Corporation."; | ||
2130 | +char atl2_driver_version[] = ATL2_DRV_VERSION; | ||
2131 | + | ||
2132 | +MODULE_AUTHOR("Atheros Corporation <xiong.huang@atheros.com>, Chris Snook <csnook@redhat.com>"); | ||
2133 | +MODULE_DESCRIPTION("Atheros Fast Ethernet Network Driver"); | ||
2134 | +MODULE_LICENSE("GPL"); | ||
2135 | +MODULE_VERSION(ATL2_DRV_VERSION); | ||
2136 | + | ||
2137 | +/* FIXME: remove this after merging, goes in pci_ids.h */ | ||
2138 | +#ifndef PCI_DEVICE_ID_ATTANSIC_L2 | ||
2139 | +#define PCI_DEVICE_ID_ATTANSIC_L2 0x2048 | ||
2140 | +#endif | ||
2141 | + | ||
2142 | +/* | ||
2143 | + * atl2_pci_tbl - PCI Device ID Table | ||
2144 | + */ | ||
2145 | +static struct pci_device_id atl2_pci_tbl[] = { | ||
2146 | + {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L2)}, | ||
2147 | + /* required last entry */ | ||
2148 | + {0,} | ||
2149 | +}; | ||
2150 | +MODULE_DEVICE_TABLE(pci, atl2_pci_tbl); | ||
2151 | + | ||
2152 | +extern void atl2_set_ethtool_ops(struct net_device *netdev); | ||
2153 | +#ifdef ETHTOOL_OPS_COMPAT | ||
2154 | +extern int ethtool_ioctl(struct ifreq *ifr); | ||
2155 | +#endif | ||
2156 | + | ||
2157 | +#define COPYBREAK_DEFAULT 256 | ||
2158 | +static unsigned int copybreak __read_mostly = COPYBREAK_DEFAULT; | ||
2159 | +module_param(copybreak, uint, 0644); | ||
2160 | +MODULE_PARM_DESC(copybreak, "Maximum size of packet that is copied to a new buffer on receive"); | ||
2161 | + | ||
2162 | +extern void atl2_check_options(struct atl2_adapter *adapter); | ||
2163 | +#ifdef SIOCDEVPRIVATE | ||
2164 | +extern int atl2_priv_ioctl(struct net_device* netdev, struct ifreq* ifr); | ||
2165 | +#endif | ||
2166 | + | ||
2167 | +/** | ||
2168 | + * atl2_sw_init - Initialize general software structures (struct atl2_adapter) | ||
2169 | + * @adapter: board private structure to initialize | ||
2170 | + * | ||
2171 | + * atl2_sw_init initializes the Adapter private data structure. | ||
2172 | + * Fields are initialized based on PCI device information and | ||
2173 | + * OS network device settings (MTU size). | ||
2174 | + **/ | ||
2175 | +static int __devinit | ||
2176 | +atl2_sw_init(struct atl2_adapter *adapter) | ||
2177 | +{ | ||
2178 | + struct atl2_hw *hw = &adapter->hw; | ||
2179 | + struct pci_dev *pdev = adapter->pdev; | ||
2180 | + | ||
2181 | + /* PCI config space info */ | ||
2182 | + hw->vendor_id = pdev->vendor; | ||
2183 | + hw->device_id = pdev->device; | ||
2184 | + hw->subsystem_vendor_id = pdev->subsystem_vendor; | ||
2185 | + hw->subsystem_id = pdev->subsystem_device; | ||
2186 | + | ||
2187 | + pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id); | ||
2188 | + pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word); | ||
2189 | + | ||
2190 | + adapter->wol = 0; | ||
2191 | + adapter->ict = 50000; // 100ms | ||
2192 | + adapter->link_speed = SPEED_0; // hardware init | ||
2193 | + adapter->link_duplex = FULL_DUPLEX; | ||
2194 | + | ||
2195 | + hw->phy_configured = false; | ||
2196 | + hw->preamble_len = 7; | ||
2197 | + hw->ipgt = 0x60; | ||
2198 | + hw->min_ifg = 0x50; | ||
2199 | + hw->ipgr1 = 0x40; | ||
2200 | + hw->ipgr2 = 0x60; | ||
2201 | + hw->retry_buf = 2; | ||
2202 | + hw->max_retry = 0xf; | ||
2203 | + hw->lcol = 0x37; | ||
2204 | + hw->jam_ipg = 7; | ||
2205 | + hw->fc_rxd_hi = 0; | ||
2206 | + hw->fc_rxd_lo = 0; | ||
2207 | + hw->max_frame_size = adapter->netdev->mtu; | ||
2208 | + | ||
2209 | + spin_lock_init(&adapter->stats_lock); | ||
2210 | + spin_lock_init(&adapter->tx_lock); | ||
2211 | + | ||
2212 | + set_bit(__ATL2_DOWN, &adapter->flags); | ||
2213 | + | ||
2214 | + return 0; | ||
2215 | +} | ||
2216 | + | ||
2217 | +/** | ||
2218 | + * atl2_set_multi - Multicast and Promiscuous mode set | ||
2219 | + * @netdev: network interface device structure | ||
2220 | + * | ||
2221 | + * The set_multi entry point is called whenever the multicast address | ||
2222 | + * list or the network interface flags are updated. This routine is | ||
2223 | + * responsible for configuring the hardware for proper multicast, | ||
2224 | + * promiscuous mode, and all-multi behavior. | ||
2225 | + **/ | ||
2226 | +static void | ||
2227 | +atl2_set_multi(struct net_device *netdev) | ||
2228 | +{ | ||
2229 | + struct atl2_adapter *adapter = netdev_priv(netdev); | ||
2230 | + struct atl2_hw *hw = &adapter->hw; | ||
2231 | + struct dev_mc_list *mc_ptr; | ||
2232 | + u32 rctl; | ||
2233 | + u32 hash_value; | ||
2234 | + | ||
2235 | + /* Check for Promiscuous and All Multicast modes */ | ||
2236 | + rctl = ATL2_READ_REG(hw, REG_MAC_CTRL); | ||
2237 | + | ||
2238 | + if(netdev->flags & IFF_PROMISC) { | ||
2239 | + rctl |= MAC_CTRL_PROMIS_EN; | ||
2240 | + } else if(netdev->flags & IFF_ALLMULTI) { | ||
2241 | + rctl |= MAC_CTRL_MC_ALL_EN; | ||
2242 | + rctl &= ~MAC_CTRL_PROMIS_EN; | ||
2243 | + } else { | ||
2244 | + rctl &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN); | ||
2245 | + } | ||
2246 | + | ||
2247 | + ATL2_WRITE_REG(hw, REG_MAC_CTRL, rctl); | ||
2248 | + | ||
2249 | + /* clear the old settings from the multicast hash table */ | ||
2250 | + ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0); | ||
2251 | + ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0); | ||
2252 | + | ||
2253 | + /* comoute mc addresses' hash value ,and put it into hash table */ | ||
2254 | + for(mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) { | ||
2255 | + hash_value = atl2_hash_mc_addr(hw, mc_ptr->dmi_addr); | ||
2256 | + atl2_hash_set(hw, hash_value); | ||
2257 | + } | ||
2258 | +} | ||
2259 | + | ||
2260 | +static void | ||
2261 | +init_ring_ptrs(struct atl2_adapter *adapter) | ||
2262 | +{ | ||
2263 | + // Read / Write Ptr Initialize: | ||
2264 | + adapter->txd_write_ptr = 0; | ||
2265 | + atomic_set(&adapter->txd_read_ptr, 0); | ||
2266 | + | ||
2267 | + adapter->rxd_read_ptr = 0; | ||
2268 | + adapter->rxd_write_ptr = 0; | ||
2269 | + | ||
2270 | + atomic_set(&adapter->txs_write_ptr, 0); | ||
2271 | + adapter->txs_next_clear = 0; | ||
2272 | +} | ||
2273 | + | ||
2274 | +/** | ||
2275 | + * atl2_configure - Configure Transmit&Receive Unit after Reset | ||
2276 | + * @adapter: board private structure | ||
2277 | + * | ||
2278 | + * Configure the Tx /Rx unit of the MAC after a reset. | ||
2279 | + **/ | ||
2280 | +static int | ||
2281 | +atl2_configure(struct atl2_adapter *adapter) | ||
2282 | +{ | ||
2283 | + struct atl2_hw * hw = &adapter->hw; | ||
2284 | + u32 value; | ||
2285 | + | ||
2286 | + // clear interrupt status | ||
2287 | + ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0xffffffff); | ||
2288 | + | ||
2289 | + // set MAC Address | ||
2290 | + value = (((u32)hw->mac_addr[2]) << 24) | | ||
2291 | + (((u32)hw->mac_addr[3]) << 16) | | ||
2292 | + (((u32)hw->mac_addr[4]) << 8 ) | | ||
2293 | + (((u32)hw->mac_addr[5]) ) ; | ||
2294 | + ATL2_WRITE_REG(hw, REG_MAC_STA_ADDR, value); | ||
2295 | + value = (((u32)hw->mac_addr[0]) << 8 ) | | ||
2296 | + (((u32)hw->mac_addr[1]) ) ; | ||
2297 | + ATL2_WRITE_REG(hw, (REG_MAC_STA_ADDR+4), value); | ||
2298 | + | ||
2299 | + // HI base address | ||
2300 | + ATL2_WRITE_REG(hw, REG_DESC_BASE_ADDR_HI, | ||
2301 | + (u32)((adapter->ring_dma & 0xffffffff00000000ULL) >> 32)); | ||
2302 | + | ||
2303 | + // LO base address | ||
2304 | + ATL2_WRITE_REG(hw, REG_TXD_BASE_ADDR_LO, | ||
2305 | + (u32)(adapter->txd_dma & 0x00000000ffffffffULL)); | ||
2306 | + ATL2_WRITE_REG(hw, REG_TXS_BASE_ADDR_LO, | ||
2307 | + (u32)(adapter->txs_dma & 0x00000000ffffffffULL)); | ||
2308 | + ATL2_WRITE_REG(hw, REG_RXD_BASE_ADDR_LO, | ||
2309 | + (u32)(adapter->rxd_dma & 0x00000000ffffffffULL)); | ||
2310 | + | ||
2311 | + // element count | ||
2312 | + ATL2_WRITE_REGW(hw, REG_TXD_MEM_SIZE, (u16)(adapter->txd_ring_size/4)); | ||
2313 | + ATL2_WRITE_REGW(hw, REG_TXS_MEM_SIZE, (u16)adapter->txs_ring_size); | ||
2314 | + ATL2_WRITE_REGW(hw, REG_RXD_BUF_NUM, (u16)adapter->rxd_ring_size); | ||
2315 | + | ||
2316 | + /* config Internal SRAM */ | ||
2317 | +/* | ||
2318 | + ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_tx_end); | ||
2319 | + ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_rx_end); | ||
2320 | +*/ | ||
2321 | + | ||
2322 | + /* config IPG/IFG */ | ||
2323 | + value = (((u32)hw->ipgt & MAC_IPG_IFG_IPGT_MASK) << MAC_IPG_IFG_IPGT_SHIFT) | | ||
2324 | + (((u32)hw->min_ifg & MAC_IPG_IFG_MIFG_MASK) << MAC_IPG_IFG_MIFG_SHIFT) | | ||
2325 | + (((u32)hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK) << MAC_IPG_IFG_IPGR1_SHIFT)| | ||
2326 | + (((u32)hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK) << MAC_IPG_IFG_IPGR2_SHIFT); | ||
2327 | + ATL2_WRITE_REG(hw, REG_MAC_IPG_IFG, value); | ||
2328 | + | ||
2329 | + /* config Half-Duplex Control */ | ||
2330 | + value = ((u32)hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) | | ||
2331 | + (((u32)hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK) << | ||
2332 | + MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) | | ||
2333 | + MAC_HALF_DUPLX_CTRL_EXC_DEF_EN | | ||
2334 | + (0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) | | ||
2335 | + (((u32)hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK) << | ||
2336 | + MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT); | ||
2337 | + ATL2_WRITE_REG(hw, REG_MAC_HALF_DUPLX_CTRL, value); | ||
2338 | + | ||
2339 | + /* set Interrupt Moderator Timer */ | ||
2340 | + ATL2_WRITE_REGW(hw, REG_IRQ_MODU_TIMER_INIT, adapter->imt); | ||
2341 | + ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_ITIMER_EN); | ||
2342 | + | ||
2343 | + /* set Interrupt Clear Timer */ | ||
2344 | + ATL2_WRITE_REGW(hw, REG_CMBDISDMA_TIMER, adapter->ict); | ||
2345 | + | ||
2346 | + /* set MTU */ | ||
2347 | + ATL2_WRITE_REG(hw, REG_MTU, adapter->netdev->mtu + | ||
2348 | + ENET_HEADER_SIZE + VLAN_SIZE + ETHERNET_FCS_SIZE); | ||
2349 | + | ||
2350 | + /* 1590 */ | ||
2351 | + ATL2_WRITE_REG(hw, REG_TX_CUT_THRESH, 0x177); | ||
2352 | + | ||
2353 | + /* flow control */ | ||
2354 | + ATL2_WRITE_REGW(hw, REG_PAUSE_ON_TH, hw->fc_rxd_hi); | ||
2355 | + ATL2_WRITE_REGW(hw, REG_PAUSE_OFF_TH, hw->fc_rxd_lo); | ||
2356 | + | ||
2357 | + /* Init mailbox */ | ||
2358 | + ATL2_WRITE_REGW(hw, REG_MB_TXD_WR_IDX, (u16)adapter->txd_write_ptr); | ||
2359 | + ATL2_WRITE_REGW(hw, REG_MB_RXD_RD_IDX, (u16)adapter->rxd_read_ptr); | ||
2360 | + | ||
2361 | + /* enable DMA read/write */ | ||
2362 | + ATL2_WRITE_REGB(hw, REG_DMAR, DMAR_EN); | ||
2363 | + ATL2_WRITE_REGB(hw, REG_DMAW, DMAW_EN); | ||
2364 | + | ||
2365 | + value = ATL2_READ_REG(&adapter->hw, REG_ISR); | ||
2366 | + if ((value & ISR_PHY_LINKDOWN) != 0) { | ||
2367 | + value = 1; // config failed | ||
2368 | + } else { | ||
2369 | + value = 0; | ||
2370 | + } | ||
2371 | + | ||
2372 | + // clear all interrupt status | ||
2373 | + ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0x3fffffff); | ||
2374 | + ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0); | ||
2375 | + return value; | ||
2376 | +} | ||
2377 | + | ||
2378 | +/** | ||
2379 | + * atl2_setup_ring_resources - allocate Tx / RX descriptor resources | ||
2380 | + * @adapter: board private structure | ||
2381 | + * | ||
2382 | + * Return 0 on success, negative on failure | ||
2383 | + **/ | ||
2384 | +static s32 | ||
2385 | +atl2_setup_ring_resources(struct atl2_adapter *adapter) | ||
2386 | +{ | ||
2387 | + struct pci_dev *pdev = adapter->pdev; | ||
2388 | + int size; | ||
2389 | + u8 offset = 0; | ||
2390 | + | ||
2391 | + /* real ring DMA buffer */ | ||
2392 | + adapter->ring_size = size = | ||
2393 | + adapter->txd_ring_size * 1 + 7 + // dword align | ||
2394 | + adapter->txs_ring_size * 4 + 7 + // dword align | ||
2395 | + adapter->rxd_ring_size * 1536 + 127; // 128bytes align | ||
2396 | + | ||
2397 | + adapter->ring_vir_addr = pci_alloc_consistent(pdev, size, &adapter->ring_dma); | ||
2398 | + if (!adapter->ring_vir_addr) { | ||
2399 | + return -ENOMEM; | ||
2400 | + } | ||
2401 | +#if 0 | ||
2402 | + if (adapter->pci_using_64) { | ||
2403 | + // test whether HIDWORD dma buffer is not cross boundary | ||
2404 | + if ( ((adapter->ring_dma &0xffffffff00000000ULL)>>32) | ||
2405 | + != (((adapter->ring_dma+size)&0xffffffff00000000ULL)>>32) ) { | ||
2406 | + pci_free_consistent(pdev, adapter->ring_size, adapter->ring_vir_addr, adapter->ring_dma); | ||
2407 | + DEBUGOUT("memory allocated cross 32bit boundary !"); | ||
2408 | + return -ENOMEM; | ||
2409 | + } | ||
2410 | + } | ||
2411 | +#endif | ||
2412 | + memset(adapter->ring_vir_addr, 0, adapter->ring_size); | ||
2413 | + | ||
2414 | + // Init TXD Ring | ||
2415 | + adapter->txd_dma = adapter->ring_dma ; | ||
2416 | + offset = (adapter->txd_dma & 0x7) ? (8 - (adapter->txd_dma & 0x7)) : 0; | ||
2417 | + adapter->txd_dma += offset; | ||
2418 | + adapter->txd_ring = (tx_pkt_header_t*) (adapter->ring_vir_addr + offset); | ||
2419 | + | ||
2420 | + // Init TXS Ring | ||
2421 | + adapter->txs_dma = adapter->txd_dma + adapter->txd_ring_size; | ||
2422 | + offset = (adapter->txs_dma & 0x7) ? (8- (adapter->txs_dma & 0x7)) : 0; | ||
2423 | + adapter->txs_dma += offset; | ||
2424 | + adapter->txs_ring = (tx_pkt_status_t*) | ||
2425 | + (((u8*)adapter->txd_ring) + (adapter->txd_ring_size+offset)); | ||
2426 | + | ||
2427 | + // Init RXD Ring | ||
2428 | + adapter->rxd_dma = adapter->txs_dma + adapter->txs_ring_size*4; | ||
2429 | + offset = (adapter->rxd_dma & 127) ? (128 - (adapter->rxd_dma & 127)) : 0; | ||
2430 | + if (offset > 7) { | ||
2431 | + offset -= 8; | ||
2432 | + } else { | ||
2433 | + offset += (128 - 8); | ||
2434 | + } | ||
2435 | + adapter->rxd_dma += offset; | ||
2436 | + adapter->rxd_ring = (rx_desc_t*) (((u8*)adapter->txs_ring) + | ||
2437 | + (adapter->txs_ring_size*4 + offset)); | ||
2438 | + | ||
2439 | +// Read / Write Ptr Initialize: | ||
2440 | +// init_ring_ptrs(adapter); | ||
2441 | + | ||
2442 | + return ATL2_SUCCESS; | ||
2443 | +} | ||
2444 | + | ||
2445 | +/** | ||
2446 | + * atl2_irq_enable - Enable default interrupt generation settings | ||
2447 | + * @adapter: board private structure | ||
2448 | + **/ | ||
2449 | +static inline void | ||
2450 | +atl2_irq_enable(struct atl2_adapter *adapter) | ||
2451 | +{ | ||
2452 | + ATL2_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK); | ||
2453 | + ATL2_WRITE_FLUSH(&adapter->hw); | ||
2454 | +} | ||
2455 | + | ||
2456 | +/** | ||
2457 | + * atl2_irq_disable - Mask off interrupt generation on the NIC | ||
2458 | + * @adapter: board private structure | ||
2459 | + **/ | ||
2460 | +static inline void | ||
2461 | +atl2_irq_disable(struct atl2_adapter *adapter) | ||
2462 | +{ | ||
2463 | + ATL2_WRITE_REG(&adapter->hw, REG_IMR, 0); | ||
2464 | + ATL2_WRITE_FLUSH(&adapter->hw); | ||
2465 | + synchronize_irq(adapter->pdev->irq); | ||
2466 | +} | ||
2467 | + | ||
2468 | +#ifdef NETIF_F_HW_VLAN_TX | ||
2469 | +static void | ||
2470 | +atl2_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp) | ||
2471 | +{ | ||
2472 | + struct atl2_adapter *adapter = netdev_priv(netdev); | ||
2473 | + u32 ctrl; | ||
2474 | + | ||
2475 | + atl2_irq_disable(adapter); | ||
2476 | + adapter->vlgrp = grp; | ||
2477 | + | ||
2478 | + if(grp) { | ||
2479 | + /* enable VLAN tag insert/strip */ | ||
2480 | + ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL); | ||
2481 | + ctrl |= MAC_CTRL_RMV_VLAN; | ||
2482 | + ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl); | ||
2483 | + } else { | ||
2484 | + /* disable VLAN tag insert/strip */ | ||
2485 | + ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL); | ||
2486 | + ctrl &= ~MAC_CTRL_RMV_VLAN; | ||
2487 | + ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl); | ||
2488 | + } | ||
2489 | + | ||
2490 | + atl2_irq_enable(adapter); | ||
2491 | +} | ||
2492 | + | ||
2493 | +static void | ||
2494 | +atl2_restore_vlan(struct atl2_adapter *adapter) | ||
2495 | +{ | ||
2496 | + atl2_vlan_rx_register(adapter->netdev, adapter->vlgrp); | ||
2497 | +} | ||
2498 | +#endif | ||
2499 | + | ||
2500 | +static void | ||
2501 | +atl2_intr_rx(struct atl2_adapter* adapter) | ||
2502 | +{ | ||
2503 | + struct net_device *netdev = adapter->netdev; | ||
2504 | + rx_desc_t* rxd; | ||
2505 | + struct sk_buff* skb; | ||
2506 | + | ||
2507 | + do { | ||
2508 | + rxd = adapter->rxd_ring+adapter->rxd_write_ptr; | ||
2509 | + if (!rxd->status.update) | ||
2510 | + break; // end of tx | ||
2511 | + | ||
2512 | + // clear this flag at once | ||
2513 | + rxd->status.update = 0; | ||
2514 | + | ||
2515 | + if (rxd->status.ok && rxd->status.pkt_size >= 60) { | ||
2516 | + int rx_size = (int)(rxd->status.pkt_size - 4); | ||
2517 | + // alloc new buffer | ||
2518 | + skb = netdev_alloc_skb(netdev, rx_size + NET_IP_ALIGN); | ||
2519 | + if (NULL == skb) { | ||
2520 | + printk(KERN_WARNING"%s: Memory squeeze, deferring packet.\n", | ||
2521 | + netdev->name); | ||
2522 | + /* We should check that some rx space is free. | ||
2523 | + * If not, free one and mark stats->rx_dropped++. */ | ||
2524 | + adapter->net_stats.rx_dropped++; | ||
2525 | + break; | ||
2526 | + } | ||
2527 | +/* FIXME: ??? | ||
2528 | + if (rx_size > 1400) { | ||
2529 | + int s,c; | ||
2530 | + c = 0; | ||
2531 | + printk("rx_size= %d\n", rx_size); | ||
2532 | + for (s=0; s < 800; s++) { | ||
2533 | + if (0 == c) { | ||
2534 | + printk("%04x ", s); | ||
2535 | + } | ||
2536 | + printk("%02x ", rxd->packet[s]); | ||
2537 | + if (++c == 16) { | ||
2538 | + c = 0; | ||
2539 | + printk("\n"); | ||
2540 | + } | ||
2541 | + } | ||
2542 | + printk(KERN_WARNING"\n"); | ||
2543 | + } | ||
2544 | +*/ | ||
2545 | + skb_reserve(skb, NET_IP_ALIGN); | ||
2546 | + skb->dev = netdev; | ||
2547 | +/* gone in 2.6.23, just use memcpy? -- CHS | ||
2548 | + eth_copy_and_sum(skb, rxd->packet, rx_size, 0); */ | ||
2549 | + memcpy(skb->data, rxd->packet, rx_size); /* totally untested -- CHS */ | ||
2550 | + skb_put(skb, rx_size); | ||
2551 | + /* FIXME ??? | ||
2552 | + memcpy(skb_put(skb, rx_size), | ||
2553 | + rxd->packet, | ||
2554 | + rx_size); | ||
2555 | + */ | ||
2556 | + skb->protocol = eth_type_trans(skb, netdev); | ||
2557 | +#ifdef NETIF_F_HW_VLAN_TX | ||
2558 | + if(adapter->vlgrp && (rxd->status.vlan)) { | ||
2559 | + u16 vlan_tag = (rxd->status.vtag>>4) | | ||
2560 | + ((rxd->status.vtag&7) << 13) | | ||
2561 | + ((rxd->status.vtag&8) << 9); | ||
2562 | + vlan_hwaccel_rx(skb, adapter->vlgrp, vlan_tag); | ||
2563 | + } else | ||
2564 | +#endif | ||
2565 | + netif_rx(skb); | ||
2566 | + adapter->net_stats.rx_bytes += rx_size; | ||
2567 | + adapter->net_stats.rx_packets++; | ||
2568 | + netdev->last_rx = jiffies; | ||
2569 | + } else { | ||
2570 | + adapter->net_stats.rx_errors++; | ||
2571 | + | ||
2572 | + if (rxd->status.ok && rxd->status.pkt_size <= 60) { | ||
2573 | + adapter->net_stats.rx_length_errors++; | ||
2574 | + } | ||
2575 | + if (rxd->status.mcast) adapter->net_stats.multicast++; | ||
2576 | + if (rxd->status.crc) adapter->net_stats.rx_crc_errors++; | ||
2577 | + if (rxd->status.align) adapter->net_stats.rx_frame_errors++; | ||
2578 | + } | ||
2579 | + | ||
2580 | + // advance write ptr | ||
2581 | + if (++adapter->rxd_write_ptr == adapter->rxd_ring_size) | ||
2582 | + adapter->rxd_write_ptr = 0; | ||
2583 | + } while (1); | ||
2584 | + | ||
2585 | + // update mailbox ? | ||
2586 | + adapter->rxd_read_ptr = adapter->rxd_write_ptr; | ||
2587 | + ATL2_WRITE_REGW(&adapter->hw, REG_MB_RXD_RD_IDX, adapter->rxd_read_ptr); | ||
2588 | +} | ||
2589 | + | ||
2590 | +static void | ||
2591 | +atl2_intr_tx(struct atl2_adapter* adapter) | ||
2592 | +{ | ||
2593 | + u32 txd_read_ptr; | ||
2594 | + u32 txs_write_ptr; | ||
2595 | + tx_pkt_status_t* txs; | ||
2596 | + tx_pkt_header_t* txph; | ||
2597 | + int free_hole = 0; | ||
2598 | + | ||
2599 | + do { | ||
2600 | + txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr); | ||
2601 | + txs = adapter->txs_ring + txs_write_ptr; | ||
2602 | + if (!txs->update) | ||
2603 | + break; // tx stop here | ||
2604 | + | ||
2605 | + free_hole = 1; | ||
2606 | + txs->update = 0; | ||
2607 | + | ||
2608 | + if (++txs_write_ptr == adapter->txs_ring_size) | ||
2609 | + txs_write_ptr = 0; | ||
2610 | + atomic_set(&adapter->txs_write_ptr, (int)txs_write_ptr); | ||
2611 | + | ||
2612 | + txd_read_ptr = (u32) atomic_read(&adapter->txd_read_ptr); | ||
2613 | + txph = (tx_pkt_header_t*) (((u8*)adapter->txd_ring) + txd_read_ptr); | ||
2614 | + | ||
2615 | + if ( txph->pkt_size != txs->pkt_size) { | ||
2616 | + tx_pkt_status_t* old_txs = txs; | ||
2617 | + printk(KERN_WARNING | ||
2618 | + "%s: txs packet size do not coinsist with txd" | ||
2619 | + " txd_:0x%08x, txs_:0x%08x!\n", | ||
2620 | + adapter->netdev->name, | ||
2621 | + *(u32*)txph, *(u32*)txs); | ||
2622 | + printk(KERN_WARNING | ||
2623 | + "txd read ptr: 0x%x\n", | ||
2624 | + txd_read_ptr); | ||
2625 | + txs = adapter->txs_ring + txs_write_ptr; | ||
2626 | + printk(KERN_WARNING | ||
2627 | + "txs-behind:0x%08x\n", | ||
2628 | + *(u32*)txs); | ||
2629 | + if (txs_write_ptr < 2) { | ||
2630 | + txs = adapter->txs_ring + | ||
2631 | + (adapter->txs_ring_size + | ||
2632 | + txs_write_ptr - 2); | ||
2633 | + } else { | ||
2634 | + txs = adapter->txs_ring + (txs_write_ptr - 2); | ||
2635 | + } | ||
2636 | + printk(KERN_WARNING | ||
2637 | + "txs-before:0x%08x\n", | ||
2638 | + *(u32*)txs); | ||
2639 | + txs = old_txs; | ||
2640 | + } | ||
2641 | + | ||
2642 | + txd_read_ptr += (((u32)(txph->pkt_size)+7)& ~3);//4for TPH | ||
2643 | + if (txd_read_ptr >= adapter->txd_ring_size) | ||
2644 | + txd_read_ptr -= adapter->txd_ring_size; | ||
2645 | + | ||
2646 | + atomic_set(&adapter->txd_read_ptr, (int)txd_read_ptr); | ||
2647 | + | ||
2648 | + // tx statistics: | ||
2649 | + if (txs->ok) | ||
2650 | + adapter->net_stats.tx_packets++; | ||
2651 | + else | ||
2652 | + adapter->net_stats.tx_errors++; | ||
2653 | + | ||
2654 | + if (txs->defer) adapter->net_stats.collisions++; | ||
2655 | + if (txs->abort_col) adapter->net_stats.tx_aborted_errors++; | ||
2656 | + if (txs->late_col) adapter->net_stats.tx_window_errors++; | ||
2657 | + if (txs->underun) adapter->net_stats.tx_fifo_errors++; | ||
2658 | + } while (1); | ||
2659 | + | ||
2660 | + if (free_hole) { | ||
2661 | + if(netif_queue_stopped(adapter->netdev) && | ||
2662 | + netif_carrier_ok(adapter->netdev)) | ||
2663 | + netif_wake_queue(adapter->netdev); | ||
2664 | + } | ||
2665 | +} | ||
2666 | + | ||
2667 | +static void | ||
2668 | +atl2_check_for_link(struct atl2_adapter* adapter) | ||
2669 | +{ | ||
2670 | + struct net_device *netdev = adapter->netdev; | ||
2671 | + u16 phy_data = 0; | ||
2672 | + | ||
2673 | + spin_lock(&adapter->stats_lock); | ||
2674 | + atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data); | ||
2675 | + atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data); | ||
2676 | + spin_unlock(&adapter->stats_lock); | ||
2677 | + | ||
2678 | + // notify upper layer link down ASAP | ||
2679 | + if (!(phy_data & BMSR_LSTATUS)) { // Link Down | ||
2680 | + if (netif_carrier_ok(netdev)) { // old link state: Up | ||
2681 | + printk(KERN_INFO "%s: %s NIC Link is Down\n", | ||
2682 | + atl2_driver_name, netdev->name); | ||
2683 | + adapter->link_speed = SPEED_0; | ||
2684 | + netif_carrier_off(netdev); | ||
2685 | + netif_stop_queue(netdev); | ||
2686 | + } | ||
2687 | + } | ||
2688 | + schedule_work(&adapter->link_chg_task); | ||
2689 | +} | ||
2690 | + | ||
2691 | +static inline void | ||
2692 | +atl2_clear_phy_int(struct atl2_adapter *adapter) | ||
2693 | +{ | ||
2694 | + u16 phy_data; | ||
2695 | + spin_lock(&adapter->stats_lock); | ||
2696 | + atl2_read_phy_reg(&adapter->hw, 19, &phy_data); | ||
2697 | + spin_unlock(&adapter->stats_lock); | ||
2698 | +} | ||
2699 | + | ||
2700 | +/** | ||
2701 | + * atl2_intr - Interrupt Handler | ||
2702 | + * @irq: interrupt number | ||
2703 | + * @data: pointer to a network interface device structure | ||
2704 | + * @pt_regs: CPU registers structure | ||
2705 | + **/ | ||
2706 | +static irqreturn_t | ||
2707 | +atl2_intr(int irq, void *data) | ||
2708 | +{ | ||
2709 | + struct atl2_adapter *adapter = netdev_priv(data); | ||
2710 | + struct atl2_hw *hw = &adapter->hw; | ||
2711 | + u32 status; | ||
2712 | + | ||
2713 | + status = ATL2_READ_REG(hw, REG_ISR); | ||
2714 | + if (0 == status) | ||
2715 | + return IRQ_NONE; | ||
2716 | + | ||
2717 | + // link event | ||
2718 | + if (status & ISR_PHY) { | ||
2719 | + atl2_clear_phy_int(adapter); | ||
2720 | + } | ||
2721 | + | ||
2722 | + // clear ISR status, and Enable CMB DMA/Disable Interrupt | ||
2723 | + ATL2_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT); | ||
2724 | + | ||
2725 | + // FIXME: if PCIe link is down, how did we read the register? -- CHS | ||
2726 | + // check if PCIE PHY Link down | ||
2727 | + if (status & ISR_PHY_LINKDOWN) { | ||
2728 | + if(netif_running(adapter->netdev)) { // reset MAC | ||
2729 | + ATL2_WRITE_REG(hw, REG_ISR, 0); | ||
2730 | + ATL2_WRITE_REG(hw, REG_IMR, 0); | ||
2731 | + ATL2_WRITE_FLUSH(hw); | ||
2732 | + schedule_work(&adapter->reset_task); | ||
2733 | + return IRQ_HANDLED; | ||
2734 | + } | ||
2735 | + } | ||
2736 | + | ||
2737 | + // check if DMA read/write error ? | ||
2738 | + if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) | ||
2739 | + { | ||
2740 | + //ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, MASTER_CTRL_SOFT_RST); | ||
2741 | + ATL2_WRITE_REG(hw, REG_ISR, 0); | ||
2742 | + ATL2_WRITE_REG(hw, REG_IMR, 0); | ||
2743 | + ATL2_WRITE_FLUSH(hw); | ||
2744 | + schedule_work(&adapter->reset_task); | ||
2745 | + return IRQ_HANDLED; | ||
2746 | + } | ||
2747 | + | ||
2748 | + // link event | ||
2749 | + if (status & (ISR_PHY | ISR_MANUAL)) | ||
2750 | + { | ||
2751 | + adapter->net_stats.tx_carrier_errors++; | ||
2752 | + atl2_check_for_link(adapter); | ||
2753 | + } | ||
2754 | + | ||
2755 | + // transmit event | ||
2756 | + if (status & ISR_TX_EVENT) { | ||
2757 | + atl2_intr_tx(adapter); | ||
2758 | + } | ||
2759 | + | ||
2760 | + // rx exception | ||
2761 | + if (status & ISR_RX_EVENT) { | ||
2762 | + atl2_intr_rx(adapter); | ||
2763 | + } | ||
2764 | + | ||
2765 | + // re-enable Interrupt | ||
2766 | + ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0); | ||
2767 | + return IRQ_HANDLED; | ||
2768 | +} | ||
2769 | + | ||
2770 | +static int | ||
2771 | +atl2_request_irq(struct atl2_adapter *adapter) | ||
2772 | +{ | ||
2773 | + struct net_device *netdev = adapter->netdev; | ||
2774 | + int flags, err = 0; | ||
2775 | + | ||
2776 | + flags = IRQF_SHARED; | ||
2777 | +#ifdef CONFIG_PCI_MSI | ||
2778 | + adapter->have_msi = true; | ||
2779 | + if ((err = pci_enable_msi(adapter->pdev))) | ||
2780 | + adapter->have_msi = false; | ||
2781 | + | ||
2782 | + if (adapter->have_msi) | ||
2783 | + flags &= ~IRQF_SHARED; | ||
2784 | +#endif | ||
2785 | + | ||
2786 | + return request_irq(adapter->pdev->irq, &atl2_intr, flags, netdev->name, netdev); | ||
2787 | +} | ||
2788 | + | ||
2789 | +/** | ||
2790 | + * atl2_free_ring_resources - Free Tx / RX descriptor Resources | ||
2791 | + * @adapter: board private structure | ||
2792 | + * | ||
2793 | + * Free all transmit software resources | ||
2794 | + **/ | ||
2795 | +static void | ||
2796 | +atl2_free_ring_resources(struct atl2_adapter *adapter) | ||
2797 | +{ | ||
2798 | + struct pci_dev *pdev = adapter->pdev; | ||
2799 | + pci_free_consistent(pdev, adapter->ring_size, adapter->ring_vir_addr, adapter->ring_dma); | ||
2800 | +} | ||
2801 | + | ||
2802 | +/** | ||
2803 | + * atl2_open - Called when a network interface is made active | ||
2804 | + * @netdev: network interface device structure | ||
2805 | + * | ||
2806 | + * Returns 0 on success, negative value on failure | ||
2807 | + * | ||
2808 | + * The open entry point is called when a network interface is made | ||
2809 | + * active by the system (IFF_UP). At this point all resources needed | ||
2810 | + * for transmit and receive operations are allocated, the interrupt | ||
2811 | + * handler is registered with the OS, the watchdog timer is started, | ||
2812 | + * and the stack is notified that the interface is ready. | ||
2813 | + **/ | ||
2814 | +static int | ||
2815 | +atl2_open(struct net_device *netdev) | ||
2816 | +{ | ||
2817 | + struct atl2_adapter *adapter = netdev_priv(netdev); | ||
2818 | + int err; | ||
2819 | + u32 val; | ||
2820 | + | ||
2821 | + /* disallow open during test */ | ||
2822 | + if (test_bit(__ATL2_TESTING, &adapter->flags)) | ||
2823 | + return -EBUSY; | ||
2824 | + | ||
2825 | + /* allocate transmit descriptors */ | ||
2826 | + if((err = atl2_setup_ring_resources(adapter))) | ||
2827 | + return err; | ||
2828 | + | ||
2829 | + if((err = atl2_init_hw(&adapter->hw))) { | ||
2830 | + err = -EIO; | ||
2831 | + goto err_init_hw; | ||
2832 | + } | ||
2833 | + | ||
2834 | + /* hardware has been reset, we need to reload some things */ | ||
2835 | + atl2_set_multi(netdev); | ||
2836 | + init_ring_ptrs(adapter); | ||
2837 | + | ||
2838 | +#ifdef NETIF_F_HW_VLAN_TX | ||
2839 | + atl2_restore_vlan(adapter); | ||
2840 | +#endif | ||
2841 | + | ||
2842 | + if (atl2_configure(adapter)) { | ||
2843 | + err = -EIO; | ||
2844 | + goto err_config; | ||
2845 | + } | ||
2846 | + | ||
2847 | + if ((err = atl2_request_irq(adapter))) | ||
2848 | + goto err_req_irq; | ||
2849 | + | ||
2850 | + clear_bit(__ATL2_DOWN, &adapter->flags); | ||
2851 | + | ||
2852 | + mod_timer(&adapter->watchdog_timer, jiffies + 4*HZ); | ||
2853 | + | ||
2854 | + val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL); | ||
2855 | + ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, val | MASTER_CTRL_MANUAL_INT); | ||
2856 | + | ||
2857 | + atl2_irq_enable(adapter); | ||
2858 | + | ||
2859 | + return 0; | ||
2860 | + | ||
2861 | +err_init_hw: | ||
2862 | +err_req_irq: | ||
2863 | +err_config: | ||
2864 | + atl2_free_ring_resources(adapter); | ||
2865 | + atl2_reset_hw(&adapter->hw); | ||
2866 | + | ||
2867 | + return err; | ||
2868 | +} | ||
2869 | + | ||
2870 | +void | ||
2871 | +atl2_down(struct atl2_adapter *adapter) | ||
2872 | +{ | ||
2873 | + struct net_device *netdev = adapter->netdev; | ||
2874 | + | ||
2875 | + /* signal that we're down so the interrupt handler does not | ||
2876 | + * reschedule our watchdog timer */ | ||
2877 | + set_bit(__ATL2_DOWN, &adapter->flags); | ||
2878 | + | ||
2879 | +#ifdef NETIF_F_LLTX | ||
2880 | + netif_stop_queue(netdev); | ||
2881 | +#else | ||
2882 | + netif_tx_disable(netdev); | ||
2883 | +#endif | ||
2884 | + | ||
2885 | + /* reset MAC to disable all RX/TX */ | ||
2886 | + atl2_reset_hw(&adapter->hw); | ||
2887 | + msleep(1); | ||
2888 | + | ||
2889 | + atl2_irq_disable(adapter); | ||
2890 | + | ||
2891 | + del_timer_sync(&adapter->watchdog_timer); | ||
2892 | + del_timer_sync(&adapter->phy_config_timer); | ||
2893 | + clear_bit(0, &adapter->cfg_phy); | ||
2894 | + | ||
2895 | + netif_carrier_off(netdev); | ||
2896 | + adapter->link_speed = SPEED_0; | ||
2897 | + adapter->link_duplex = -1; | ||
2898 | + | ||
2899 | +// atl2_reset(adapter); | ||
2900 | +} | ||
2901 | + | ||
2902 | +static void | ||
2903 | +atl2_free_irq(struct atl2_adapter *adapter) | ||
2904 | +{ | ||
2905 | + struct net_device *netdev = adapter->netdev; | ||
2906 | + | ||
2907 | + free_irq(adapter->pdev->irq, netdev); | ||
2908 | + | ||
2909 | +#ifdef CONFIG_PCI_MSI | ||
2910 | + if (adapter->have_msi) | ||
2911 | + pci_disable_msi(adapter->pdev); | ||
2912 | +#endif | ||
2913 | +} | ||
2914 | + | ||
2915 | +/** | ||
2916 | + * atl2_close - Disables a network interface | ||
2917 | + * @netdev: network interface device structure | ||
2918 | + * | ||
2919 | + * Returns 0, this is not allowed to fail | ||
2920 | + * | ||
2921 | + * The close entry point is called when an interface is de-activated | ||
2922 | + * by the OS. The hardware is still under the drivers control, but | ||
2923 | + * needs to be disabled. A global MAC reset is issued to stop the | ||
2924 | + * hardware, and all transmit and receive resources are freed. | ||
2925 | + **/ | ||
2926 | +static int | ||
2927 | +atl2_close(struct net_device *netdev) | ||
2928 | +{ | ||
2929 | + struct atl2_adapter *adapter = netdev_priv(netdev); | ||
2930 | + | ||
2931 | + WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags)); | ||
2932 | + | ||
2933 | + atl2_down(adapter); | ||
2934 | + atl2_free_irq(adapter); | ||
2935 | + atl2_free_ring_resources(adapter); | ||
2936 | + | ||
2937 | + return 0; | ||
2938 | +} | ||
2939 | + | ||
2940 | +static inline int | ||
2941 | +TxsFreeUnit(struct atl2_adapter *adapter) | ||
2942 | +{ | ||
2943 | + u32 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr); | ||
2944 | + | ||
2945 | + return (adapter->txs_next_clear >= txs_write_ptr) ? | ||
2946 | + (int) (adapter->txs_ring_size - adapter->txs_next_clear + | ||
2947 | + txs_write_ptr - 1) : | ||
2948 | + (int) (txs_write_ptr - adapter->txs_next_clear - 1); | ||
2949 | +} | ||
2950 | + | ||
2951 | +static inline int | ||
2952 | +TxdFreeBytes(struct atl2_adapter *adapter) | ||
2953 | +{ | ||
2954 | + u32 txd_read_ptr = (u32)atomic_read(&adapter->txd_read_ptr); | ||
2955 | + | ||
2956 | + return (adapter->txd_write_ptr >= txd_read_ptr) ? | ||
2957 | + (int) (adapter->txd_ring_size - adapter->txd_write_ptr + | ||
2958 | + txd_read_ptr - 1): | ||
2959 | + (int) (txd_read_ptr - adapter->txd_write_ptr - 1); | ||
2960 | +} | ||
2961 | + | ||
2962 | +static int | ||
2963 | +atl2_xmit_frame(struct sk_buff *skb, struct net_device *netdev) | ||
2964 | +{ | ||
2965 | + struct atl2_adapter *adapter = netdev_priv(netdev); | ||
2966 | + unsigned long flags; | ||
2967 | + tx_pkt_header_t* txph; | ||
2968 | + u32 offset, copy_len; | ||
2969 | + int txs_unused; | ||
2970 | + int txbuf_unused; | ||
2971 | + | ||
2972 | + if (test_bit(__ATL2_DOWN, &adapter->flags)) { | ||
2973 | + dev_kfree_skb_any(skb); | ||
2974 | + return NETDEV_TX_OK; | ||
2975 | + } | ||
2976 | + | ||
2977 | + if (unlikely(skb->len <= 0)) { | ||
2978 | + dev_kfree_skb_any(skb); | ||
2979 | + return NETDEV_TX_OK; | ||
2980 | + } | ||
2981 | + | ||
2982 | +#ifdef NETIF_F_LLTX | ||
2983 | + local_irq_save(flags); | ||
2984 | + if (!spin_trylock(&adapter->tx_lock)) { | ||
2985 | + /* Collision - tell upper layer to requeue */ | ||
2986 | + local_irq_restore(flags); | ||
2987 | + return NETDEV_TX_LOCKED; | ||
2988 | + } | ||
2989 | +#else | ||
2990 | + spin_lock_irqsave(&adapter->tx_lock, flags); | ||
2991 | +#endif | ||
2992 | + txs_unused = TxsFreeUnit(adapter); | ||
2993 | + txbuf_unused = TxdFreeBytes(adapter); | ||
2994 | + | ||
2995 | + if (txs_unused < 1 || skb->len > txbuf_unused) { | ||
2996 | + // no enough resource | ||
2997 | + netif_stop_queue(netdev); | ||
2998 | + spin_unlock_irqrestore(&adapter->tx_lock, flags); | ||
2999 | + return NETDEV_TX_BUSY; | ||
3000 | + } | ||
3001 | + | ||
3002 | + offset = adapter->txd_write_ptr; | ||
3003 | + | ||
3004 | + txph = (tx_pkt_header_t*) (((u8*)adapter->txd_ring)+offset); | ||
3005 | + | ||
3006 | + *(u32*)txph = 0; | ||
3007 | + txph->pkt_size = skb->len; | ||
3008 | + | ||
3009 | + offset += 4; | ||
3010 | + if (offset >= adapter->txd_ring_size) | ||
3011 | + offset -= adapter->txd_ring_size; | ||
3012 | + copy_len = adapter->txd_ring_size - offset; | ||
3013 | + if (copy_len >= skb->len) { | ||
3014 | + memcpy(((u8*)adapter->txd_ring)+offset, skb->data, skb->len); | ||
3015 | + offset += ((u32)(skb->len+3)&~3); | ||
3016 | + } else { | ||
3017 | + memcpy(((u8*)adapter->txd_ring)+offset, skb->data, copy_len); | ||
3018 | + memcpy((u8*)adapter->txd_ring, skb->data+copy_len, skb->len-copy_len); | ||
3019 | + offset = ((u32)(skb->len-copy_len+3)&~3); | ||
3020 | + } | ||
3021 | +#ifdef NETIF_F_HW_VLAN_TX | ||
3022 | + if (adapter->vlgrp && vlan_tx_tag_present(skb)) { | ||
3023 | + u16 vlan_tag = vlan_tx_tag_get(skb); | ||
3024 | + vlan_tag = (vlan_tag << 4) | | ||
3025 | + (vlan_tag >> 13) | | ||
3026 | + ((vlan_tag >>9) & 0x8); | ||
3027 | + txph->ins_vlan = 1; | ||
3028 | + txph->vlan = vlan_tag; | ||
3029 | + } | ||
3030 | +#endif | ||
3031 | + if (offset >= adapter->txd_ring_size) | ||
3032 | + offset -= adapter->txd_ring_size; | ||
3033 | + adapter->txd_write_ptr = offset; | ||
3034 | + | ||
3035 | + // clear txs before send | ||
3036 | + adapter->txs_ring[adapter->txs_next_clear].update = 0; | ||
3037 | + if (++adapter->txs_next_clear == adapter->txs_ring_size) | ||
3038 | + adapter->txs_next_clear = 0; | ||
3039 | + | ||
3040 | + ATL2_WRITE_REGW(&adapter->hw, REG_MB_TXD_WR_IDX, (adapter->txd_write_ptr >> 2)); | ||
3041 | + | ||
3042 | + spin_unlock_irqrestore(&adapter->tx_lock, flags); | ||
3043 | + | ||
3044 | + netdev->trans_start = jiffies; | ||
3045 | + dev_kfree_skb_any(skb); | ||
3046 | + return NETDEV_TX_OK; | ||
3047 | +} | ||
3048 | + | ||
3049 | +/** | ||
3050 | + * atl2_get_stats - Get System Network Statistics | ||
3051 | + * @netdev: network interface device structure | ||
3052 | + * | ||
3053 | + * Returns the address of the device statistics structure. | ||
3054 | + * The statistics are actually updated from the timer callback. | ||
3055 | + **/ | ||
3056 | +static struct net_device_stats * | ||
3057 | +atl2_get_stats(struct net_device *netdev) | ||
3058 | +{ | ||
3059 | + struct atl2_adapter *adapter = netdev_priv(netdev); | ||
3060 | + | ||
3061 | + return &adapter->net_stats; | ||
3062 | +} | ||
3063 | + | ||
3064 | +/** | ||
3065 | + * atl2_change_mtu - Change the Maximum Transfer Unit | ||
3066 | + * @netdev: network interface device structure | ||
3067 | + * @new_mtu: new value for maximum frame size | ||
3068 | + * | ||
3069 | + * Returns 0 on success, negative on failure | ||
3070 | + **/ | ||
3071 | +static int | ||
3072 | +atl2_change_mtu(struct net_device *netdev, int new_mtu) | ||
3073 | +{ | ||
3074 | + struct atl2_adapter *adapter = netdev_priv(netdev); | ||
3075 | + struct atl2_hw *hw = &adapter->hw; | ||
3076 | + | ||
3077 | + if ((new_mtu < 40) || (new_mtu > (ETH_DATA_LEN + VLAN_SIZE))) | ||
3078 | + return -EINVAL; | ||
3079 | + | ||
3080 | + /* set MTU */ | ||
3081 | + if (hw->max_frame_size != new_mtu) { | ||
3082 | +// while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags)) | ||
3083 | +// msleep(1); | ||
3084 | + netdev->mtu = new_mtu; | ||
3085 | + | ||
3086 | + ATL2_WRITE_REG(hw, REG_MTU, | ||
3087 | + new_mtu + ENET_HEADER_SIZE + VLAN_SIZE + ETHERNET_FCS_SIZE); | ||
3088 | +// clear_bit(__ATL2_RESETTING, &adapter->flags); | ||
3089 | + } | ||
3090 | + | ||
3091 | + return 0; | ||
3092 | +} | ||
3093 | + | ||
3094 | +/** | ||
3095 | + * atl2_set_mac - Change the Ethernet Address of the NIC | ||
3096 | + * @netdev: network interface device structure | ||
3097 | + * @p: pointer to an address structure | ||
3098 | + * | ||
3099 | + * Returns 0 on success, negative on failure | ||
3100 | + **/ | ||
3101 | +static int | ||
3102 | +atl2_set_mac(struct net_device *netdev, void *p) | ||
3103 | +{ | ||
3104 | + struct atl2_adapter *adapter = netdev_priv(netdev); | ||
3105 | + struct sockaddr *addr = p; | ||
3106 | + | ||
3107 | + if (!is_valid_ether_addr(addr->sa_data)) | ||
3108 | + return -EADDRNOTAVAIL; | ||
3109 | + | ||
3110 | + if (netif_running(netdev)) | ||
3111 | + return -EBUSY; | ||
3112 | + | ||
3113 | + memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | ||
3114 | + memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len); | ||
3115 | + | ||
3116 | + atl2_set_mac_addr(&adapter->hw); | ||
3117 | + | ||
3118 | + return 0; | ||
3119 | +} | ||
3120 | + | ||
3121 | +/** | ||
3122 | + * atl2_mii_ioctl - | ||
3123 | + * @netdev: | ||
3124 | + * @ifreq: | ||
3125 | + * @cmd: | ||
3126 | + **/ | ||
3127 | +static int | ||
3128 | +atl2_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) | ||
3129 | +{ | ||
3130 | + struct atl2_adapter *adapter = netdev_priv(netdev); | ||
3131 | + struct mii_ioctl_data *data = if_mii(ifr); | ||
3132 | + unsigned long flags; | ||
3133 | + | ||
3134 | + switch (cmd) { | ||
3135 | + case SIOCGMIIPHY: | ||
3136 | + data->phy_id = 0; | ||
3137 | + break; | ||
3138 | + case SIOCGMIIREG: | ||
3139 | + if (!capable(CAP_NET_ADMIN)) | ||
3140 | + return -EPERM; | ||
3141 | + spin_lock_irqsave(&adapter->stats_lock, flags); | ||
3142 | + if (atl2_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, &data->val_out)) { | ||
3143 | + spin_unlock_irqrestore(&adapter->stats_lock, flags); | ||
3144 | + return -EIO; | ||
3145 | + } | ||
3146 | + spin_unlock_irqrestore(&adapter->stats_lock, flags); | ||
3147 | + break; | ||
3148 | + case SIOCSMIIREG: | ||
3149 | + if (!capable(CAP_NET_ADMIN)) | ||
3150 | + return -EPERM; | ||
3151 | + if (data->reg_num & ~(0x1F)) | ||
3152 | + return -EFAULT; | ||
3153 | + spin_lock_irqsave(&adapter->stats_lock, flags); | ||
3154 | + if (atl2_write_phy_reg(&adapter->hw, data->reg_num, data->val_in)) { | ||
3155 | + spin_unlock_irqrestore(&adapter->stats_lock, flags); | ||
3156 | + return -EIO; | ||
3157 | + } | ||
3158 | + spin_unlock_irqrestore(&adapter->stats_lock, flags); | ||
3159 | + break; | ||
3160 | + default: | ||
3161 | + return -EOPNOTSUPP; | ||
3162 | + } | ||
3163 | + return ATL2_SUCCESS; | ||
3164 | +} | ||
3165 | + | ||
3166 | +/** | ||
3167 | + * atl2_ioctl - | ||
3168 | + * @netdev: | ||
3169 | + * @ifreq: | ||
3170 | + * @cmd: | ||
3171 | + **/ | ||
3172 | +static int | ||
3173 | +atl2_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) | ||
3174 | +{ | ||
3175 | + switch (cmd) { | ||
3176 | + case SIOCGMIIPHY: | ||
3177 | + case SIOCGMIIREG: | ||
3178 | + case SIOCSMIIREG: | ||
3179 | + return atl2_mii_ioctl(netdev, ifr, cmd); | ||
3180 | +#ifdef ETHTOOL_OPS_COMPAT | ||
3181 | + case SIOCETHTOOL: | ||
3182 | + return ethtool_ioctl(ifr); | ||
3183 | +#endif | ||
3184 | + default: | ||
3185 | + return -EOPNOTSUPP; | ||
3186 | + } | ||
3187 | +} | ||
3188 | + | ||
3189 | +/** | ||
3190 | + * atl2_tx_timeout - Respond to a Tx Hang | ||
3191 | + * @netdev: network interface device structure | ||
3192 | + **/ | ||
3193 | +static void | ||
3194 | +atl2_tx_timeout(struct net_device *netdev) | ||
3195 | +{ | ||
3196 | + struct atl2_adapter *adapter = netdev_priv(netdev); | ||
3197 | + | ||
3198 | + /* Do the reset outside of interrupt context */ | ||
3199 | + schedule_work(&adapter->reset_task); | ||
3200 | +} | ||
3201 | + | ||
3202 | +/** | ||
3203 | + * atl2_watchdog - Timer Call-back | ||
3204 | + * @data: pointer to netdev cast into an unsigned long | ||
3205 | + **/ | ||
3206 | +static void | ||
3207 | +atl2_watchdog(unsigned long data) | ||
3208 | +{ | ||
3209 | + struct atl2_adapter *adapter = (struct atl2_adapter *) data; | ||
3210 | + u32 drop_rxd, drop_rxs; | ||
3211 | + unsigned long flags; | ||
3212 | + | ||
3213 | + if (!test_bit(__ATL2_DOWN, &adapter->flags)) { | ||
3214 | + spin_lock_irqsave(&adapter->stats_lock, flags); | ||
3215 | + drop_rxd = ATL2_READ_REG(&adapter->hw, REG_STS_RXD_OV); | ||
3216 | + drop_rxs = ATL2_READ_REG(&adapter->hw, REG_STS_RXS_OV); | ||
3217 | + adapter->net_stats.rx_over_errors += (drop_rxd+drop_rxs); | ||
3218 | + spin_unlock_irqrestore(&adapter->stats_lock, flags); | ||
3219 | + | ||
3220 | + /* Reset the timer */ | ||
3221 | + mod_timer(&adapter->watchdog_timer, jiffies + 4 * HZ); | ||
3222 | + } | ||
3223 | +} | ||
3224 | + | ||
3225 | +/** | ||
3226 | + * atl2_phy_config - Timer Call-back | ||
3227 | + * @data: pointer to netdev cast into an unsigned long | ||
3228 | + **/ | ||
3229 | +static void | ||
3230 | +atl2_phy_config(unsigned long data) | ||
3231 | +{ | ||
3232 | + struct atl2_adapter *adapter = (struct atl2_adapter *) data; | ||
3233 | + struct atl2_hw *hw = &adapter->hw; | ||
3234 | + unsigned long flags; | ||
3235 | + | ||
3236 | + spin_lock_irqsave(&adapter->stats_lock, flags); | ||
3237 | + atl2_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg); | ||
3238 | + atl2_write_phy_reg(hw, MII_BMCR, MII_CR_RESET|MII_CR_AUTO_NEG_EN|MII_CR_RESTART_AUTO_NEG); | ||
3239 | + spin_unlock_irqrestore(&adapter->stats_lock, flags); | ||
3240 | + clear_bit(0, &adapter->cfg_phy); | ||
3241 | +} | ||
3242 | + | ||
3243 | +int | ||
3244 | +atl2_up(struct atl2_adapter *adapter) | ||
3245 | +{ | ||
3246 | + struct net_device *netdev = adapter->netdev; | ||
3247 | + int err = 0; | ||
3248 | + u32 val; | ||
3249 | + | ||
3250 | + /* hardware has been reset, we need to reload some things */ | ||
3251 | + | ||
3252 | + err = atl2_init_hw(&adapter->hw); | ||
3253 | + if (err) { | ||
3254 | + err = -EIO; | ||
3255 | + return err; | ||
3256 | + } | ||
3257 | + | ||
3258 | + atl2_set_multi(netdev); | ||
3259 | + init_ring_ptrs(adapter); | ||
3260 | + | ||
3261 | +#ifdef NETIF_F_HW_VLAN_TX | ||
3262 | + atl2_restore_vlan(adapter); | ||
3263 | +#endif | ||
3264 | + | ||
3265 | + if (atl2_configure(adapter)) { | ||
3266 | + err = -EIO; | ||
3267 | + goto err_up; | ||
3268 | + } | ||
3269 | + | ||
3270 | + clear_bit(__ATL2_DOWN, &adapter->flags); | ||
3271 | + | ||
3272 | + val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL); | ||
3273 | + ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, val | MASTER_CTRL_MANUAL_INT); | ||
3274 | + | ||
3275 | + atl2_irq_enable(adapter); | ||
3276 | + | ||
3277 | +err_up: | ||
3278 | + return err; | ||
3279 | +} | ||
3280 | + | ||
3281 | +void | ||
3282 | +atl2_reinit_locked(struct atl2_adapter *adapter) | ||
3283 | +{ | ||
3284 | + WARN_ON(in_interrupt()); | ||
3285 | + while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags)) | ||
3286 | + msleep(1); | ||
3287 | + atl2_down(adapter); | ||
3288 | + atl2_up(adapter); | ||
3289 | + clear_bit(__ATL2_RESETTING, &adapter->flags); | ||
3290 | +} | ||
3291 | + | ||
3292 | +static void | ||
3293 | +atl2_reset_task(struct work_struct *work) | ||
3294 | +{ | ||
3295 | + struct atl2_adapter *adapter; | ||
3296 | + adapter = container_of(work, struct atl2_adapter, reset_task); | ||
3297 | + | ||
3298 | + atl2_reinit_locked(adapter); | ||
3299 | +} | ||
3300 | + | ||
3301 | +static inline void | ||
3302 | +atl2_setup_mac_ctrl(struct atl2_adapter *adapter) | ||
3303 | +{ | ||
3304 | + u32 value; | ||
3305 | + struct atl2_hw* hw = &adapter->hw; | ||
3306 | + struct net_device* netdev = adapter->netdev; | ||
3307 | + | ||
3308 | + /* Config MAC CTRL Register */ | ||
3309 | + value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY; | ||
3310 | + | ||
3311 | + // duplex | ||
3312 | + if (FULL_DUPLEX == adapter->link_duplex) | ||
3313 | + value |= MAC_CTRL_DUPLX; | ||
3314 | + | ||
3315 | + // flow control | ||
3316 | + value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW); | ||
3317 | + | ||
3318 | + // PAD & CRC | ||
3319 | + value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD); | ||
3320 | + | ||
3321 | + // preamble length | ||
3322 | + value |= (((u32)adapter->hw.preamble_len & MAC_CTRL_PRMLEN_MASK) << | ||
3323 | + MAC_CTRL_PRMLEN_SHIFT); | ||
3324 | + | ||
3325 | + // vlan | ||
3326 | + if (adapter->vlgrp) | ||
3327 | + value |= MAC_CTRL_RMV_VLAN; | ||
3328 | + | ||
3329 | + // filter mode | ||
3330 | + value |= MAC_CTRL_BC_EN; | ||
3331 | + if (netdev->flags & IFF_PROMISC) | ||
3332 | + value |= MAC_CTRL_PROMIS_EN; | ||
3333 | + else if (netdev->flags & IFF_ALLMULTI) | ||
3334 | + value |= MAC_CTRL_MC_ALL_EN; | ||
3335 | + | ||
3336 | + // half retry buffer | ||
3337 | + value |= (((u32)(adapter->hw.retry_buf & MAC_CTRL_HALF_LEFT_BUF_MASK)) << | ||
3338 | + MAC_CTRL_HALF_LEFT_BUF_SHIFT); | ||
3339 | + | ||
3340 | + ATL2_WRITE_REG(hw, REG_MAC_CTRL, value); | ||
3341 | +} | ||
3342 | + | ||
3343 | +static int | ||
3344 | +atl2_check_link(struct atl2_adapter *adapter) | ||
3345 | +{ | ||
3346 | + struct atl2_hw *hw = &adapter->hw; | ||
3347 | + struct net_device * netdev = adapter->netdev; | ||
3348 | + int ret_val; | ||
3349 | + u16 speed, duplex, phy_data; | ||
3350 | + int reconfig = 0; | ||
3351 | + | ||
3352 | + // MII_BMSR must read twise | ||
3353 | + atl2_read_phy_reg(hw, MII_BMSR, &phy_data); | ||
3354 | + atl2_read_phy_reg(hw, MII_BMSR, &phy_data); | ||
3355 | + if (!(phy_data&BMSR_LSTATUS)) { // link down | ||
3356 | + if (netif_carrier_ok(netdev)) { // old link state: Up | ||
3357 | + u32 value; | ||
3358 | + //disable rx | ||
3359 | + value = ATL2_READ_REG(hw, REG_MAC_CTRL); | ||
3360 | + value &= ~MAC_CTRL_RX_EN; | ||
3361 | + ATL2_WRITE_REG(hw, REG_MAC_CTRL, value); | ||
3362 | + adapter->link_speed = SPEED_0; | ||
3363 | + netif_carrier_off(netdev); | ||
3364 | + netif_stop_queue(netdev); | ||
3365 | + } | ||
3366 | + return ATL2_SUCCESS; | ||
3367 | + } | ||
3368 | + | ||
3369 | + // Link Up | ||
3370 | + ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex); | ||
3371 | + if (ret_val) | ||
3372 | + return ret_val; | ||
3373 | + switch( hw->MediaType ) { | ||
3374 | + case MEDIA_TYPE_100M_FULL: | ||
3375 | + if (speed != SPEED_100 || duplex != FULL_DUPLEX) | ||
3376 | + reconfig = 1; | ||
3377 | + break; | ||
3378 | + case MEDIA_TYPE_100M_HALF: | ||
3379 | + if (speed != SPEED_100 || duplex != HALF_DUPLEX) | ||
3380 | + reconfig = 1; | ||
3381 | + break; | ||
3382 | + case MEDIA_TYPE_10M_FULL: | ||
3383 | + if (speed != SPEED_10 || duplex != FULL_DUPLEX) | ||
3384 | + reconfig = 1; | ||
3385 | + break; | ||
3386 | + case MEDIA_TYPE_10M_HALF: | ||
3387 | + if (speed != SPEED_10 || duplex != HALF_DUPLEX) | ||
3388 | + reconfig = 1; | ||
3389 | + break; | ||
3390 | + } | ||
3391 | + // link result is our setting | ||
3392 | + if (0 == reconfig) { | ||
3393 | + if (adapter->link_speed != speed || adapter->link_duplex != duplex ) { | ||
3394 | + adapter->link_speed = speed; | ||
3395 | + adapter->link_duplex = duplex; | ||
3396 | + atl2_setup_mac_ctrl(adapter); | ||
3397 | + printk(KERN_INFO "%s: %s NIC Link is Up<%d Mbps %s>\n", | ||
3398 | + atl2_driver_name, netdev->name, | ||
3399 | + adapter->link_speed, | ||
3400 | + adapter->link_duplex == FULL_DUPLEX ? | ||
3401 | + "Full Duplex" : "Half Duplex"); | ||
3402 | + } | ||
3403 | + | ||
3404 | + if (!netif_carrier_ok(netdev)) { // Link down -> Up | ||
3405 | + netif_carrier_on(netdev); | ||
3406 | + netif_wake_queue(netdev); | ||
3407 | + } | ||
3408 | + return ATL2_SUCCESS; | ||
3409 | + } | ||
3410 | + | ||
3411 | + // change orignal link status | ||
3412 | + if (netif_carrier_ok(netdev)) { | ||
3413 | + u32 value; | ||
3414 | + // disable rx | ||
3415 | + value = ATL2_READ_REG(hw, REG_MAC_CTRL); | ||
3416 | + value &= ~MAC_CTRL_RX_EN; | ||
3417 | + ATL2_WRITE_REG(hw, REG_MAC_CTRL, value); | ||
3418 | + | ||
3419 | + adapter->link_speed = SPEED_0; | ||
3420 | + netif_carrier_off(netdev); | ||
3421 | + netif_stop_queue(netdev); | ||
3422 | + } | ||
3423 | + | ||
3424 | + // auto-neg, insert timer to re-config phy (if interval smaller than 5 seconds, something strange) | ||
3425 | + if (!test_bit(__ATL2_DOWN, &adapter->flags)) { | ||
3426 | + if (!test_and_set_bit(0, &adapter->cfg_phy)) { | ||
3427 | + mod_timer(&adapter->phy_config_timer, jiffies + 5 * HZ); | ||
3428 | + } | ||
3429 | + } | ||
3430 | + | ||
3431 | + return ATL2_SUCCESS; | ||
3432 | +} | ||
3433 | + | ||
3434 | +/** | ||
3435 | + * atl2_link_chg_task - deal with link change event Out of interrupt context | ||
3436 | + * @netdev: network interface device structure | ||
3437 | + **/ | ||
3438 | +static void | ||
3439 | +atl2_link_chg_task(struct work_struct *work) | ||
3440 | +{ | ||
3441 | + struct atl2_adapter *adapter; | ||
3442 | + unsigned long flags; | ||
3443 | + | ||
3444 | + adapter = container_of(work, struct atl2_adapter, link_chg_task); | ||
3445 | + | ||
3446 | + spin_lock_irqsave(&adapter->stats_lock, flags); | ||
3447 | + atl2_check_link(adapter); | ||
3448 | + spin_unlock_irqrestore(&adapter->stats_lock, flags); | ||
3449 | +} | ||
3450 | + | ||
3451 | +static void | ||
3452 | +atl2_setup_pcicmd(struct pci_dev *pdev) | ||
3453 | +{ | ||
3454 | + u16 cmd; | ||
3455 | + | ||
3456 | + pci_read_config_word(pdev, PCI_COMMAND, &cmd); | ||
3457 | + | ||
3458 | + if (cmd & PCI_COMMAND_INTX_DISABLE) | ||
3459 | + cmd &= ~PCI_COMMAND_INTX_DISABLE; | ||
3460 | + if (cmd & PCI_COMMAND_IO) | ||
3461 | + cmd &= ~PCI_COMMAND_IO; | ||
3462 | + if (0 == (cmd & PCI_COMMAND_MEMORY)) | ||
3463 | + cmd |= PCI_COMMAND_MEMORY; | ||
3464 | + if (0 == (cmd & PCI_COMMAND_MASTER)) | ||
3465 | + cmd |= PCI_COMMAND_MASTER; | ||
3466 | + pci_write_config_word(pdev, PCI_COMMAND, cmd); | ||
3467 | + | ||
3468 | + /* | ||
3469 | + * some motherboards BIOS(PXE/EFI) driver may set PME | ||
3470 | + * while they transfer control to OS (Windows/Linux) | ||
3471 | + * so we should clear this bit before NIC work normally | ||
3472 | + */ | ||
3473 | + pci_write_config_dword(pdev, REG_PM_CTRLSTAT, 0); | ||
3474 | +} | ||
3475 | + | ||
3476 | +/** | ||
3477 | + * atl2_probe - Device Initialization Routine | ||
3478 | + * @pdev: PCI device information struct | ||
3479 | + * @ent: entry in atl2_pci_tbl | ||
3480 | + * | ||
3481 | + * Returns 0 on success, negative on failure | ||
3482 | + * | ||
3483 | + * atl2_probe initializes an adapter identified by a pci_dev structure. | ||
3484 | + * The OS initialization, configuring of the adapter private structure, | ||
3485 | + * and a hardware reset occur. | ||
3486 | + **/ | ||
3487 | +static int __devinit | ||
3488 | +atl2_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | ||
3489 | +{ | ||
3490 | + struct net_device *netdev; | ||
3491 | + struct atl2_adapter *adapter; | ||
3492 | + static int cards_found = 0; | ||
3493 | + unsigned long mmio_start; | ||
3494 | + int mmio_len; | ||
3495 | + int err; | ||
3496 | + | ||
3497 | + if((err = pci_enable_device(pdev))) | ||
3498 | + return err; | ||
3499 | + | ||
3500 | + /* | ||
3501 | + * atl2 is a shared-high-32-bit device, so we're stuck with 32-bit DMA | ||
3502 | + * until the kernel has the proper infrastructure to support 64-bit DMA | ||
3503 | + * on these devices. | ||
3504 | + */ | ||
3505 | + if ((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) && | ||
3506 | + (err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))) { | ||
3507 | + printk(KERN_ERR "atl2: No usable DMA configuration, aborting\n"); | ||
3508 | + goto err_dma; | ||
3509 | + } | ||
3510 | + | ||
3511 | + // Mark all PCI regions associated with PCI device | ||
3512 | + // pdev as being reserved by owner atl2_driver_name | ||
3513 | + if((err = pci_request_regions(pdev, atl2_driver_name))) | ||
3514 | + goto err_pci_reg; | ||
3515 | + | ||
3516 | + // Enables bus-mastering on the device and calls | ||
3517 | + // pcibios_set_master to do the needed arch specific settings | ||
3518 | + pci_set_master(pdev); | ||
3519 | + | ||
3520 | + err = -ENOMEM; | ||
3521 | + netdev = alloc_etherdev(sizeof(struct atl2_adapter)); | ||
3522 | + if(!netdev) | ||
3523 | + goto err_alloc_etherdev; | ||
3524 | + | ||
3525 | + SET_NETDEV_DEV(netdev, &pdev->dev); | ||
3526 | + | ||
3527 | + pci_set_drvdata(pdev, netdev); | ||
3528 | + adapter = netdev_priv(netdev); | ||
3529 | + adapter->netdev = netdev; | ||
3530 | + adapter->pdev = pdev; | ||
3531 | + adapter->hw.back = adapter; | ||
3532 | + | ||
3533 | + mmio_start = pci_resource_start(pdev, 0x0); | ||
3534 | + mmio_len = pci_resource_len(pdev, 0x0); | ||
3535 | + | ||
3536 | + adapter->hw.mem_rang = (u32)mmio_len; | ||
3537 | + adapter->hw.hw_addr = ioremap(mmio_start, mmio_len); | ||
3538 | + if(!adapter->hw.hw_addr) { | ||
3539 | + err = -EIO; | ||
3540 | + goto err_ioremap; | ||
3541 | + } | ||
3542 | + | ||
3543 | + atl2_setup_pcicmd(pdev); | ||
3544 | + | ||
3545 | + netdev->open = &atl2_open; | ||
3546 | + netdev->stop = &atl2_close; | ||
3547 | + netdev->hard_start_xmit = &atl2_xmit_frame; | ||
3548 | + netdev->get_stats = &atl2_get_stats; | ||
3549 | + netdev->set_multicast_list = &atl2_set_multi; | ||
3550 | + netdev->set_mac_address = &atl2_set_mac; | ||
3551 | + netdev->change_mtu = &atl2_change_mtu; | ||
3552 | + netdev->do_ioctl = &atl2_ioctl; | ||
3553 | + atl2_set_ethtool_ops(netdev); | ||
3554 | + | ||
3555 | +#ifdef HAVE_TX_TIMEOUT | ||
3556 | + netdev->tx_timeout = &atl2_tx_timeout; | ||
3557 | + netdev->watchdog_timeo = 5 * HZ; //FIXME -- CHS | ||
3558 | +#endif | ||
3559 | +#ifdef NETIF_F_HW_VLAN_TX | ||
3560 | + netdev->vlan_rx_register = atl2_vlan_rx_register; | ||
3561 | +#endif | ||
3562 | + strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); | ||
3563 | + | ||
3564 | + netdev->mem_start = mmio_start; | ||
3565 | + netdev->mem_end = mmio_start + mmio_len; | ||
3566 | + //netdev->base_addr = adapter->io_base; | ||
3567 | + adapter->bd_number = cards_found; | ||
3568 | + adapter->pci_using_64 = false; | ||
3569 | + | ||
3570 | + /* setup the private structure */ | ||
3571 | + | ||
3572 | + if((err = atl2_sw_init(adapter))) | ||
3573 | + goto err_sw_init; | ||
3574 | + | ||
3575 | + err = -EIO; | ||
3576 | + | ||
3577 | +#ifdef NETIF_F_HW_VLAN_TX | ||
3578 | + netdev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX ); | ||
3579 | +#endif | ||
3580 | + | ||
3581 | +#ifdef NETIF_F_LLTX | ||
3582 | + netdev->features |= NETIF_F_LLTX; | ||
3583 | +#endif | ||
3584 | + | ||
3585 | + /* Init PHY as early as possible due to power saving issue */ | ||
3586 | + atl2_phy_init(&adapter->hw); | ||
3587 | + | ||
3588 | + /* reset the controller to | ||
3589 | + * put the device in a known good starting state */ | ||
3590 | + | ||
3591 | + if (atl2_reset_hw(&adapter->hw)) { | ||
3592 | + err = -EIO; | ||
3593 | + goto err_reset; | ||
3594 | + } | ||
3595 | + | ||
3596 | + /* copy the MAC address out of the EEPROM */ | ||
3597 | + atl2_read_mac_addr(&adapter->hw); | ||
3598 | + memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len); | ||
3599 | +//FIXME: do we still need this? | ||
3600 | +#ifdef ETHTOOL_GPERMADDR | ||
3601 | + memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len); | ||
3602 | + | ||
3603 | + if (!is_valid_ether_addr(netdev->perm_addr)) { | ||
3604 | +#else | ||
3605 | + if (!is_valid_ether_addr(netdev->dev_addr)) { | ||
3606 | +#endif | ||
3607 | + err = -EIO; | ||
3608 | + goto err_eeprom; | ||
3609 | + } | ||
3610 | + | ||
3611 | + atl2_check_options(adapter); | ||
3612 | + | ||
3613 | + init_timer(&adapter->watchdog_timer); | ||
3614 | + adapter->watchdog_timer.function = &atl2_watchdog; | ||
3615 | + adapter->watchdog_timer.data = (unsigned long) adapter; | ||
3616 | + | ||
3617 | + init_timer(&adapter->phy_config_timer); | ||
3618 | + adapter->phy_config_timer.function = &atl2_phy_config; | ||
3619 | + adapter->phy_config_timer.data = (unsigned long) adapter; | ||
3620 | + | ||
3621 | + INIT_WORK(&adapter->reset_task, atl2_reset_task); | ||
3622 | + INIT_WORK(&adapter->link_chg_task, atl2_link_chg_task); | ||
3623 | + | ||
3624 | + strcpy(netdev->name, "eth%d"); // ?? | ||
3625 | + if((err = register_netdev(netdev))) | ||
3626 | + goto err_register; | ||
3627 | + | ||
3628 | + /* assume we have no link for now */ | ||
3629 | + netif_carrier_off(netdev); | ||
3630 | + netif_stop_queue(netdev); | ||
3631 | + | ||
3632 | + cards_found++; | ||
3633 | + | ||
3634 | + return 0; | ||
3635 | + | ||
3636 | +//err_init_hw: | ||
3637 | +err_reset: | ||
3638 | +err_register: | ||
3639 | +err_sw_init: | ||
3640 | +err_eeprom: | ||
3641 | + iounmap(adapter->hw.hw_addr); | ||
3642 | +err_ioremap: | ||
3643 | + free_netdev(netdev); | ||
3644 | +err_alloc_etherdev: | ||
3645 | + pci_release_regions(pdev); | ||
3646 | +err_pci_reg: | ||
3647 | +err_dma: | ||
3648 | + pci_disable_device(pdev); | ||
3649 | + return err; | ||
3650 | +} | ||
3651 | + | ||
3652 | +/** | ||
3653 | + * atl2_remove - Device Removal Routine | ||
3654 | + * @pdev: PCI device information struct | ||
3655 | + * | ||
3656 | + * atl2_remove is called by the PCI subsystem to alert the driver | ||
3657 | + * that it should release a PCI device. The could be caused by a | ||
3658 | + * Hot-Plug event, or because the driver is going to be removed from | ||
3659 | + * memory. | ||
3660 | + **/ | ||
3661 | +/* FIXME: write the original MAC address back in case it was changed from a | ||
3662 | + * BIOS-set value, as in atl1 -- CHS */ | ||
3663 | +static void __devexit | ||
3664 | +atl2_remove(struct pci_dev *pdev) | ||
3665 | +{ | ||
3666 | + struct net_device *netdev = pci_get_drvdata(pdev); | ||
3667 | + struct atl2_adapter *adapter = netdev_priv(netdev); | ||
3668 | + | ||
3669 | + /* flush_scheduled work may reschedule our watchdog task, so | ||
3670 | + * explicitly disable watchdog tasks from being rescheduled */ | ||
3671 | + set_bit(__ATL2_DOWN, &adapter->flags); | ||
3672 | + | ||
3673 | + del_timer_sync(&adapter->watchdog_timer); | ||
3674 | + del_timer_sync(&adapter->phy_config_timer); | ||
3675 | + | ||
3676 | + flush_scheduled_work(); | ||
3677 | + | ||
3678 | + unregister_netdev(netdev); | ||
3679 | + | ||
3680 | + atl2_force_ps(&adapter->hw); | ||
3681 | + | ||
3682 | + iounmap(adapter->hw.hw_addr); | ||
3683 | + pci_release_regions(pdev); | ||
3684 | + | ||
3685 | + free_netdev(netdev); | ||
3686 | + | ||
3687 | + pci_disable_device(pdev); | ||
3688 | +} | ||
3689 | + | ||
3690 | +static int | ||
3691 | +atl2_suspend(struct pci_dev *pdev, pm_message_t state) | ||
3692 | +{ | ||
3693 | + struct net_device *netdev = pci_get_drvdata(pdev); | ||
3694 | + struct atl2_adapter *adapter = netdev_priv(netdev); | ||
3695 | + struct atl2_hw * hw = &adapter->hw; | ||
3696 | + u16 speed, duplex; | ||
3697 | + u32 ctrl = 0; | ||
3698 | + u32 wufc = adapter->wol; | ||
3699 | + | ||
3700 | +#ifdef CONFIG_PM | ||
3701 | + int retval = 0; | ||
3702 | +#endif | ||
3703 | + | ||
3704 | + netif_device_detach(netdev); | ||
3705 | + | ||
3706 | + if (netif_running(netdev)) { | ||
3707 | + WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags)); | ||
3708 | + atl2_down(adapter); | ||
3709 | + } | ||
3710 | + | ||
3711 | +#ifdef CONFIG_PM | ||
3712 | + retval = pci_save_state(pdev); | ||
3713 | + if (retval) | ||
3714 | + return retval; | ||
3715 | +#endif | ||
3716 | + | ||
3717 | + atl2_read_phy_reg(hw, MII_BMSR, (u16*)&ctrl); | ||
3718 | + atl2_read_phy_reg(hw, MII_BMSR, (u16*)&ctrl); | ||
3719 | + if(ctrl & BMSR_LSTATUS) | ||
3720 | + wufc &= ~ATL2_WUFC_LNKC; | ||
3721 | + | ||
3722 | + if (0 != (ctrl & BMSR_LSTATUS) && 0 != wufc) { | ||
3723 | + u32 ret_val; | ||
3724 | + /* get current link speed & duplex */ | ||
3725 | + ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex); | ||
3726 | + if (ret_val) { | ||
3727 | + printk(KERN_DEBUG "%s: get speed&duplex error while suspend\n", atl2_driver_name); | ||
3728 | + goto wol_dis; | ||
3729 | + } | ||
3730 | + | ||
3731 | + ctrl = 0; | ||
3732 | + | ||
3733 | + /* turn on magic packet wol */ | ||
3734 | + if (wufc & ATL2_WUFC_MAG) | ||
3735 | + ctrl |= (WOL_MAGIC_EN | WOL_MAGIC_PME_EN); | ||
3736 | + | ||
3737 | + /* ignore Link Chg event when Link is up */ | ||
3738 | + ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl); | ||
3739 | + | ||
3740 | + /* Config MAC CTRL Register */ | ||
3741 | + ctrl = MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY; | ||
3742 | + if (FULL_DUPLEX == adapter->link_duplex) | ||
3743 | + ctrl |= MAC_CTRL_DUPLX; | ||
3744 | + ctrl |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD); | ||
3745 | + ctrl |= (((u32)adapter->hw.preamble_len & | ||
3746 | + MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT); | ||
3747 | + ctrl |= (((u32)(adapter->hw.retry_buf & | ||
3748 | + MAC_CTRL_HALF_LEFT_BUF_MASK)) << | ||
3749 | + MAC_CTRL_HALF_LEFT_BUF_SHIFT); | ||
3750 | + if (wufc & ATL2_WUFC_MAG) { | ||
3751 | + /* magic packet maybe Broadcast&multicast&Unicast frame */ | ||
3752 | + ctrl |= MAC_CTRL_BC_EN; | ||
3753 | + } | ||
3754 | + | ||
3755 | + ATL2_WRITE_REG(hw, REG_MAC_CTRL, ctrl); | ||
3756 | + | ||
3757 | + /* pcie patch */ | ||
3758 | + ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC); | ||
3759 | + ctrl |= PCIE_PHYMISC_FORCE_RCV_DET; | ||
3760 | + ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl); | ||
3761 | + ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1); | ||
3762 | + ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK; | ||
3763 | + ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl); | ||
3764 | + | ||
3765 | + pci_enable_wake(pdev, pci_choose_state(pdev, state), 1); | ||
3766 | + goto suspend_exit; | ||
3767 | + } | ||
3768 | + | ||
3769 | + if (0 == (ctrl&BMSR_LSTATUS) && 0 != (wufc&ATL2_WUFC_LNKC)) { | ||
3770 | + /* link is down, so only LINK CHG WOL event enable */ | ||
3771 | + ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN); | ||
3772 | + ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl); | ||
3773 | + ATL2_WRITE_REG(hw, REG_MAC_CTRL, 0); | ||
3774 | + | ||
3775 | + /* pcie patch */ | ||
3776 | + ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC); | ||
3777 | + ctrl |= PCIE_PHYMISC_FORCE_RCV_DET; | ||
3778 | + ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl); | ||
3779 | + ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1); | ||
3780 | + ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK; | ||
3781 | + ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl); | ||
3782 | + | ||
3783 | + hw->phy_configured = false; /* re-init PHY when resume */ | ||
3784 | + | ||
3785 | + pci_enable_wake(pdev, pci_choose_state(pdev, state), 1); | ||
3786 | + | ||
3787 | + goto suspend_exit; | ||
3788 | + } | ||
3789 | + | ||
3790 | +wol_dis: | ||
3791 | + /* WOL disabled */ | ||
3792 | + ATL2_WRITE_REG(hw, REG_WOL_CTRL, 0); | ||
3793 | + | ||
3794 | + /* pcie patch */ | ||
3795 | + ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC); | ||
3796 | + ctrl |= PCIE_PHYMISC_FORCE_RCV_DET; | ||
3797 | + ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl); | ||
3798 | + ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1); | ||
3799 | + ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK; | ||
3800 | + ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl); | ||
3801 | + | ||
3802 | + atl2_force_ps(hw); | ||
3803 | + hw->phy_configured = false; /* re-init PHY when resume */ | ||
3804 | + | ||
3805 | + pci_enable_wake(pdev, pci_choose_state(pdev, state), 0); | ||
3806 | + | ||
3807 | +suspend_exit: | ||
3808 | + if (netif_running(netdev)) | ||
3809 | + atl2_free_irq(adapter); | ||
3810 | + | ||
3811 | + pci_disable_device(pdev); | ||
3812 | + | ||
3813 | + pci_set_power_state(pdev, pci_choose_state(pdev, state)); | ||
3814 | + | ||
3815 | + return 0; | ||
3816 | +} | ||
3817 | + | ||
3818 | +#ifdef CONFIG_PM | ||
3819 | +static int | ||
3820 | +atl2_resume(struct pci_dev *pdev) | ||
3821 | +{ | ||
3822 | + struct net_device *netdev = pci_get_drvdata(pdev); | ||
3823 | + struct atl2_adapter *adapter = netdev_priv(netdev); | ||
3824 | + u32 err; | ||
3825 | + | ||
3826 | + pci_set_power_state(pdev, PCI_D0); | ||
3827 | + pci_restore_state(pdev); | ||
3828 | + | ||
3829 | + if ((err = pci_enable_device(pdev))) { | ||
3830 | + printk(KERN_ERR "atl2: Cannot enable PCI device from suspend\n"); | ||
3831 | + return err; | ||
3832 | + } | ||
3833 | + | ||
3834 | + pci_set_master(pdev); | ||
3835 | + | ||
3836 | + ATL2_READ_REG(&adapter->hw, REG_WOL_CTRL); /* clear WOL status */ | ||
3837 | + | ||
3838 | + pci_enable_wake(pdev, PCI_D3hot, 0); | ||
3839 | + pci_enable_wake(pdev, PCI_D3cold, 0); | ||
3840 | + | ||
3841 | + ATL2_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0); | ||
3842 | + | ||
3843 | + if (netif_running(netdev) && (err = atl2_request_irq(adapter))) | ||
3844 | + return err; | ||
3845 | + | ||
3846 | + atl2_reset_hw(&adapter->hw); | ||
3847 | + | ||
3848 | + if(netif_running(netdev)) | ||
3849 | + atl2_up(adapter); | ||
3850 | + | ||
3851 | + netif_device_attach(netdev); | ||
3852 | + | ||
3853 | + return 0; | ||
3854 | +} | ||
3855 | +#endif | ||
3856 | + | ||
3857 | +static void | ||
3858 | +atl2_shutdown(struct pci_dev *pdev) | ||
3859 | +{ | ||
3860 | + atl2_suspend(pdev, PMSG_SUSPEND); | ||
3861 | +} | ||
3862 | + | ||
3863 | +static struct pci_driver atl2_driver = { | ||
3864 | + .name = atl2_driver_name, | ||
3865 | + .id_table = atl2_pci_tbl, | ||
3866 | + .probe = atl2_probe, | ||
3867 | + .remove = __devexit_p(atl2_remove), | ||
3868 | + /* Power Managment Hooks */ | ||
3869 | + .suspend = atl2_suspend, | ||
3870 | +#ifdef CONFIG_PM | ||
3871 | + .resume = atl2_resume, | ||
3872 | +#endif | ||
3873 | + .shutdown = atl2_shutdown, | ||
3874 | +}; | ||
3875 | + | ||
3876 | +/** | ||
3877 | + * atl2_init_module - Driver Registration Routine | ||
3878 | + * | ||
3879 | + * atl2_init_module is the first routine called when the driver is | ||
3880 | + * loaded. All it does is register with the PCI subsystem. | ||
3881 | + **/ | ||
3882 | +static int __init | ||
3883 | +atl2_init_module(void) | ||
3884 | +{ | ||
3885 | + int ret; | ||
3886 | + printk(KERN_INFO "%s - version %s\n", atl2_driver_string, atl2_driver_version); | ||
3887 | + printk(KERN_INFO "%s\n", atl2_copyright); | ||
3888 | + | ||
3889 | + ret = pci_register_driver(&atl2_driver); | ||
3890 | + if (copybreak != COPYBREAK_DEFAULT) { | ||
3891 | + if (copybreak == 0) | ||
3892 | + printk(KERN_INFO "atl2: copybreak disabled\n"); | ||
3893 | + else | ||
3894 | + printk(KERN_INFO "atl2: copybreak enabled for packets <= %u bytes\n", copybreak); | ||
3895 | + } | ||
3896 | + return ret; | ||
3897 | +} | ||
3898 | +module_init(atl2_init_module); | ||
3899 | + | ||
3900 | +/** | ||
3901 | + * atl2_exit_module - Driver Exit Cleanup Routine | ||
3902 | + * | ||
3903 | + * atl2_exit_module is called just before the driver is removed | ||
3904 | + * from memory. | ||
3905 | + **/ | ||
3906 | +static void __exit | ||
3907 | +atl2_exit_module(void) | ||
3908 | +{ | ||
3909 | + pci_unregister_driver(&atl2_driver); | ||
3910 | +} | ||
3911 | +module_exit(atl2_exit_module); | ||
3912 | + | ||
3913 | +void | ||
3914 | +atl2_read_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value) | ||
3915 | +{ | ||
3916 | + struct atl2_adapter *adapter = hw->back; | ||
3917 | + pci_read_config_word(adapter->pdev, reg, value); | ||
3918 | +} | ||
3919 | + | ||
3920 | +void | ||
3921 | +atl2_write_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value) | ||
3922 | +{ | ||
3923 | + struct atl2_adapter *adapter = hw->back; | ||
3924 | + pci_write_config_word(adapter->pdev, reg, *value); | ||
3925 | +} | ||
3926 | diff -Nurp a/drivers/net/atl2/atl2_osdep.h b/drivers/net/atl2/atl2_osdep.h | ||
3927 | --- a/drivers/net/atl2/atl2_osdep.h 1969-12-31 19:00:00.000000000 -0500 | ||
3928 | +++ b/drivers/net/atl2/atl2_osdep.h 2007-12-04 16:48:02.000000000 -0500 | ||
3929 | @@ -0,0 +1,72 @@ | ||
3930 | +/* atl2_osdep.h -- atl2 compat cruft | ||
3931 | + * | ||
3932 | + * Copyright(c) 2007 Atheros Corporation. All rights reserved. | ||
3933 | + * Copyright(c) 2006 xiong huang <xiong.huang@atheros.com> | ||
3934 | + * Copyright(c) 2007 Chris Snook <csnook@redhat.com> | ||
3935 | + * | ||
3936 | + * Derived from Intel e1000 driver | ||
3937 | + * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. | ||
3938 | + * | ||
3939 | + * This program is free software; you can redistribute it and/or modify it | ||
3940 | + * under the terms of the GNU General Public License as published by the Free | ||
3941 | + * Software Foundation; either version 2 of the License, or (at your option) | ||
3942 | + * any later version. | ||
3943 | + * | ||
3944 | + * This program is distributed in the hope that it will be useful, but WITHOUT | ||
3945 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
3946 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
3947 | + * more details. | ||
3948 | + * | ||
3949 | + * You should have received a copy of the GNU General Public License along with | ||
3950 | + * this program; if not, write to the Free Software Foundation, Inc., 59 | ||
3951 | + * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
3952 | + */ | ||
3953 | + | ||
3954 | +#ifndef _ATL2_OSDEP_H_ | ||
3955 | +#define _ATL2_OSDEP_H_ | ||
3956 | + | ||
3957 | +#include <linux/pci.h> | ||
3958 | +#include <linux/delay.h> | ||
3959 | +#include <linux/interrupt.h> | ||
3960 | +#include <linux/if_ether.h> | ||
3961 | + | ||
3962 | +#define usec_delay(x) udelay(x) | ||
3963 | +#ifndef msec_delay | ||
3964 | +#define msec_delay(x) do { \ | ||
3965 | + if(in_interrupt()) BUG(); \ | ||
3966 | + else msleep(x); \ | ||
3967 | + } while (0) | ||
3968 | + | ||
3969 | +/* Some workarounds require millisecond delays and are run during interrupt | ||
3970 | + * context. Most notably, when establishing link, the phy may need tweaking | ||
3971 | + * but cannot process phy register reads/writes faster than millisecond | ||
3972 | + * intervals...and we establish link due to a "link status change" interrupt. | ||
3973 | + */ | ||
3974 | +#define msec_delay_irq(x) mdelay(x) | ||
3975 | +#endif | ||
3976 | + | ||
3977 | +#define PCI_COMMAND_REGISTER PCI_COMMAND | ||
3978 | +#define CMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE | ||
3979 | +#define ETH_ADDR_LEN ETH_ALEN | ||
3980 | + | ||
3981 | +#define ATL2_WRITE_REG(a, reg, value) (writel((value), ((a)->hw_addr + reg))) | ||
3982 | + | ||
3983 | +#define ATL2_WRITE_FLUSH(a) (readl((a)->hw_addr)) | ||
3984 | + | ||
3985 | +#define ATL2_READ_REG(a, reg) (readl((a)->hw_addr + reg)) | ||
3986 | + | ||
3987 | +#define ATL2_WRITE_REGB(a, reg, value) (writeb((value), ((a)->hw_addr + reg))) | ||
3988 | + | ||
3989 | +#define ATL2_READ_REGB(a, reg) (readb((a)->hw_addr + reg)) | ||
3990 | + | ||
3991 | +#define ATL2_WRITE_REGW(a, reg, value) (writew((value), ((a)->hw_addr + reg))) | ||
3992 | + | ||
3993 | +#define ATL2_READ_REGW(a, reg) (readw((a)->hw_addr + reg)) | ||
3994 | + | ||
3995 | +#define ATL2_WRITE_REG_ARRAY(a, reg, offset, value) \ | ||
3996 | + (writel((value), (((a)->hw_addr + reg) + ((offset) << 2)))) | ||
3997 | + | ||
3998 | +#define ATL2_READ_REG_ARRAY(a, reg, offset) \ | ||
3999 | + (readl(((a)->hw_addr + reg) + ((offset) << 2))) | ||
4000 | + | ||
4001 | +#endif /* _ATL2_OSDEP_H_ */ | ||
4002 | diff -Nurp a/drivers/net/atl2/atl2_param.c b/drivers/net/atl2/atl2_param.c | ||
4003 | --- a/drivers/net/atl2/atl2_param.c 1969-12-31 19:00:00.000000000 -0500 | ||
4004 | +++ b/drivers/net/atl2/atl2_param.c 2007-12-10 10:29:07.000000000 -0500 | ||
4005 | @@ -0,0 +1,317 @@ | ||
4006 | +/* atl2_param.c -- atl2 parameter processing | ||
4007 | + * | ||
4008 | + * Copyright(c) 2007 Atheros Corporation. All rights reserved. | ||
4009 | + * Copyright(c) 2006 xiong huang <xiong.huang@atheros.com> | ||
4010 | + * Copyright(c) 2007 Chris Snook <csnook@redhat.com> | ||
4011 | + * | ||
4012 | + * Derived from Intel e1000 driver | ||
4013 | + * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. | ||
4014 | + * | ||
4015 | + * This program is free software; you can redistribute it and/or modify it | ||
4016 | + * under the terms of the GNU General Public License as published by the Free | ||
4017 | + * Software Foundation; either version 2 of the License, or (at your option) | ||
4018 | + * any later version. | ||
4019 | + * | ||
4020 | + * This program is distributed in the hope that it will be useful, but WITHOUT | ||
4021 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
4022 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
4023 | + * more details. | ||
4024 | + * | ||
4025 | + * You should have received a copy of the GNU General Public License along with | ||
4026 | + * this program; if not, write to the Free Software Foundation, Inc., 59 | ||
4027 | + * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
4028 | + */ | ||
4029 | + | ||
4030 | +#include <linux/netdevice.h> | ||
4031 | +#include "atl2.h" | ||
4032 | + | ||
4033 | +/* This is the only thing that needs to be changed to adjust the | ||
4034 | + * maximum number of ports that the driver can manage. | ||
4035 | + */ | ||
4036 | +#define ATL2_MAX_NIC 4 | ||
4037 | + | ||
4038 | +#define OPTION_UNSET -1 | ||
4039 | +#define OPTION_DISABLED 0 | ||
4040 | +#define OPTION_ENABLED 1 | ||
4041 | + | ||
4042 | +/* All parameters are treated the same, as an integer array of values. | ||
4043 | + * This macro just reduces the need to repeat the same declaration code | ||
4044 | + * over and over (plus this helps to avoid typo bugs). | ||
4045 | + */ | ||
4046 | +#define ATL2_PARAM_INIT { [0 ... ATL2_MAX_NIC] = OPTION_UNSET } | ||
4047 | +#ifndef module_param_array | ||
4048 | +/* Module Parameters are always initialized to -1, so that the driver | ||
4049 | + * can tell the difference between no user specified value or the | ||
4050 | + * user asking for the default value. | ||
4051 | + * The true default values are loaded in when atl2_check_options is called. | ||
4052 | + * | ||
4053 | + * This is a GCC extension to ANSI C. | ||
4054 | + * See the item "Labeled Elements in Initializers" in the section | ||
4055 | + * "Extensions to the C Language Family" of the GCC documentation. | ||
4056 | + */ | ||
4057 | + | ||
4058 | +#define ATL2_PARAM(X, desc) \ | ||
4059 | + static const int __devinitdata X[ATL2_MAX_NIC + 1] = ATL2_PARAM_INIT; \ | ||
4060 | + MODULE_PARM(X, "1-" __MODULE_STRING(ATL2_MAX_NIC) "i"); \ | ||
4061 | + MODULE_PARM_DESC(X, desc); | ||
4062 | +#else | ||
4063 | +#define ATL2_PARAM(X, desc) \ | ||
4064 | + static int __devinitdata X[ATL2_MAX_NIC+1] = ATL2_PARAM_INIT; \ | ||
4065 | + static int num_##X = 0; \ | ||
4066 | + module_param_array_named(X, X, int, &num_##X, 0); \ | ||
4067 | + MODULE_PARM_DESC(X, desc); | ||
4068 | +#endif | ||
4069 | + | ||
4070 | +/* Transmit Memory Size | ||
4071 | + * | ||
4072 | + * Valid Range: 64-2048 | ||
4073 | + * | ||
4074 | + * Default Value: 128 | ||
4075 | + */ | ||
4076 | +#define ATL2_MIN_TX_MEMSIZE 4 // 4KB | ||
4077 | +#define ATL2_MAX_TX_MEMSIZE 64 // 64KB | ||
4078 | +#define ATL2_DEFAULT_TX_MEMSIZE 8 // 8KB | ||
4079 | +ATL2_PARAM(TxMemSize, "Bytes of Transmit Memory"); | ||
4080 | + | ||
4081 | +/* Receive Memory Block Count | ||
4082 | + * | ||
4083 | + * Valid Range: 16-512 | ||
4084 | + * | ||
4085 | + * Default Value: 128 | ||
4086 | + */ | ||
4087 | +#define ATL2_MIN_RXD_COUNT 16 | ||
4088 | +#define ATL2_MAX_RXD_COUNT 512 | ||
4089 | +#define ATL2_DEFAULT_RXD_COUNT 64 | ||
4090 | +ATL2_PARAM(RxMemBlock, "Number of receive memory block"); | ||
4091 | + | ||
4092 | +/* User Specified MediaType Override | ||
4093 | + * | ||
4094 | + * Valid Range: 0-5 | ||
4095 | + * - 0 - auto-negotiate at all supported speeds | ||
4096 | + * - 1 - only link at 1000Mbps Full Duplex | ||
4097 | + * - 2 - only link at 100Mbps Full Duplex | ||
4098 | + * - 3 - only link at 100Mbps Half Duplex | ||
4099 | + * - 4 - only link at 10Mbps Full Duplex | ||
4100 | + * - 5 - only link at 10Mbps Half Duplex | ||
4101 | + * Default Value: 0 | ||
4102 | + */ | ||
4103 | +ATL2_PARAM(MediaType, "MediaType Select"); | ||
4104 | + | ||
4105 | +/* Interrupt Moderate Timer in units of 2 us | ||
4106 | + * | ||
4107 | + * Valid Range: 10-65535 | ||
4108 | + * | ||
4109 | + * Default Value: 45000(90ms) | ||
4110 | + */ | ||
4111 | +#define INT_MOD_DEFAULT_CNT 100 // 200us | ||
4112 | +#define INT_MOD_MAX_CNT 65000 | ||
4113 | +#define INT_MOD_MIN_CNT 50 | ||
4114 | +ATL2_PARAM(IntModTimer, "Interrupt Moderator Timer"); | ||
4115 | + | ||
4116 | +/* FlashVendor | ||
4117 | + * Valid Range: 0-2 | ||
4118 | + * 0 - Atmel | ||
4119 | + * 1 - SST | ||
4120 | + * 2 - ST | ||
4121 | + */ | ||
4122 | +ATL2_PARAM(FlashVendor, "SPI Flash Vendor"); | ||
4123 | + | ||
4124 | +#define AUTONEG_ADV_DEFAULT 0x2F | ||
4125 | +#define AUTONEG_ADV_MASK 0x2F | ||
4126 | +#define FLOW_CONTROL_DEFAULT FLOW_CONTROL_FULL | ||
4127 | + | ||
4128 | +#define FLASH_VENDOR_DEFAULT 0 | ||
4129 | +#define FLASH_VENDOR_MIN 0 | ||
4130 | +#define FLASH_VENDOR_MAX 2 | ||
4131 | + | ||
4132 | +struct atl2_option { | ||
4133 | + enum { enable_option, range_option, list_option } type; | ||
4134 | + char *name; | ||
4135 | + char *err; | ||
4136 | + int def; | ||
4137 | + union { | ||
4138 | + struct { /* range_option info */ | ||
4139 | + int min; | ||
4140 | + int max; | ||
4141 | + } r; | ||
4142 | + struct { /* list_option info */ | ||
4143 | + int nr; | ||
4144 | + struct atl2_opt_list { int i; char *str; } *p; | ||
4145 | + } l; | ||
4146 | + } arg; | ||
4147 | +}; | ||
4148 | + | ||
4149 | +static int __devinit | ||
4150 | +atl2_validate_option(int *value, struct atl2_option *opt) | ||
4151 | +{ | ||
4152 | + int i; | ||
4153 | + struct atl2_opt_list *ent; | ||
4154 | + | ||
4155 | + if(*value == OPTION_UNSET) { | ||
4156 | + *value = opt->def; | ||
4157 | + return 0; | ||
4158 | + } | ||
4159 | + | ||
4160 | + switch (opt->type) { | ||
4161 | + case enable_option: | ||
4162 | + switch (*value) { | ||
4163 | + case OPTION_ENABLED: | ||
4164 | + printk(KERN_INFO "%s Enabled\n", opt->name); | ||
4165 | + return 0; | ||
4166 | + break; | ||
4167 | + case OPTION_DISABLED: | ||
4168 | + printk(KERN_INFO "%s Disabled\n", opt->name); | ||
4169 | + return 0; | ||
4170 | + break; | ||
4171 | + } | ||
4172 | + break; | ||
4173 | + case range_option: | ||
4174 | + if(*value >= opt->arg.r.min && *value <= opt->arg.r.max) { | ||
4175 | + printk(KERN_INFO "%s set to %i\n", opt->name, *value); | ||
4176 | + return 0; | ||
4177 | + } | ||
4178 | + break; | ||
4179 | + case list_option: | ||
4180 | + for(i = 0; i < opt->arg.l.nr; i++) { | ||
4181 | + ent = &opt->arg.l.p[i]; | ||
4182 | + if(*value == ent->i) { | ||
4183 | + if(ent->str[0] != '\0') | ||
4184 | + printk(KERN_INFO "%s\n", ent->str); | ||
4185 | + return 0; | ||
4186 | + } | ||
4187 | + } | ||
4188 | + break; | ||
4189 | + default: | ||
4190 | + BUG(); | ||
4191 | + } | ||
4192 | + | ||
4193 | + printk(KERN_INFO "Invalid %s specified (%i) %s\n", | ||
4194 | + opt->name, *value, opt->err); | ||
4195 | + *value = opt->def; | ||
4196 | + return -1; | ||
4197 | +} | ||
4198 | + | ||
4199 | +/** | ||
4200 | + * atl2_check_options - Range Checking for Command Line Parameters | ||
4201 | + * @adapter: board private structure | ||
4202 | + * | ||
4203 | + * This routine checks all command line parameters for valid user | ||
4204 | + * input. If an invalid value is given, or if no user specified | ||
4205 | + * value exists, a default value is used. The final value is stored | ||
4206 | + * in a variable in the adapter structure. | ||
4207 | + **/ | ||
4208 | +void __devinit | ||
4209 | +atl2_check_options(struct atl2_adapter *adapter) | ||
4210 | +{ | ||
4211 | + int val; | ||
4212 | + struct atl2_option opt; | ||
4213 | + int bd = adapter->bd_number; | ||
4214 | + if(bd >= ATL2_MAX_NIC) { | ||
4215 | + printk(KERN_NOTICE "Warning: no configuration for board #%i\n", bd); | ||
4216 | + printk(KERN_NOTICE "Using defaults for all values\n"); | ||
4217 | +#ifndef module_param_array | ||
4218 | + bd = ATL2_MAX_NIC; | ||
4219 | +#endif | ||
4220 | + } | ||
4221 | + | ||
4222 | + /* Bytes of Transmit Memory */ | ||
4223 | + opt.type = range_option; | ||
4224 | + opt.name = "Bytes of Transmit Memory"; | ||
4225 | + opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_TX_MEMSIZE); | ||
4226 | + opt.def = ATL2_DEFAULT_TX_MEMSIZE; | ||
4227 | + opt.arg.r.min = ATL2_MIN_TX_MEMSIZE; | ||
4228 | + opt.arg.r.max = ATL2_MAX_TX_MEMSIZE; | ||
4229 | +#ifdef module_param_array | ||
4230 | + if(num_TxMemSize > bd) { | ||
4231 | +#endif | ||
4232 | + val = TxMemSize[bd]; | ||
4233 | + atl2_validate_option(&val, &opt); | ||
4234 | + adapter->txd_ring_size = ((u32) val) * 1024; | ||
4235 | +#ifdef module_param_array | ||
4236 | + } else { | ||
4237 | + adapter->txd_ring_size = ((u32)opt.def) * 1024; | ||
4238 | + } | ||
4239 | +#endif | ||
4240 | + // txs ring size: | ||
4241 | + adapter->txs_ring_size = adapter->txd_ring_size / 128; | ||
4242 | + if (adapter->txs_ring_size > 160) | ||
4243 | + adapter->txs_ring_size = 160; | ||
4244 | + | ||
4245 | + /* Receive Memory Block Count */ | ||
4246 | + opt.type = range_option; | ||
4247 | + opt.name = "Number of receive memory block"; | ||
4248 | + opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_RXD_COUNT); | ||
4249 | + opt.def = ATL2_DEFAULT_RXD_COUNT; | ||
4250 | + opt.arg.r.min = ATL2_MIN_RXD_COUNT; | ||
4251 | + opt.arg.r.max = ATL2_MAX_RXD_COUNT; | ||
4252 | +#ifdef module_param_array | ||
4253 | + if(num_RxMemBlock > bd) { | ||
4254 | +#endif | ||
4255 | + val = RxMemBlock[bd]; | ||
4256 | + atl2_validate_option(&val, &opt); | ||
4257 | + adapter->rxd_ring_size = (u32)val; //((u16)val)&~1; // even number | ||
4258 | +#ifdef module_param_array | ||
4259 | + } else { | ||
4260 | + adapter->rxd_ring_size = (u32)opt.def; | ||
4261 | + } | ||
4262 | +#endif | ||
4263 | + // init RXD Flow control value | ||
4264 | + adapter->hw.fc_rxd_hi = (adapter->rxd_ring_size/8)*7; | ||
4265 | + adapter->hw.fc_rxd_lo = (ATL2_MIN_RXD_COUNT/8) > (adapter->rxd_ring_size/12) ? | ||
4266 | + (ATL2_MIN_RXD_COUNT/8) : (adapter->rxd_ring_size/12); | ||
4267 | + | ||
4268 | + /* Interrupt Moderate Timer */ | ||
4269 | + opt.type = range_option; | ||
4270 | + opt.name = "Interrupt Moderate Timer"; | ||
4271 | + opt.err = "using default of " __MODULE_STRING(INT_MOD_DEFAULT_CNT); | ||
4272 | + opt.def = INT_MOD_DEFAULT_CNT; | ||
4273 | + opt.arg.r.min = INT_MOD_MIN_CNT; | ||
4274 | + opt.arg.r.max = INT_MOD_MAX_CNT; | ||
4275 | +#ifdef module_param_array | ||
4276 | + if(num_IntModTimer > bd) { | ||
4277 | +#endif | ||
4278 | + val = IntModTimer[bd]; | ||
4279 | + atl2_validate_option(&val, &opt); | ||
4280 | + adapter->imt = (u16) val; | ||
4281 | +#ifdef module_param_array | ||
4282 | + } else { | ||
4283 | + adapter->imt = (u16)(opt.def); | ||
4284 | + } | ||
4285 | +#endif | ||
4286 | + /* Flash Vendor */ | ||
4287 | + opt.type = range_option; | ||
4288 | + opt.name = "SPI Flash Vendor"; | ||
4289 | + opt.err = "using default of " __MODULE_STRING(FLASH_VENDOR_DEFAULT); | ||
4290 | + opt.def = FLASH_VENDOR_DEFAULT; | ||
4291 | + opt.arg.r.min = FLASH_VENDOR_MIN; | ||
4292 | + opt.arg.r.max = FLASH_VENDOR_MAX; | ||
4293 | +#ifdef module_param_array | ||
4294 | + if(num_FlashVendor > bd) { | ||
4295 | +#endif | ||
4296 | + val = FlashVendor[bd]; | ||
4297 | + atl2_validate_option(&val, &opt); | ||
4298 | + adapter->hw.flash_vendor = (u8) val; | ||
4299 | +#ifdef module_param_array | ||
4300 | + } else { | ||
4301 | + adapter->hw.flash_vendor = (u8)(opt.def); | ||
4302 | + } | ||
4303 | +#endif | ||
4304 | + /* MediaType */ | ||
4305 | + opt.type = range_option; | ||
4306 | + opt.name = "Speed/Duplex Selection"; | ||
4307 | + opt.err = "using default of " __MODULE_STRING(MEDIA_TYPE_AUTO_SENSOR); | ||
4308 | + opt.def = MEDIA_TYPE_AUTO_SENSOR; | ||
4309 | + opt.arg.r.min = MEDIA_TYPE_AUTO_SENSOR; | ||
4310 | + opt.arg.r.max = MEDIA_TYPE_10M_HALF; | ||
4311 | +#ifdef module_param_array | ||
4312 | + if(num_MediaType > bd) { | ||
4313 | +#endif | ||
4314 | + val = MediaType[bd]; | ||
4315 | + atl2_validate_option(&val, &opt); | ||
4316 | + adapter->hw.MediaType = (u16) val; | ||
4317 | +#ifdef module_param_array | ||
4318 | + } else { | ||
4319 | + adapter->hw.MediaType = (u16)(opt.def); | ||
4320 | + } | ||
4321 | +#endif | ||
4322 | +} | ||
4323 | diff -Nurp a/drivers/net/atl2/Makefile b/drivers/net/atl2/Makefile | ||
4324 | --- a/drivers/net/atl2/Makefile 1969-12-31 19:00:00.000000000 -0500 | ||
4325 | +++ b/drivers/net/atl2/Makefile 2008-01-31 14:37:35.000000000 -0500 | ||
4326 | @@ -0,0 +1,2 @@ | ||
4327 | +obj-$(CONFIG_ATL2) += atl2.o | ||
4328 | +atl2-y += atl2_main.o atl2_hw.o atl2_ethtool.o atl2_param.o | ||
4329 | diff -Nurp a/drivers/net/Kconfig b/drivers/net/Kconfig | ||
4330 | --- a/drivers/net/Kconfig 2008-01-31 14:32:05.000000000 -0500 | ||
4331 | +++ b/drivers/net/Kconfig 2008-01-31 14:44:01.000000000 -0500 | ||
4332 | @@ -1999,6 +1999,17 @@ config NE_H8300 | ||
4333 | Say Y here if you want to use the NE2000 compatible | ||
4334 | controller on the Renesas H8/300 processor. | ||
4335 | |||
4336 | +config ATL2 | ||
4337 | + tristate "Atheros L2 Fast Ethernet support (EXPERIMENTAL)" | ||
4338 | + depends on PCI && EXPERIMENTAL | ||
4339 | + select CRC32 | ||
4340 | + select MII | ||
4341 | + help | ||
4342 | + This driver supports the Atheros L2 fast ethernet adapter. | ||
4343 | + | ||
4344 | + To compile this driver as a module, choose M here. The module | ||
4345 | + will be called atl2. | ||
4346 | + | ||
4347 | source "drivers/net/fec_8xx/Kconfig" | ||
4348 | source "drivers/net/fs_enet/Kconfig" | ||
4349 | |||
4350 | diff -Nurp a/drivers/net/Makefile b/drivers/net/Makefile | ||
4351 | --- a/drivers/net/Makefile 2008-01-31 14:32:05.000000000 -0500 | ||
4352 | +++ b/drivers/net/Makefile 2008-01-31 14:38:52.000000000 -0500 | ||
4353 | @@ -11,6 +11,7 @@ obj-$(CONFIG_CHELSIO_T3) += cxgb3/ | ||
4354 | obj-$(CONFIG_EHEA) += ehea/ | ||
4355 | obj-$(CONFIG_BONDING) += bonding/ | ||
4356 | obj-$(CONFIG_ATL1) += atl1/ | ||
4357 | +obj-$(CONFIG_ATL2) += atl2/ | ||
4358 | obj-$(CONFIG_GIANFAR) += gianfar_driver.o | ||
4359 | |||
4360 | gianfar_driver-objs := gianfar.o \ |