diff -uNr xc/programs/Xserver/hw/xfree86/vgahw/vgaHW.c.orig xc/programs/Xserver/hw/xfree86/vgahw/vgaHW.c
--- xc/programs/Xserver/hw/xfree86/vgahw/vgaHW.c.orig	Tue Aug 13 17:27:10 2002
+++ xc/programs/Xserver/hw/xfree86/vgahw/vgaHW.c	Thu Aug 15 10:18:31 2002
@@ -157,12 +157,14 @@
 {
     outb(hwp->IOBase + hwp->PIOOffset + VGA_CRTC_INDEX_OFFSET, index);
     outb(hwp->IOBase + hwp->PIOOffset + VGA_CRTC_DATA_OFFSET, value);
+    write_mem_barrier();
 }
 
 static CARD8
 stdReadCrtc(vgaHWPtr hwp, CARD8 index)
 {
     outb(hwp->IOBase + hwp->PIOOffset + VGA_CRTC_INDEX_OFFSET, index);
+    write_mem_barrier();
     return inb(hwp->IOBase + hwp->PIOOffset + VGA_CRTC_DATA_OFFSET);
 }
 
@@ -171,12 +177,14 @@
 {
     outb(hwp->PIOOffset + VGA_GRAPH_INDEX, index);
     outb(hwp->PIOOffset + VGA_GRAPH_DATA, value);
+    write_mem_barrier();
 }
 
 static CARD8
 stdReadGr(vgaHWPtr hwp, CARD8 index)
 {
     outb(hwp->PIOOffset + VGA_GRAPH_INDEX, index);
+    write_mem_barrier();
     return inb(hwp->PIOOffset + VGA_GRAPH_DATA);
 }
 
@@ -185,12 +197,14 @@
 {
     outb(hwp->PIOOffset + VGA_SEQ_INDEX, index);
     outb(hwp->PIOOffset + VGA_SEQ_DATA, value);
+    write_mem_barrier();
 }
 
 static CARD8
 stdReadSeq(vgaHWPtr hwp, CARD8 index)
 {
     outb(hwp->PIOOffset + VGA_SEQ_INDEX, index);
+    write_mem_barrier();
     return inb(hwp->PIOOffset + VGA_SEQ_DATA);
 }
 
@@ -216,6 +234,7 @@
 stdWriteFCR(vgaHWPtr hwp, CARD8 value)
 {
     outb(hwp->IOBase + hwp->PIOOffset + VGA_FEATURE_W_OFFSET,value);
+    write_mem_barrier();
 }
 
 static void
@@ -231,6 +252,7 @@
     tmp = inb(hwp->IOBase + hwp->PIOOffset + VGA_IN_STAT_1_OFFSET);
     outb(hwp->PIOOffset + VGA_ATTR_INDEX, index);
     outb(hwp->PIOOffset + VGA_ATTR_DATA_W, value);
+    write_mem_barrier();
 }
 
 static CARD8
@@ -245,6 +269,7 @@
 
     tmp = inb(hwp->IOBase + hwp->PIOOffset + VGA_IN_STAT_1_OFFSET);
     outb(hwp->PIOOffset + VGA_ATTR_INDEX, index);
+    write_mem_barrier();
     return inb(hwp->PIOOffset + VGA_ATTR_DATA_R);
 }
 
@@ -252,6 +279,7 @@
 stdWriteMiscOut(vgaHWPtr hwp, CARD8 value)
 {
     outb(hwp->PIOOffset + VGA_MISC_OUT_W, value);
+    write_mem_barrier();
 }
 
 static CARD8
@@ -267,6 +297,7 @@
 
     tmp = inb(hwp->IOBase + hwp->PIOOffset + VGA_IN_STAT_1_OFFSET);
     outb(hwp->PIOOffset + VGA_ATTR_INDEX, 0x00);
+    write_mem_barrier();
     hwp->paletteEnabled = TRUE;
 }
 
@@ -277,6 +310,7 @@
 
     tmp = inb(hwp->IOBase + hwp->PIOOffset + VGA_IN_STAT_1_OFFSET);
     outb(hwp->PIOOffset + VGA_ATTR_INDEX, 0x20);
+    write_mem_barrier();
     hwp->paletteEnabled = FALSE;
 }
 
@@ -284,6 +320,7 @@
 stdWriteDacMask(vgaHWPtr hwp, CARD8 value)
 {
     outb(hwp->PIOOffset + VGA_DAC_MASK, value);
+    write_mem_barrier();
 }
 
 static CARD8
@@ -296,18 +335,21 @@
 stdWriteDacReadAddr(vgaHWPtr hwp, CARD8 value)
 {
     outb(hwp->PIOOffset + VGA_DAC_READ_ADDR, value);
+    write_mem_barrier();
 }
 
 static void
 stdWriteDacWriteAddr(vgaHWPtr hwp, CARD8 value)
 {
     outb(hwp->PIOOffset + VGA_DAC_WRITE_ADDR, value);
+    write_mem_barrier();
 }
 
 static void
 stdWriteDacData(vgaHWPtr hwp, CARD8 value)
 {
     outb(hwp->PIOOffset + VGA_DAC_DATA, value);
+    write_mem_barrier();
 }
 
 static CARD8
@@ -326,6 +374,7 @@
 stdWriteEnable(vgaHWPtr hwp, CARD8 value)
 {
     outb(hwp->PIOOffset + VGA_ENABLE, value);
+    write_mem_barrier();
 }
 
 void
@@ -372,12 +423,14 @@
 {
     moutb(hwp->IOBase + VGA_CRTC_INDEX_OFFSET, index);
     moutb(hwp->IOBase + VGA_CRTC_DATA_OFFSET, value);
+    write_mem_barrier();
 }
 
 static CARD8
 mmioReadCrtc(vgaHWPtr hwp, CARD8 index)
 {
     moutb(hwp->IOBase + VGA_CRTC_INDEX_OFFSET, index);
+    write_mem_barrier();
     return minb(hwp->IOBase + VGA_CRTC_DATA_OFFSET);
 }
 
@@ -386,12 +443,14 @@
 {
     moutb(VGA_GRAPH_INDEX, index);
     moutb(VGA_GRAPH_DATA, value);
+    write_mem_barrier();
 }
 
 static CARD8
 mmioReadGr(vgaHWPtr hwp, CARD8 index)
 {
     moutb(VGA_GRAPH_INDEX, index);
+    write_mem_barrier();
     return minb(VGA_GRAPH_DATA);
 }
 
@@ -400,12 +463,14 @@
 {
     moutb(VGA_SEQ_INDEX, index);
     moutb(VGA_SEQ_DATA, value);
+    write_mem_barrier();
 }
 
 static CARD8
 mmioReadSeq(vgaHWPtr hwp, CARD8 index)
 {
     moutb(VGA_SEQ_INDEX, index);
+    write_mem_barrier();
     return minb(VGA_SEQ_DATA);
 }
 
@@ -431,6 +500,7 @@
 mmioWriteFCR(vgaHWPtr hwp, CARD8 value)
 {
     moutb(hwp->IOBase + VGA_FEATURE_W_OFFSET,value);
+    write_mem_barrier();
 }
 
 static void
@@ -446,6 +518,7 @@
     tmp = minb(hwp->IOBase + VGA_IN_STAT_1_OFFSET);
     moutb(VGA_ATTR_INDEX, index);
     moutb(VGA_ATTR_DATA_W, value);
+    write_mem_barrier();
 }
 
 static CARD8
@@ -460,6 +535,7 @@
 
     tmp = minb(hwp->IOBase + VGA_IN_STAT_1_OFFSET);
     moutb(VGA_ATTR_INDEX, index);
+    write_mem_barrier();
     return minb(VGA_ATTR_DATA_R);
 }
 
@@ -467,6 +545,7 @@
 mmioWriteMiscOut(vgaHWPtr hwp, CARD8 value)
 {
     moutb(VGA_MISC_OUT_W, value);
+    write_mem_barrier();
 }
 
 static CARD8
@@ -482,6 +563,7 @@
 
     tmp = minb(hwp->IOBase + VGA_IN_STAT_1_OFFSET);
     moutb(VGA_ATTR_INDEX, 0x00);
+    write_mem_barrier();
     hwp->paletteEnabled = TRUE;
 }
 
@@ -492,6 +576,7 @@
 
     tmp = minb(hwp->IOBase + VGA_IN_STAT_1_OFFSET);
     moutb(VGA_ATTR_INDEX, 0x20);
+    write_mem_barrier();
     hwp->paletteEnabled = FALSE;
 }
 
@@ -499,6 +586,7 @@
 mmioWriteDacMask(vgaHWPtr hwp, CARD8 value)
 {
     moutb(VGA_DAC_MASK, value);
+    write_mem_barrier();
 }
 
 static CARD8
@@ -511,18 +601,21 @@
 mmioWriteDacReadAddr(vgaHWPtr hwp, CARD8 value)
 {
     moutb(VGA_DAC_READ_ADDR, value);
+    write_mem_barrier();
 }
 
 static void
 mmioWriteDacWriteAddr(vgaHWPtr hwp, CARD8 value)
 {
     moutb(VGA_DAC_WRITE_ADDR, value);
+    write_mem_barrier();
 }
 
 static void
 mmioWriteDacData(vgaHWPtr hwp, CARD8 value)
 {
     moutb(VGA_DAC_DATA, value);
+    write_mem_barrier();
 }
 
 static CARD8
@@ -541,6 +640,7 @@
 mmioWriteEnable(vgaHWPtr hwp, CARD8 value)
 {
     moutb(VGA_ENABLE, value);
+    write_mem_barrier();
 }
 
 void