Contents of /trunk/xorg-old/patches-6.9.0-r1/7000_all_4.1.0-ia64-hp-vgaHW-memory-barrier2.patch
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Revision 167 -
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Tue May 8 20:58:51 2007 UTC (17 years, 4 months ago) by niro
File size: 6008 byte(s)
Tue May 8 20:58:51 2007 UTC (17 years, 4 months ago) by niro
File size: 6008 byte(s)
-import
1 | diff -uNr xc/programs/Xserver/hw/xfree86/vgahw/vgaHW.c.orig xc/programs/Xserver/hw/xfree86/vgahw/vgaHW.c |
2 | --- xc/programs/Xserver/hw/xfree86/vgahw/vgaHW.c.orig Tue Aug 13 17:27:10 2002 |
3 | +++ xc/programs/Xserver/hw/xfree86/vgahw/vgaHW.c Thu Aug 15 10:18:31 2002 |
4 | @@ -157,12 +157,14 @@ |
5 | { |
6 | outb(hwp->IOBase + hwp->PIOOffset + VGA_CRTC_INDEX_OFFSET, index); |
7 | outb(hwp->IOBase + hwp->PIOOffset + VGA_CRTC_DATA_OFFSET, value); |
8 | + write_mem_barrier(); |
9 | } |
10 | |
11 | static CARD8 |
12 | stdReadCrtc(vgaHWPtr hwp, CARD8 index) |
13 | { |
14 | outb(hwp->IOBase + hwp->PIOOffset + VGA_CRTC_INDEX_OFFSET, index); |
15 | + write_mem_barrier(); |
16 | return inb(hwp->IOBase + hwp->PIOOffset + VGA_CRTC_DATA_OFFSET); |
17 | } |
18 | |
19 | @@ -171,12 +177,14 @@ |
20 | { |
21 | outb(hwp->PIOOffset + VGA_GRAPH_INDEX, index); |
22 | outb(hwp->PIOOffset + VGA_GRAPH_DATA, value); |
23 | + write_mem_barrier(); |
24 | } |
25 | |
26 | static CARD8 |
27 | stdReadGr(vgaHWPtr hwp, CARD8 index) |
28 | { |
29 | outb(hwp->PIOOffset + VGA_GRAPH_INDEX, index); |
30 | + write_mem_barrier(); |
31 | return inb(hwp->PIOOffset + VGA_GRAPH_DATA); |
32 | } |
33 | |
34 | @@ -185,12 +197,14 @@ |
35 | { |
36 | outb(hwp->PIOOffset + VGA_SEQ_INDEX, index); |
37 | outb(hwp->PIOOffset + VGA_SEQ_DATA, value); |
38 | + write_mem_barrier(); |
39 | } |
40 | |
41 | static CARD8 |
42 | stdReadSeq(vgaHWPtr hwp, CARD8 index) |
43 | { |
44 | outb(hwp->PIOOffset + VGA_SEQ_INDEX, index); |
45 | + write_mem_barrier(); |
46 | return inb(hwp->PIOOffset + VGA_SEQ_DATA); |
47 | } |
48 | |
49 | @@ -216,6 +234,7 @@ |
50 | stdWriteFCR(vgaHWPtr hwp, CARD8 value) |
51 | { |
52 | outb(hwp->IOBase + hwp->PIOOffset + VGA_FEATURE_W_OFFSET,value); |
53 | + write_mem_barrier(); |
54 | } |
55 | |
56 | static void |
57 | @@ -231,6 +252,7 @@ |
58 | tmp = inb(hwp->IOBase + hwp->PIOOffset + VGA_IN_STAT_1_OFFSET); |
59 | outb(hwp->PIOOffset + VGA_ATTR_INDEX, index); |
60 | outb(hwp->PIOOffset + VGA_ATTR_DATA_W, value); |
61 | + write_mem_barrier(); |
62 | } |
63 | |
64 | static CARD8 |
65 | @@ -245,6 +269,7 @@ |
66 | |
67 | tmp = inb(hwp->IOBase + hwp->PIOOffset + VGA_IN_STAT_1_OFFSET); |
68 | outb(hwp->PIOOffset + VGA_ATTR_INDEX, index); |
69 | + write_mem_barrier(); |
70 | return inb(hwp->PIOOffset + VGA_ATTR_DATA_R); |
71 | } |
72 | |
73 | @@ -252,6 +279,7 @@ |
74 | stdWriteMiscOut(vgaHWPtr hwp, CARD8 value) |
75 | { |
76 | outb(hwp->PIOOffset + VGA_MISC_OUT_W, value); |
77 | + write_mem_barrier(); |
78 | } |
79 | |
80 | static CARD8 |
81 | @@ -267,6 +297,7 @@ |
82 | |
83 | tmp = inb(hwp->IOBase + hwp->PIOOffset + VGA_IN_STAT_1_OFFSET); |
84 | outb(hwp->PIOOffset + VGA_ATTR_INDEX, 0x00); |
85 | + write_mem_barrier(); |
86 | hwp->paletteEnabled = TRUE; |
87 | } |
88 | |
89 | @@ -277,6 +310,7 @@ |
90 | |
91 | tmp = inb(hwp->IOBase + hwp->PIOOffset + VGA_IN_STAT_1_OFFSET); |
92 | outb(hwp->PIOOffset + VGA_ATTR_INDEX, 0x20); |
93 | + write_mem_barrier(); |
94 | hwp->paletteEnabled = FALSE; |
95 | } |
96 | |
97 | @@ -284,6 +320,7 @@ |
98 | stdWriteDacMask(vgaHWPtr hwp, CARD8 value) |
99 | { |
100 | outb(hwp->PIOOffset + VGA_DAC_MASK, value); |
101 | + write_mem_barrier(); |
102 | } |
103 | |
104 | static CARD8 |
105 | @@ -296,18 +335,21 @@ |
106 | stdWriteDacReadAddr(vgaHWPtr hwp, CARD8 value) |
107 | { |
108 | outb(hwp->PIOOffset + VGA_DAC_READ_ADDR, value); |
109 | + write_mem_barrier(); |
110 | } |
111 | |
112 | static void |
113 | stdWriteDacWriteAddr(vgaHWPtr hwp, CARD8 value) |
114 | { |
115 | outb(hwp->PIOOffset + VGA_DAC_WRITE_ADDR, value); |
116 | + write_mem_barrier(); |
117 | } |
118 | |
119 | static void |
120 | stdWriteDacData(vgaHWPtr hwp, CARD8 value) |
121 | { |
122 | outb(hwp->PIOOffset + VGA_DAC_DATA, value); |
123 | + write_mem_barrier(); |
124 | } |
125 | |
126 | static CARD8 |
127 | @@ -326,6 +374,7 @@ |
128 | stdWriteEnable(vgaHWPtr hwp, CARD8 value) |
129 | { |
130 | outb(hwp->PIOOffset + VGA_ENABLE, value); |
131 | + write_mem_barrier(); |
132 | } |
133 | |
134 | void |
135 | @@ -372,12 +423,14 @@ |
136 | { |
137 | moutb(hwp->IOBase + VGA_CRTC_INDEX_OFFSET, index); |
138 | moutb(hwp->IOBase + VGA_CRTC_DATA_OFFSET, value); |
139 | + write_mem_barrier(); |
140 | } |
141 | |
142 | static CARD8 |
143 | mmioReadCrtc(vgaHWPtr hwp, CARD8 index) |
144 | { |
145 | moutb(hwp->IOBase + VGA_CRTC_INDEX_OFFSET, index); |
146 | + write_mem_barrier(); |
147 | return minb(hwp->IOBase + VGA_CRTC_DATA_OFFSET); |
148 | } |
149 | |
150 | @@ -386,12 +443,14 @@ |
151 | { |
152 | moutb(VGA_GRAPH_INDEX, index); |
153 | moutb(VGA_GRAPH_DATA, value); |
154 | + write_mem_barrier(); |
155 | } |
156 | |
157 | static CARD8 |
158 | mmioReadGr(vgaHWPtr hwp, CARD8 index) |
159 | { |
160 | moutb(VGA_GRAPH_INDEX, index); |
161 | + write_mem_barrier(); |
162 | return minb(VGA_GRAPH_DATA); |
163 | } |
164 | |
165 | @@ -400,12 +463,14 @@ |
166 | { |
167 | moutb(VGA_SEQ_INDEX, index); |
168 | moutb(VGA_SEQ_DATA, value); |
169 | + write_mem_barrier(); |
170 | } |
171 | |
172 | static CARD8 |
173 | mmioReadSeq(vgaHWPtr hwp, CARD8 index) |
174 | { |
175 | moutb(VGA_SEQ_INDEX, index); |
176 | + write_mem_barrier(); |
177 | return minb(VGA_SEQ_DATA); |
178 | } |
179 | |
180 | @@ -431,6 +500,7 @@ |
181 | mmioWriteFCR(vgaHWPtr hwp, CARD8 value) |
182 | { |
183 | moutb(hwp->IOBase + VGA_FEATURE_W_OFFSET,value); |
184 | + write_mem_barrier(); |
185 | } |
186 | |
187 | static void |
188 | @@ -446,6 +518,7 @@ |
189 | tmp = minb(hwp->IOBase + VGA_IN_STAT_1_OFFSET); |
190 | moutb(VGA_ATTR_INDEX, index); |
191 | moutb(VGA_ATTR_DATA_W, value); |
192 | + write_mem_barrier(); |
193 | } |
194 | |
195 | static CARD8 |
196 | @@ -460,6 +535,7 @@ |
197 | |
198 | tmp = minb(hwp->IOBase + VGA_IN_STAT_1_OFFSET); |
199 | moutb(VGA_ATTR_INDEX, index); |
200 | + write_mem_barrier(); |
201 | return minb(VGA_ATTR_DATA_R); |
202 | } |
203 | |
204 | @@ -467,6 +545,7 @@ |
205 | mmioWriteMiscOut(vgaHWPtr hwp, CARD8 value) |
206 | { |
207 | moutb(VGA_MISC_OUT_W, value); |
208 | + write_mem_barrier(); |
209 | } |
210 | |
211 | static CARD8 |
212 | @@ -482,6 +563,7 @@ |
213 | |
214 | tmp = minb(hwp->IOBase + VGA_IN_STAT_1_OFFSET); |
215 | moutb(VGA_ATTR_INDEX, 0x00); |
216 | + write_mem_barrier(); |
217 | hwp->paletteEnabled = TRUE; |
218 | } |
219 | |
220 | @@ -492,6 +576,7 @@ |
221 | |
222 | tmp = minb(hwp->IOBase + VGA_IN_STAT_1_OFFSET); |
223 | moutb(VGA_ATTR_INDEX, 0x20); |
224 | + write_mem_barrier(); |
225 | hwp->paletteEnabled = FALSE; |
226 | } |
227 | |
228 | @@ -499,6 +586,7 @@ |
229 | mmioWriteDacMask(vgaHWPtr hwp, CARD8 value) |
230 | { |
231 | moutb(VGA_DAC_MASK, value); |
232 | + write_mem_barrier(); |
233 | } |
234 | |
235 | static CARD8 |
236 | @@ -511,18 +601,21 @@ |
237 | mmioWriteDacReadAddr(vgaHWPtr hwp, CARD8 value) |
238 | { |
239 | moutb(VGA_DAC_READ_ADDR, value); |
240 | + write_mem_barrier(); |
241 | } |
242 | |
243 | static void |
244 | mmioWriteDacWriteAddr(vgaHWPtr hwp, CARD8 value) |
245 | { |
246 | moutb(VGA_DAC_WRITE_ADDR, value); |
247 | + write_mem_barrier(); |
248 | } |
249 | |
250 | static void |
251 | mmioWriteDacData(vgaHWPtr hwp, CARD8 value) |
252 | { |
253 | moutb(VGA_DAC_DATA, value); |
254 | + write_mem_barrier(); |
255 | } |
256 | |
257 | static CARD8 |
258 | @@ -541,6 +640,7 @@ |
259 | mmioWriteEnable(vgaHWPtr hwp, CARD8 value) |
260 | { |
261 | moutb(VGA_ENABLE, value); |
262 | + write_mem_barrier(); |
263 | } |
264 | |
265 | void |